git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 54647cd003c08b714474a5b599a147ec6a160486 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Sun, 20 Mar 2022 18:00:01 +0800
   4 Subject: [PATCH 5/5] mtd: spinand: gigadevice: add support for GD5FxGM7xExxG
   5
   6 Add support for:
   7  GD5F{1,2}GM7{U,R}ExxG
   8  GD5F4GM8{U,R}ExxG
   9
  10 These are new 27nm counterparts for the GD5FxGQ4 chips from GigaDevice
  11 with 8b/512b on-die ECC capability.
  12 These chips (and currently supported GD5FxGQ5 chips) have QIO DTR
  13 instruction for reading page cache. It isn't added in this patch because
  14 I don't have a DTR spi controller for testing.
  15
  16 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  17 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  18 Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-6-gch981213@gmail.com
  19 ---
  20  drivers/mtd/nand/spi/gigadevice.c | 60 +++++++++++++++++++++++++++++++
  21  1 file changed, 60 insertions(+)
  22
  23 --- a/drivers/mtd/nand/spi/gigadevice.c
  24 +++ b/drivers/mtd/nand/spi/gigadevice.c
  25 @@ -441,6 +441,66 @@ static const struct spinand_info gigadev
  26                      SPINAND_HAS_QE_BIT,
  27                      SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  28                                      gd5fxgq5xexxg_ecc_get_status)),
  29 +       SPINAND_INFO("GD5F1GM7UExxG",
  30 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
  31 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
  32 +                    NAND_ECCREQ(8, 512),
  33 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  34 +                                             &write_cache_variants,
  35 +                                             &update_cache_variants),
  36 +                    SPINAND_HAS_QE_BIT,
  37 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  38 +                                    gd5fxgq4uexxg_ecc_get_status)),
  39 +       SPINAND_INFO("GD5F1GM7RExxG",
  40 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
  41 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
  42 +                    NAND_ECCREQ(8, 512),
  43 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  44 +                                             &write_cache_variants,
  45 +                                             &update_cache_variants),
  46 +                    SPINAND_HAS_QE_BIT,
  47 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  48 +                                    gd5fxgq4uexxg_ecc_get_status)),
  49 +       SPINAND_INFO("GD5F2GM7UExxG",
  50 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
  51 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  52 +                    NAND_ECCREQ(8, 512),
  53 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  54 +                                             &write_cache_variants,
  55 +                                             &update_cache_variants),
  56 +                    SPINAND_HAS_QE_BIT,
  57 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  58 +                                    gd5fxgq4uexxg_ecc_get_status)),
  59 +       SPINAND_INFO("GD5F2GM7RExxG",
  60 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
  61 +                    NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
  62 +                    NAND_ECCREQ(8, 512),
  63 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  64 +                                             &write_cache_variants,
  65 +                                             &update_cache_variants),
  66 +                    SPINAND_HAS_QE_BIT,
  67 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  68 +                                    gd5fxgq4uexxg_ecc_get_status)),
  69 +       SPINAND_INFO("GD5F4GM8UExxG",
  70 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
  71 +                    NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
  72 +                    NAND_ECCREQ(8, 512),
  73 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  74 +                                             &write_cache_variants,
  75 +                                             &update_cache_variants),
  76 +                    SPINAND_HAS_QE_BIT,
  77 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  78 +                                    gd5fxgq4uexxg_ecc_get_status)),
  79 +       SPINAND_INFO("GD5F4GM8RExxG",
  80 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
  81 +                    NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1),
  82 +                    NAND_ECCREQ(8, 512),
  83 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
  84 +                                             &write_cache_variants,
  85 +                                             &update_cache_variants),
  86 +                    SPINAND_HAS_QE_BIT,
  87 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
  88 +                                    gd5fxgq4uexxg_ecc_get_status)),
  89  };
  90
  91  static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {