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1 From b3f2f10693aadeacf83ab5be03810941a4b77612 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Tue, 14 Aug 2018 17:42:21 +0530
4 Subject: [PATCH 02/12] clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
5
6 HFPLLs are the main frequency source for Krait CPU clocks. Add
7 support for changing the rate of these PLLs.
8
9 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
10 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
11 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
12 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
13 ---
14 drivers/clk/qcom/Makefile | 1 +
15 drivers/clk/qcom/clk-hfpll.c | 244 +++++++++++++++++++++++++++++++++++
16 drivers/clk/qcom/clk-hfpll.h | 44 +++++++
17 3 files changed, 289 insertions(+)
18 create mode 100644 drivers/clk/qcom/clk-hfpll.c
19 create mode 100644 drivers/clk/qcom/clk-hfpll.h
20
21 --- a/drivers/clk/qcom/Makefile
22 +++ b/drivers/clk/qcom/Makefile
23 @@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
24 clk-qcom-y += clk-regmap-divider.o
25 clk-qcom-y += clk-regmap-mux.o
26 clk-qcom-y += clk-regmap-mux-div.o
27 +clk-qcom-y += clk-hfpll.o
28 clk-qcom-y += reset.o
29 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
30
31 --- /dev/null
32 +++ b/drivers/clk/qcom/clk-hfpll.c
33 @@ -0,0 +1,244 @@
34 +// SPDX-License-Identifier: GPL-2.0
35 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
36 +
37 +#include <linux/kernel.h>
38 +#include <linux/export.h>
39 +#include <linux/regmap.h>
40 +#include <linux/delay.h>
41 +#include <linux/err.h>
42 +#include <linux/clk-provider.h>
43 +#include <linux/spinlock.h>
44 +
45 +#include "clk-regmap.h"
46 +#include "clk-hfpll.h"
47 +
48 +#define PLL_OUTCTRL BIT(0)
49 +#define PLL_BYPASSNL BIT(1)
50 +#define PLL_RESET_N BIT(2)
51 +
52 +/* Initialize a HFPLL at a given rate and enable it. */
53 +static void __clk_hfpll_init_once(struct clk_hw *hw)
54 +{
55 + struct clk_hfpll *h = to_clk_hfpll(hw);
56 + struct hfpll_data const *hd = h->d;
57 + struct regmap *regmap = h->clkr.regmap;
58 +
59 + if (likely(h->init_done))
60 + return;
61 +
62 + /* Configure PLL parameters for integer mode. */
63 + if (hd->config_val)
64 + regmap_write(regmap, hd->config_reg, hd->config_val);
65 + regmap_write(regmap, hd->m_reg, 0);
66 + regmap_write(regmap, hd->n_reg, 1);
67 +
68 + if (hd->user_reg) {
69 + u32 regval = hd->user_val;
70 + unsigned long rate;
71 +
72 + rate = clk_hw_get_rate(hw);
73 +
74 + /* Pick the right VCO. */
75 + if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
76 + regval |= hd->user_vco_mask;
77 + regmap_write(regmap, hd->user_reg, regval);
78 + }
79 +
80 + if (hd->droop_reg)
81 + regmap_write(regmap, hd->droop_reg, hd->droop_val);
82 +
83 + h->init_done = true;
84 +}
85 +
86 +static void __clk_hfpll_enable(struct clk_hw *hw)
87 +{
88 + struct clk_hfpll *h = to_clk_hfpll(hw);
89 + struct hfpll_data const *hd = h->d;
90 + struct regmap *regmap = h->clkr.regmap;
91 + u32 val;
92 +
93 + __clk_hfpll_init_once(hw);
94 +
95 + /* Disable PLL bypass mode. */
96 + regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
97 +
98 + /*
99 + * H/W requires a 5us delay between disabling the bypass and
100 + * de-asserting the reset. Delay 10us just to be safe.
101 + */
102 + udelay(10);
103 +
104 + /* De-assert active-low PLL reset. */
105 + regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
106 +
107 + /* Wait for PLL to lock. */
108 + if (hd->status_reg) {
109 + do {
110 + regmap_read(regmap, hd->status_reg, &val);
111 + } while (!(val & BIT(hd->lock_bit)));
112 + } else {
113 + udelay(60);
114 + }
115 +
116 + /* Enable PLL output. */
117 + regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
118 +}
119 +
120 +/* Enable an already-configured HFPLL. */
121 +static int clk_hfpll_enable(struct clk_hw *hw)
122 +{
123 + unsigned long flags;
124 + struct clk_hfpll *h = to_clk_hfpll(hw);
125 + struct hfpll_data const *hd = h->d;
126 + struct regmap *regmap = h->clkr.regmap;
127 + u32 mode;
128 +
129 + spin_lock_irqsave(&h->lock, flags);
130 + regmap_read(regmap, hd->mode_reg, &mode);
131 + if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
132 + __clk_hfpll_enable(hw);
133 + spin_unlock_irqrestore(&h->lock, flags);
134 +
135 + return 0;
136 +}
137 +
138 +static void __clk_hfpll_disable(struct clk_hfpll *h)
139 +{
140 + struct hfpll_data const *hd = h->d;
141 + struct regmap *regmap = h->clkr.regmap;
142 +
143 + /*
144 + * Disable the PLL output, disable test mode, enable the bypass mode,
145 + * and assert the reset.
146 + */
147 + regmap_update_bits(regmap, hd->mode_reg,
148 + PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
149 +}
150 +
151 +static void clk_hfpll_disable(struct clk_hw *hw)
152 +{
153 + struct clk_hfpll *h = to_clk_hfpll(hw);
154 + unsigned long flags;
155 +
156 + spin_lock_irqsave(&h->lock, flags);
157 + __clk_hfpll_disable(h);
158 + spin_unlock_irqrestore(&h->lock, flags);
159 +}
160 +
161 +static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
162 + unsigned long *parent_rate)
163 +{
164 + struct clk_hfpll *h = to_clk_hfpll(hw);
165 + struct hfpll_data const *hd = h->d;
166 + unsigned long rrate;
167 +
168 + rate = clamp(rate, hd->min_rate, hd->max_rate);
169 +
170 + rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
171 + if (rrate > hd->max_rate)
172 + rrate -= *parent_rate;
173 +
174 + return rrate;
175 +}
176 +
177 +/*
178 + * For optimization reasons, assumes no downstream clocks are actively using
179 + * it.
180 + */
181 +static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
182 + unsigned long parent_rate)
183 +{
184 + struct clk_hfpll *h = to_clk_hfpll(hw);
185 + struct hfpll_data const *hd = h->d;
186 + struct regmap *regmap = h->clkr.regmap;
187 + unsigned long flags;
188 + u32 l_val, val;
189 + bool enabled;
190 +
191 + l_val = rate / parent_rate;
192 +
193 + spin_lock_irqsave(&h->lock, flags);
194 +
195 + enabled = __clk_is_enabled(hw->clk);
196 + if (enabled)
197 + __clk_hfpll_disable(h);
198 +
199 + /* Pick the right VCO. */
200 + if (hd->user_reg && hd->user_vco_mask) {
201 + regmap_read(regmap, hd->user_reg, &val);
202 + if (rate <= hd->low_vco_max_rate)
203 + val &= ~hd->user_vco_mask;
204 + else
205 + val |= hd->user_vco_mask;
206 + regmap_write(regmap, hd->user_reg, val);
207 + }
208 +
209 + regmap_write(regmap, hd->l_reg, l_val);
210 +
211 + if (enabled)
212 + __clk_hfpll_enable(hw);
213 +
214 + spin_unlock_irqrestore(&h->lock, flags);
215 +
216 + return 0;
217 +}
218 +
219 +static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
220 + unsigned long parent_rate)
221 +{
222 + struct clk_hfpll *h = to_clk_hfpll(hw);
223 + struct hfpll_data const *hd = h->d;
224 + struct regmap *regmap = h->clkr.regmap;
225 + u32 l_val;
226 +
227 + regmap_read(regmap, hd->l_reg, &l_val);
228 +
229 + return l_val * parent_rate;
230 +}
231 +
232 +static void clk_hfpll_init(struct clk_hw *hw)
233 +{
234 + struct clk_hfpll *h = to_clk_hfpll(hw);
235 + struct hfpll_data const *hd = h->d;
236 + struct regmap *regmap = h->clkr.regmap;
237 + u32 mode, status;
238 +
239 + regmap_read(regmap, hd->mode_reg, &mode);
240 + if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
241 + __clk_hfpll_init_once(hw);
242 + return;
243 + }
244 +
245 + if (hd->status_reg) {
246 + regmap_read(regmap, hd->status_reg, &status);
247 + if (!(status & BIT(hd->lock_bit))) {
248 + WARN(1, "HFPLL %s is ON, but not locked!\n",
249 + __clk_get_name(hw->clk));
250 + clk_hfpll_disable(hw);
251 + __clk_hfpll_init_once(hw);
252 + }
253 + }
254 +}
255 +
256 +static int hfpll_is_enabled(struct clk_hw *hw)
257 +{
258 + struct clk_hfpll *h = to_clk_hfpll(hw);
259 + struct hfpll_data const *hd = h->d;
260 + struct regmap *regmap = h->clkr.regmap;
261 + u32 mode;
262 +
263 + regmap_read(regmap, hd->mode_reg, &mode);
264 + mode &= 0x7;
265 + return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
266 +}
267 +
268 +const struct clk_ops clk_ops_hfpll = {
269 + .enable = clk_hfpll_enable,
270 + .disable = clk_hfpll_disable,
271 + .is_enabled = hfpll_is_enabled,
272 + .round_rate = clk_hfpll_round_rate,
273 + .set_rate = clk_hfpll_set_rate,
274 + .recalc_rate = clk_hfpll_recalc_rate,
275 + .init = clk_hfpll_init,
276 +};
277 +EXPORT_SYMBOL_GPL(clk_ops_hfpll);
278 --- /dev/null
279 +++ b/drivers/clk/qcom/clk-hfpll.h
280 @@ -0,0 +1,44 @@
281 +/* SPDX-License-Identifier: GPL-2.0 */
282 +
283 +#ifndef __QCOM_CLK_HFPLL_H__
284 +#define __QCOM_CLK_HFPLL_H__
285 +
286 +#include <linux/clk-provider.h>
287 +#include <linux/spinlock.h>
288 +#include "clk-regmap.h"
289 +
290 +struct hfpll_data {
291 + u32 mode_reg;
292 + u32 l_reg;
293 + u32 m_reg;
294 + u32 n_reg;
295 + u32 user_reg;
296 + u32 droop_reg;
297 + u32 config_reg;
298 + u32 status_reg;
299 + u8 lock_bit;
300 +
301 + u32 droop_val;
302 + u32 config_val;
303 + u32 user_val;
304 + u32 user_vco_mask;
305 + unsigned long low_vco_max_rate;
306 +
307 + unsigned long min_rate;
308 + unsigned long max_rate;
309 +};
310 +
311 +struct clk_hfpll {
312 + struct hfpll_data const *d;
313 + int init_done;
314 +
315 + struct clk_regmap clkr;
316 + spinlock_t lock;
317 +};
318 +
319 +#define to_clk_hfpll(_hw) \
320 + container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
321 +
322 +extern const struct clk_ops clk_ops_hfpll;
323 +
324 +#endif
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