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1 From 63b81694ef7736849dcf7f7daf0becc6ebc02844 Mon Sep 17 00:00:00 2001
2 From: Viorel Suman <viorel.suman@nxp.com>
3 Date: Mon, 14 May 2018 16:28:48 +0300
4 Subject: [PATCH] MLK-17531-1: ASoC: fsl: sai: add support for SAI v3.01
5
6 a) Add support for new SAI (VERID, PARAM, MCTL, MDIV) registers
7 available in i.MX 850d (SAI v3.00) and i.MX 845s (SAI v3.01).
8 b) Handle SAI MCLK register as function of SAI IP version.
9
10 Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
11 Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
12 ---
13 sound/soc/fsl/fsl_sai.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++-
14 sound/soc/fsl/fsl_sai.h | 59 +++++++++++++++++++++++++++++++++++++++++++-
15 2 files changed, 122 insertions(+), 2 deletions(-)
16
17 --- a/sound/soc/fsl/fsl_sai.c
18 +++ b/sound/soc/fsl/fsl_sai.c
19 @@ -29,6 +29,8 @@
20 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
21 FSL_SAI_CSR_FEIE)
22
23 +#define FSL_SAI_VERID_0301 0x0301
24 +
25 static struct fsl_sai_soc_data fsl_sai_vf610 = {
26 .imx = false,
27 /*dataline is mask, not index*/
28 @@ -422,6 +424,48 @@ static int fsl_sai_set_dai_fmt(struct sn
29 return ret;
30 }
31
32 +static int fsl_sai_check_ver(struct snd_soc_dai *cpu_dai)
33 +{
34 + struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
35 + unsigned char offset = sai->soc->reg_offset;
36 + unsigned int val;
37 +
38 + if (FSL_SAI_TCSR(offset) == FSL_SAI_VERID)
39 + return 0;
40 +
41 + if (sai->verid.loaded)
42 + return 0;
43 +
44 + sai->verid.loaded = true;
45 + regmap_read(sai->regmap, FSL_SAI_VERID, &val);
46 + dev_dbg(cpu_dai->dev, "VERID: 0x%016X\n", val);
47 +
48 + sai->verid.id = (val & FSL_SAI_VER_ID_MASK) >> FSL_SAI_VER_ID_SHIFT;
49 + sai->verid.extfifo_en = (val & FSL_SAI_VER_EFIFO_EN);
50 + sai->verid.timestamp_en = (val & FSL_SAI_VER_TSTMP_EN);
51 +
52 + regmap_read(sai->regmap, FSL_SAI_PARAM, &val);
53 + dev_dbg(cpu_dai->dev, "PARAM: 0x%016X\n", val);
54 +
55 + /* max slots per frame, power of 2 */
56 + sai->param.spf = 1 <<
57 + ((val & FSL_SAI_PAR_SPF_MASK) >> FSL_SAI_PAR_SPF_SHIFT);
58 +
59 + /* words per fifo, power of 2 */
60 + sai->param.wpf = 1 <<
61 + ((val & FSL_SAI_PAR_WPF_MASK) >> FSL_SAI_PAR_WPF_SHIFT);
62 +
63 + /* number of datalines implemented */
64 + sai->param.dln = val & FSL_SAI_PAR_DLN_MASK;
65 +
66 + dev_dbg(cpu_dai->dev,
67 + "Version: 0x%08X, SPF: %u, WPF: %u, DLN: %u\n",
68 + sai->verid.id, sai->param.spf, sai->param.wpf, sai->param.dln
69 + );
70 +
71 + return 0;
72 +}
73 +
74 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
75 {
76 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
77 @@ -502,6 +546,15 @@ static int fsl_sai_set_bclk(struct snd_s
78 FSL_SAI_CR2_DIV_MASK, savediv - 1);
79 }
80
81 + fsl_sai_check_ver(dai);
82 + switch (sai->verid.id) {
83 + case FSL_SAI_VERID_0301:
84 + /* SAI is in master mode at this point, so enable MCLK */
85 + regmap_update_bits(sai->regmap, FSL_SAI_MCTL,
86 + FSL_SAI_MCTL_MCLK_EN, FSL_SAI_MCTL_MCLK_EN);
87 + break;
88 + }
89 +
90 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
91 sai->mclk_id[tx], savediv, savesub);
92
93 @@ -1001,6 +1054,8 @@ static struct reg_default fsl_sai_v3_reg
94 {FSL_SAI_RCR4(8), 0},
95 {FSL_SAI_RCR5(8), 0},
96 {FSL_SAI_RMR, 0},
97 + {FSL_SAI_MCTL, 0},
98 + {FSL_SAI_MDIV, 0},
99 };
100
101 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
102 @@ -1041,6 +1096,10 @@ static bool fsl_sai_readable_reg(struct
103 case FSL_SAI_RFR6:
104 case FSL_SAI_RFR7:
105 case FSL_SAI_RMR:
106 + case FSL_SAI_MCTL:
107 + case FSL_SAI_MDIV:
108 + case FSL_SAI_VERID:
109 + case FSL_SAI_PARAM:
110 return true;
111 default:
112 return false;
113 @@ -1056,6 +1115,8 @@ static bool fsl_sai_volatile_reg(struct
114 return true;
115
116 switch (reg) {
117 + case FSL_SAI_VERID:
118 + case FSL_SAI_PARAM:
119 case FSL_SAI_TFR0:
120 case FSL_SAI_TFR1:
121 case FSL_SAI_TFR2:
122 @@ -1108,6 +1169,8 @@ static bool fsl_sai_writeable_reg(struct
123 case FSL_SAI_TDR7:
124 case FSL_SAI_TMR:
125 case FSL_SAI_RMR:
126 + case FSL_SAI_MCTL:
127 + case FSL_SAI_MDIV:
128 return true;
129 default:
130 return false;
131 @@ -1133,7 +1196,7 @@ static const struct regmap_config fsl_sa
132 .reg_stride = 4,
133 .val_bits = 32,
134
135 - .max_register = FSL_SAI_RMR,
136 + .max_register = FSL_SAI_MDIV,
137 .reg_defaults = fsl_sai_v3_reg_defaults,
138 .num_reg_defaults = ARRAY_SIZE(fsl_sai_v3_reg_defaults),
139 .readable_reg = fsl_sai_readable_reg,
140 --- a/sound/soc/fsl/fsl_sai.h
141 +++ b/sound/soc/fsl/fsl_sai.h
142 @@ -17,6 +17,8 @@
143 SNDRV_PCM_FMTBIT_DSD_U32_LE)
144
145 /* SAI Register Map Register */
146 +#define FSL_SAI_VERID 0x00 /* SAI Version ID Register */
147 +#define FSL_SAI_PARAM 0x04 /* SAI Parameter Register */
148 #define FSL_SAI_TCSR(offset) (0x00 + offset) /* SAI Transmit Control */
149 #define FSL_SAI_TCR1(offset) (0x04 + offset) /* SAI Transmit Configuration 1 */
150 #define FSL_SAI_TCR2(offset) (0x08 + offset) /* SAI Transmit Configuration 2 */
151 @@ -39,8 +41,12 @@
152 #define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO */
153 #define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO */
154 #define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO */
155 -#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
156 #define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
157 +#define FSL_SAI_TTCTL 0x70 /* SAI Transmit Timestamp Control Register */
158 +#define FSL_SAI_TTCTN 0x74 /* SAI Transmit Timestamp Counter Register */
159 +#define FSL_SAI_TBCTN 0x78 /* SAI Transmit Bit Counter Register */
160 +#define FSL_SAI_TTCAP 0x7C /* SAI Transmit Timestamp Capture */
161 +
162 #define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
163 #define FSL_SAI_RCR1(offset) (0x84 + offset) /* SAI Receive Configuration 1 */
164 #define FSL_SAI_RCR2(offset) (0x88 + offset) /* SAI Receive Configuration 2 */
165 @@ -64,6 +70,13 @@
166 #define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO */
167 #define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO */
168 #define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
169 +#define FSL_SAI_RTCTL 0xf0 /* SAI Receive Timestamp Control Register */
170 +#define FSL_SAI_RTCTN 0xf4 /* SAI Receive Timestamp Counter Register */
171 +#define FSL_SAI_RBCTN 0xf8 /* SAI Receive Bit Counter Register */
172 +#define FSL_SAI_RTCAP 0xfc /* SAI Receive Timestamp Capture */
173 +
174 +#define FSL_SAI_MCTL 0x100 /* SAI MCLK Control Register */
175 +#define FSL_SAI_MDIV 0x104 /* SAI MCLK Divide Register */
176
177 #define FSL_SAI_xCSR(tx, off) (tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))
178 #define FSL_SAI_xCR1(tx, off) (tx ? FSL_SAI_TCR1(off) : FSL_SAI_RCR1(off))
179 @@ -109,6 +122,7 @@
180 #define FSL_SAI_CR2_MSEL(ID) ((ID) << 26)
181 #define FSL_SAI_CR2_BCP BIT(25)
182 #define FSL_SAI_CR2_BCD_MSTR BIT(24)
183 +#define FSL_SAI_CR2_BCBP BIT(23) /* BCLK bypass */
184 #define FSL_SAI_CR2_DIV_MASK 0xff
185
186 /* SAI Transmit and Receive Configuration 3 Register */
187 @@ -144,6 +158,33 @@
188 #define FSL_SAI_CR5_FBT(x) ((x) << 8)
189 #define FSL_SAI_CR5_FBT_MASK (0x1f << 8)
190
191 +/* SAI MCLK Control Register */
192 +#define FSL_SAI_MCTL_MCLK_EN BIT(30) /* MCLK Enable */
193 +#define FSL_SAI_MCTL_MSEL_MASK (0x3 << 24)
194 +#define FSL_SAI_MCTL_MSEL(ID) ((ID) << 24)
195 +#define FSL_SAI_MCTL_MSEL_BUS 0
196 +#define FSL_SAI_MCTL_MSEL_MCLK1 BIT(24)
197 +#define FSL_SAI_MCTL_MSEL_MCLK2 BIT(25)
198 +#define FSL_SAI_MCTL_MSEL_MCLK3 (BIT(24) | BIT(25))
199 +#define FSL_SAI_MCTL_DIV_EN BIT(23)
200 +#define FSL_SAI_MCTL_DIV_MASK 0xFF
201 +
202 +/* SAI VERID Register */
203 +#define FSL_SAI_VER_ID_SHIFT 16
204 +#define FSL_SAI_VER_ID_MASK (0xFFFF << FSL_SAI_VER_ID_SHIFT)
205 +#define FSL_SAI_VER_EFIFO_EN BIT(0)
206 +#define FSL_SAI_VER_TSTMP_EN BIT(1)
207 +
208 +/* SAI PARAM Register */
209 +#define FSL_SAI_PAR_SPF_SHIFT 16
210 +#define FSL_SAI_PAR_SPF_MASK (0x0F << FSL_SAI_PAR_SPF_SHIFT)
211 +#define FSL_SAI_PAR_WPF_SHIFT 8
212 +#define FSL_SAI_PAR_WPF_MASK (0x0F << FSL_SAI_PAR_WPF_SHIFT)
213 +#define FSL_SAI_PAR_DLN_MASK (0x0F)
214 +
215 +/* SAI MCLK Divide Register */
216 +#define FSL_SAI_MDIV_MASK 0xFFFFF
217 +
218 /* SAI type */
219 #define FSL_SAI_DMA BIT(0)
220 #define FSL_SAI_USE_AC97 BIT(1)
221 @@ -181,6 +222,19 @@ struct fsl_sai_soc_data {
222 bool constrain_period_size;
223 };
224
225 +struct fsl_sai_verid {
226 + u32 id;
227 + bool timestamp_en;
228 + bool extfifo_en;
229 + bool loaded;
230 +};
231 +
232 +struct fsl_sai_param {
233 + u32 spf; /* max slots per frame */
234 + u32 wpf; /* words in fifo */
235 + u32 dln; /* number of datalines implemented */
236 +};
237 +
238 struct fsl_sai {
239 struct platform_device *pdev;
240 struct regmap *regmap;
241 @@ -212,6 +266,9 @@ struct fsl_sai {
242 struct pm_qos_request pm_qos_req;
243 struct pinctrl *pinctrl;
244 struct pinctrl_state *pins_state;
245 +
246 + struct fsl_sai_verid verid;
247 + struct fsl_sai_param param;
248 };
249
250 #define TX 1
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