git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 61d4a1751cfe5a22e5f18478fe16ffb1ee12607d Mon Sep 17 00:00:00 2001
   2 From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
   3 Date: Tue, 5 Apr 2022 08:34:44 +0200
   4 Subject: [PATCH] arm64: dts: qcom: align clocks in I2C/SPI with DT schema
   5
   6 The DT schema expects clocks core-iface order.  No functional change.
   7
   8 Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
   9 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  10 Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org
  11 ---
  12  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++++++++------------
  13  1 file changed, 12 insertions(+), 12 deletions(-)
  14
  15 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  16 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  17 @@ -468,9 +468,9 @@
  18                         #size-cells = <0>;
  19                         reg = <0x078b6000 0x600>;
  20                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  21 -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
  22 -                               <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
  23 -                       clock-names = "iface", "core";
  24 +                       clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
  25 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  26 +                       clock-names = "core", "iface";
  27                         clock-frequency = <400000>;
  28                         dmas = <&blsp_dma 14>, <&blsp_dma 15>;
  29                         dma-names = "tx", "rx";
  30 @@ -485,9 +485,9 @@
  31                         #size-cells = <0>;
  32                         reg = <0x078b7000 0x600>;
  33                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
  34 -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
  35 -                               <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
  36 -                       clock-names = "iface", "core";
  37 +                       clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
  38 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  39 +                       clock-names = "core", "iface";
  40                         clock-frequency = <100000>;
  41                         dmas = <&blsp_dma 16>, <&blsp_dma 17>;
  42                         dma-names = "tx", "rx";
  43 @@ -500,9 +500,9 @@
  44                         #size-cells = <0>;
  45                         reg = <0x78b9000 0x600>;
  46                         interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
  47 -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
  48 -                                <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
  49 -                       clock-names = "iface", "core";
  50 +                       clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
  51 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  52 +                       clock-names = "core", "iface";
  53                         clock-frequency = <400000>;
  54                         dmas = <&blsp_dma 20>, <&blsp_dma 21>;
  55                         dma-names = "tx", "rx";
  56 @@ -515,9 +515,9 @@
  57                         #size-cells = <0>;
  58                         reg = <0x078ba000 0x600>;
  59                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
  60 -                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
  61 -                                <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
  62 -                       clock-names = "iface", "core";
  63 +                       clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
  64 +                                <&gcc GCC_BLSP1_AHB_CLK>;
  65 +                       clock-names = "core", "iface";
  66                         clock-frequency = <100000>;
  67                         dmas = <&blsp_dma 22>, <&blsp_dma 23>;
  68                         dma-names = "tx", "rx";