projects / openwrt / staging / pepe2k.git / blob
? search:


d10f60017de2ed9935782372e2e9a121a7d12fd7
[openwrt/staging/pepe2k.git] /
1 From 546bac0479e51024027f8c8820f912573643b101 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 18 Jan 2017 07:31:57 +1100
4 Subject: [PATCH] clk: bcm2835: Add leaf clock measurement support, disabled by
5 default
6
7 This proved incredibly useful during debugging of the DSI driver, to
8 see if our clocks were running at rate we requested. Let's leave it
9 here for the next person interacting with clocks on the platform (and
10 so that hopefully we can just hook it up to debugfs some day).
11
12 Signed-off-by: Eric Anholt <eric@anholt.net>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 (cherry picked from commit 3f9195811d8d829556c4cd88d3f9e56a80d5ba60)
15 ---
16 drivers/clk/bcm/clk-bcm2835.c | 144 ++++++++++++++++++++++++++++++++++--------
17 1 file changed, 119 insertions(+), 25 deletions(-)
18
19 --- a/drivers/clk/bcm/clk-bcm2835.c
20 +++ b/drivers/clk/bcm/clk-bcm2835.c
21 @@ -39,6 +39,7 @@
22 #include <linux/clk.h>
23 #include <linux/clk/bcm2835.h>
24 #include <linux/debugfs.h>
25 +#include <linux/delay.h>
26 #include <linux/module.h>
27 #include <linux/of.h>
28 #include <linux/platform_device.h>
29 @@ -98,7 +99,8 @@
30 #define CM_SMIDIV 0x0b4
31 /* no definition for 0x0b8 and 0x0bc */
32 #define CM_TCNTCTL 0x0c0
33 -#define CM_TCNTDIV 0x0c4
34 +# define CM_TCNT_SRC1_SHIFT 12
35 +#define CM_TCNTCNT 0x0c4
36 #define CM_TECCTL 0x0c8
37 #define CM_TECDIV 0x0cc
38 #define CM_TD0CTL 0x0d0
39 @@ -338,6 +340,61 @@ static inline u32 cprman_read(struct bcm
40 return readl(cprman->regs + reg);
41 }
42
43 +/* Does a cycle of measuring a clock through the TCNT clock, which may
44 + * source from many other clocks in the system.
45 + */
46 +static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
47 + u32 tcnt_mux)
48 +{
49 + u32 osccount = 19200; /* 1ms */
50 + u32 count;
51 + ktime_t timeout;
52 +
53 + spin_lock(&cprman->regs_lock);
54 +
55 + cprman_write(cprman, CM_TCNTCTL, CM_KILL);
56 +
57 + cprman_write(cprman, CM_TCNTCTL,
58 + (tcnt_mux & CM_SRC_MASK) |
59 + (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
60 +
61 + cprman_write(cprman, CM_OSCCOUNT, osccount);
62 +
63 + /* do a kind delay at the start */
64 + mdelay(1);
65 +
66 + /* Finish off whatever is left of OSCCOUNT */
67 + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
68 + while (cprman_read(cprman, CM_OSCCOUNT)) {
69 + if (ktime_after(ktime_get(), timeout)) {
70 + dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
71 + count = 0;
72 + goto out;
73 + }
74 + cpu_relax();
75 + }
76 +
77 + /* Wait for BUSY to clear. */
78 + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
79 + while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
80 + if (ktime_after(ktime_get(), timeout)) {
81 + dev_err(cprman->dev, "timeout waiting for !BUSY\n");
82 + count = 0;
83 + goto out;
84 + }
85 + cpu_relax();
86 + }
87 +
88 + count = cprman_read(cprman, CM_TCNTCNT);
89 +
90 + cprman_write(cprman, CM_TCNTCTL, 0);
91 +
92 +out:
93 + spin_unlock(&cprman->regs_lock);
94 +
95 + return count * 1000;
96 +}
97 +
98 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
99 struct debugfs_reg32 *regs, size_t nregs,
100 struct dentry *dentry)
101 @@ -473,6 +530,8 @@ struct bcm2835_clock_data {
102
103 bool is_vpu_clock;
104 bool is_mash_clock;
105 +
106 + u32 tcnt_mux;
107 };
108
109 struct bcm2835_gate_data {
110 @@ -1014,6 +1073,17 @@ static int bcm2835_clock_on(struct clk_h
111 CM_GATE);
112 spin_unlock(&cprman->regs_lock);
113
114 + /* Debug code to measure the clock once it's turned on to see
115 + * if it's ticking at the rate we expect.
116 + */
117 + if (data->tcnt_mux && false) {
118 + dev_info(cprman->dev,
119 + "clk %s: rate %ld, measure %ld\n",
120 + data->name,
121 + clk_hw_get_rate(hw),
122 + bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
123 + }
124 +
125 return 0;
126 }
127
128 @@ -1780,7 +1850,8 @@ static const struct bcm2835_clk_desc clk
129 .ctl_reg = CM_OTPCTL,
130 .div_reg = CM_OTPDIV,
131 .int_bits = 4,
132 - .frac_bits = 0),
133 + .frac_bits = 0,
134 + .tcnt_mux = 6),
135 /*
136 * Used for a 1Mhz clock for the system clocksource, and also used
137 * bythe watchdog timer and the camera pulse generator.
138 @@ -1814,13 +1885,15 @@ static const struct bcm2835_clk_desc clk
139 .ctl_reg = CM_H264CTL,
140 .div_reg = CM_H264DIV,
141 .int_bits = 4,
142 - .frac_bits = 8),
143 + .frac_bits = 8,
144 + .tcnt_mux = 1),
145 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
146 .name = "isp",
147 .ctl_reg = CM_ISPCTL,
148 .div_reg = CM_ISPDIV,
149 .int_bits = 4,
150 - .frac_bits = 8),
151 + .frac_bits = 8,
152 + .tcnt_mux = 2),
153
154 /*
155 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
156 @@ -1831,13 +1904,15 @@ static const struct bcm2835_clk_desc clk
157 .ctl_reg = CM_SDCCTL,
158 .div_reg = CM_SDCDIV,
159 .int_bits = 6,
160 - .frac_bits = 0),
161 + .frac_bits = 0,
162 + .tcnt_mux = 3),
163 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
164 .name = "v3d",
165 .ctl_reg = CM_V3DCTL,
166 .div_reg = CM_V3DDIV,
167 .int_bits = 4,
168 - .frac_bits = 8),
169 + .frac_bits = 8,
170 + .tcnt_mux = 4),
171 /*
172 * VPU clock. This doesn't have an enable bit, since it drives
173 * the bus for everything else, and is special so it doesn't need
174 @@ -1851,7 +1926,8 @@ static const struct bcm2835_clk_desc clk
175 .int_bits = 12,
176 .frac_bits = 8,
177 .flags = CLK_IS_CRITICAL,
178 - .is_vpu_clock = true),
179 + .is_vpu_clock = true,
180 + .tcnt_mux = 5),
181
182 /* clocks with per parent mux */
183 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
184 @@ -1859,19 +1935,22 @@ static const struct bcm2835_clk_desc clk
185 .ctl_reg = CM_AVEOCTL,
186 .div_reg = CM_AVEODIV,
187 .int_bits = 4,
188 - .frac_bits = 0),
189 + .frac_bits = 0,
190 + .tcnt_mux = 38),
191 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
192 .name = "cam0",
193 .ctl_reg = CM_CAM0CTL,
194 .div_reg = CM_CAM0DIV,
195 .int_bits = 4,
196 - .frac_bits = 8),
197 + .frac_bits = 8,
198 + .tcnt_mux = 14),
199 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
200 .name = "cam1",
201 .ctl_reg = CM_CAM1CTL,
202 .div_reg = CM_CAM1DIV,
203 .int_bits = 4,
204 - .frac_bits = 8),
205 + .frac_bits = 8,
206 + .tcnt_mux = 15),
207 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
208 .name = "dft",
209 .ctl_reg = CM_DFTCTL,
210 @@ -1883,7 +1962,8 @@ static const struct bcm2835_clk_desc clk
211 .ctl_reg = CM_DPICTL,
212 .div_reg = CM_DPIDIV,
213 .int_bits = 4,
214 - .frac_bits = 8),
215 + .frac_bits = 8,
216 + .tcnt_mux = 17),
217
218 /* Arasan EMMC clock */
219 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
220 @@ -1891,7 +1971,8 @@ static const struct bcm2835_clk_desc clk
221 .ctl_reg = CM_EMMCCTL,
222 .div_reg = CM_EMMCDIV,
223 .int_bits = 4,
224 - .frac_bits = 8),
225 + .frac_bits = 8,
226 + .tcnt_mux = 39),
227
228 /* General purpose (GPIO) clocks */
229 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
230 @@ -1900,7 +1981,8 @@ static const struct bcm2835_clk_desc clk
231 .div_reg = CM_GP0DIV,
232 .int_bits = 12,
233 .frac_bits = 12,
234 - .is_mash_clock = true),
235 + .is_mash_clock = true,
236 + .tcnt_mux = 20),
237 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
238 .name = "gp1",
239 .ctl_reg = CM_GP1CTL,
240 @@ -1908,7 +1990,8 @@ static const struct bcm2835_clk_desc clk
241 .int_bits = 12,
242 .frac_bits = 12,
243 .flags = CLK_IS_CRITICAL,
244 - .is_mash_clock = true),
245 + .is_mash_clock = true,
246 + .tcnt_mux = 21),
247 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
248 .name = "gp2",
249 .ctl_reg = CM_GP2CTL,
250 @@ -1923,40 +2006,46 @@ static const struct bcm2835_clk_desc clk
251 .ctl_reg = CM_HSMCTL,
252 .div_reg = CM_HSMDIV,
253 .int_bits = 4,
254 - .frac_bits = 8),
255 + .frac_bits = 8,
256 + .tcnt_mux = 22),
257 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK(
258 .name = "pcm",
259 .ctl_reg = CM_PCMCTL,
260 .div_reg = CM_PCMDIV,
261 .int_bits = 12,
262 .frac_bits = 12,
263 - .is_mash_clock = true),
264 + .is_mash_clock = true,
265 + .tcnt_mux = 23),
266 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
267 .name = "pwm",
268 .ctl_reg = CM_PWMCTL,
269 .div_reg = CM_PWMDIV,
270 .int_bits = 12,
271 .frac_bits = 12,
272 - .is_mash_clock = true),
273 + .is_mash_clock = true,
274 + .tcnt_mux = 24),
275 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
276 .name = "slim",
277 .ctl_reg = CM_SLIMCTL,
278 .div_reg = CM_SLIMDIV,
279 .int_bits = 12,
280 .frac_bits = 12,
281 - .is_mash_clock = true),
282 + .is_mash_clock = true,
283 + .tcnt_mux = 25),
284 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
285 .name = "smi",
286 .ctl_reg = CM_SMICTL,
287 .div_reg = CM_SMIDIV,
288 .int_bits = 4,
289 - .frac_bits = 8),
290 + .frac_bits = 8,
291 + .tcnt_mux = 27),
292 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
293 .name = "uart",
294 .ctl_reg = CM_UARTCTL,
295 .div_reg = CM_UARTDIV,
296 .int_bits = 10,
297 - .frac_bits = 12),
298 + .frac_bits = 12,
299 + .tcnt_mux = 28),
300
301 /* TV encoder clock. Only operating frequency is 108Mhz. */
302 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
303 @@ -1969,7 +2058,8 @@ static const struct bcm2835_clk_desc clk
304 * Allow rate change propagation only on PLLH_AUX which is
305 * assigned index 7 in the parent array.
306 */
307 - .set_rate_parent = BIT(7)),
308 + .set_rate_parent = BIT(7),
309 + .tcnt_mux = 29),
310
311 /* dsi clocks */
312 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
313 @@ -1977,25 +2067,29 @@ static const struct bcm2835_clk_desc clk
314 .ctl_reg = CM_DSI0ECTL,
315 .div_reg = CM_DSI0EDIV,
316 .int_bits = 4,
317 - .frac_bits = 8),
318 + .frac_bits = 8,
319 + .tcnt_mux = 18),
320 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
321 .name = "dsi1e",
322 .ctl_reg = CM_DSI1ECTL,
323 .div_reg = CM_DSI1EDIV,
324 .int_bits = 4,
325 - .frac_bits = 8),
326 + .frac_bits = 8,
327 + .tcnt_mux = 19),
328 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
329 .name = "dsi0p",
330 .ctl_reg = CM_DSI0PCTL,
331 .div_reg = CM_DSI0PDIV,
332 .int_bits = 0,
333 - .frac_bits = 0),
334 + .frac_bits = 0,
335 + .tcnt_mux = 12),
336 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
337 .name = "dsi1p",
338 .ctl_reg = CM_DSI1PCTL,
339 .div_reg = CM_DSI1PDIV,
340 .int_bits = 0,
341 - .frac_bits = 0),
342 + .frac_bits = 0,
343 + .tcnt_mux = 13),
344
345 /* the gates */
346
Staging tree of Piotr Dymacz