git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 4dc9c850a974ba7db2091ce73bcffe631aafe144 Mon Sep 17 00:00:00 2001
   2 From: Qiang Yu <quic_qianyu@quicinc.com>
   3 Date: Tue, 7 Nov 2023 16:14:50 +0800
   4 Subject: [PATCH 1/2] bus: mhi: host: pci_generic: Add SDX75 based modem
   5  support
   6
   7 Add generic info for SDX75 based modems. SDX75 takes longer to set ready
   8 during power up. Hence use separate configuration.
   9
  10 Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
  11 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  12 Link: https://lore.kernel.org/r/1699344890-87076-3-git-send-email-quic_qianyu@quicinc.com
  13 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  14 ---
  15  drivers/bus/mhi/host/pci_generic.c | 22 ++++++++++++++++++++++
  16  1 file changed, 22 insertions(+)
  17
  18 --- a/drivers/bus/mhi/host/pci_generic.c
  19 +++ b/drivers/bus/mhi/host/pci_generic.c
  20 @@ -269,6 +269,16 @@ static struct mhi_event_config modem_qco
  21         MHI_EVENT_CONFIG_HW_DATA(5, 2048, 101)
  22  };
  23
  24 +static const struct mhi_controller_config modem_qcom_v2_mhiv_config = {
  25 +       .max_channels = 128,
  26 +       .timeout_ms = 8000,
  27 +       .ready_timeout_ms = 50000,
  28 +       .num_channels = ARRAY_SIZE(modem_qcom_v1_mhi_channels),
  29 +       .ch_cfg = modem_qcom_v1_mhi_channels,
  30 +       .num_events = ARRAY_SIZE(modem_qcom_v1_mhi_events),
  31 +       .event_cfg = modem_qcom_v1_mhi_events,
  32 +};
  33 +
  34  static const struct mhi_controller_config modem_qcom_v1_mhiv_config = {
  35         .max_channels = 128,
  36         .timeout_ms = 8000,
  37 @@ -278,6 +288,16 @@ static const struct mhi_controller_confi
  38         .event_cfg = modem_qcom_v1_mhi_events,
  39  };
  40
  41 +static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
  42 +       .name = "qcom-sdx75m",
  43 +       .fw = "qcom/sdx75m/xbl.elf",
  44 +       .edl = "qcom/sdx75m/edl.mbn",
  45 +       .config = &modem_qcom_v2_mhiv_config,
  46 +       .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
  47 +       .dma_data_width = 32,
  48 +       .sideband_wake = false,
  49 +};
  50 +
  51  static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
  52         .name = "qcom-sdx65m",
  53         .fw = "qcom/sdx65m/xbl.elf",
  54 @@ -600,6 +620,8 @@ static const struct pci_device_id mhi_pc
  55                 .driver_data = (kernel_ulong_t) &mhi_telit_fn990_info },
  56         { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0308),
  57                 .driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
  58 +       { PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),
  59 +               .driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info },
  60         { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
  61                 .driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
  62         { PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */