git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 9aad43ad3285fc21158fb416830a6156a9a31fa5 Mon Sep 17 00:00:00 2001
   2 From: Balsam CHIHI <bchihi@baylibre.com>
   3 Date: Tue, 7 Mar 2023 16:45:22 +0100
   4 Subject: [PATCH 15/42] thermal/drivers/mediatek/lvts_thermal: Add AP domain
   5  for mt8195
   6
   7 Add MT8195 AP Domain support to LVTS Driver.
   8
   9 Take the opportunity to update the comments to show calibration data
  10 information related to the new domain.
  11
  12 [dlezcano]: Massaged a bit the changelog
  13
  14 Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
  15 Tested-by: Chen-Yu Tsai <wenst@chromium.org>
  16 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  17 Link: https://lore.kernel.org/r/20230307154524.118541-3-bchihi@baylibre.com
  18 ---
  19  drivers/thermal/mediatek/lvts_thermal.c | 94 +++++++++++++++++++------
  20  1 file changed, 74 insertions(+), 20 deletions(-)
  21
  22 --- a/drivers/thermal/mediatek/lvts_thermal.c
  23 +++ b/drivers/thermal/mediatek/lvts_thermal.c
  24 @@ -530,29 +530,33 @@ static int lvts_sensor_init(struct devic
  25   * The efuse blob values follows the sensor enumeration per thermal
  26   * controller. The decoding of the stream is as follow:
  27   *
  28 - *                        <--?-> <----big0 ???---> <-sensor0-> <-0->
  29 - *                        ------------------------------------------
  30 - * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 |
  31 - *                        ------------------------------------------
  32 + * stream index map for MCU Domain :
  33   *
  34 - *                        <--sensor1--><-0-> <----big1 ???---> <-sen
  35 - *                        ------------------------------------------
  36 - *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
  37 - *                        ------------------------------------------
  38 + * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
  39 + *  0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
  40   *
  41 - *                        sor0-> <-0-> <-sensor1-> <-0-> ..........
  42 - *                        ------------------------------------------
  43 - *                        | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD |
  44 - *                        ------------------------------------------
  45 + * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
  46 + *  0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
  47   *
  48 - * And so on ...
  49 + * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
  50 + *  0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
  51 + *
  52 + * stream index map for AP Domain :
  53 + *
  54 + * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
  55 + *  0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
  56 + *
  57 + * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
  58 + *  0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
  59 + *
  60 + * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
  61 + *  0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
  62 + *
  63 + * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
  64 + *  0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
  65   *
  66   * The data description gives the offset of the calibration data in
  67   * this bytes stream for each sensor.
  68 - *
  69 - * Each thermal controller can handle up to 4 sensors max, we don't
  70 - * care if there are less as the array of calibration is sized to 4
  71 - * anyway. The unused sensor slot will be zeroed.
  72   */
  73  static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
  74                                         const struct lvts_ctrl_data *lvts_ctrl_data,
  75 @@ -1165,7 +1169,7 @@ static int lvts_remove(struct platform_d
  76         return 0;
  77  }
  78
  79 -static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = {
  80 +static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
  81         {
  82                 .cal_offset = { 0x04, 0x07 },
  83                 .lvts_sensor = {
  84 @@ -1200,13 +1204,63 @@ static const struct lvts_ctrl_data mt819
  85         }
  86  };
  87
  88 +static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
  89 +               {
  90 +               .cal_offset = { 0x25, 0x28 },
  91 +               .lvts_sensor = {
  92 +                       { .dt_id = MT8195_AP_VPU0 },
  93 +                       { .dt_id = MT8195_AP_VPU1 }
  94 +               },
  95 +               .num_lvts_sensor = 2,
  96 +               .offset = 0x0,
  97 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
  98 +       },
  99 +       {
 100 +               .cal_offset = { 0x2e, 0x31 },
 101 +               .lvts_sensor = {
 102 +                       { .dt_id = MT8195_AP_GPU0 },
 103 +                       { .dt_id = MT8195_AP_GPU1 }
 104 +               },
 105 +               .num_lvts_sensor = 2,
 106 +               .offset = 0x100,
 107 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
 108 +       },
 109 +       {
 110 +               .cal_offset = { 0x37, 0x3a, 0x3d },
 111 +               .lvts_sensor = {
 112 +                       { .dt_id = MT8195_AP_VDEC },
 113 +                       { .dt_id = MT8195_AP_IMG },
 114 +                       { .dt_id = MT8195_AP_INFRA },
 115 +               },
 116 +               .num_lvts_sensor = 3,
 117 +               .offset = 0x200,
 118 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
 119 +       },
 120 +       {
 121 +               .cal_offset = { 0x43, 0x46 },
 122 +               .lvts_sensor = {
 123 +                       { .dt_id = MT8195_AP_CAM0 },
 124 +                       { .dt_id = MT8195_AP_CAM1 }
 125 +               },
 126 +               .num_lvts_sensor = 2,
 127 +               .offset = 0x300,
 128 +               .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
 129 +       }
 130 +};
 131 +
 132  static const struct lvts_data mt8195_lvts_mcu_data = {
 133 -       .lvts_ctrl      = mt8195_lvts_data_ctrl,
 134 -       .num_lvts_ctrl  = ARRAY_SIZE(mt8195_lvts_data_ctrl),
 135 +       .lvts_ctrl      = mt8195_lvts_mcu_data_ctrl,
 136 +       .num_lvts_ctrl  = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
 137 +};
 138 +
 139 +static const struct lvts_data mt8195_lvts_ap_data = {
 140 +       .lvts_ctrl      = mt8195_lvts_ap_data_ctrl,
 141 +       .num_lvts_ctrl  = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
 142  };
 143
 144  static const struct of_device_id lvts_of_match[] = {
 145         { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
 146 +       { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
 147         {},
 148  };
 149  MODULE_DEVICE_TABLE(of, lvts_of_match);