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d050691841f41932d96264512a702f146dd05873
[openwrt/staging/hauke.git] /
1 --- a/drivers/net/phy/broadcom.c
2 +++ b/drivers/net/phy/broadcom.c
3 @@ -30,6 +30,50 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
4 MODULE_AUTHOR("Maciej W. Rozycki");
5 MODULE_LICENSE("GPL");
6
7 +static int bcm54210e_config_init(struct phy_device *phydev)
8 +{
9 + int val;
10 +
11 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
12 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
13 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
14 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
15 +
16 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
17 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
18 + bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
19 +
20 + return 0;
21 +}
22 +
23 +static int bcm54612e_config_init(struct phy_device *phydev)
24 +{
25 + /* Clear TX internal delay unless requested. */
26 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
27 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
28 + /* Disable TXD to GTXCLK clock delay (default set) */
29 + /* Bit 9 is the only field in shadow register 00011 */
30 + bcm_phy_write_shadow(phydev, 0x03, 0);
31 + }
32 +
33 + /* Clear RX internal delay unless requested. */
34 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
35 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
36 + u16 reg;
37 +
38 + reg = bcm54xx_auxctl_read(phydev,
39 + MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
40 + /* Disable RXD to RXC delay (default set) */
41 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
42 + /* Clear shadow selector field */
43 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
44 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
45 + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
46 + }
47 +
48 + return 0;
49 +}
50 +
51 static int bcm54810_config(struct phy_device *phydev)
52 {
53 int rc, val;
54 @@ -230,7 +274,15 @@ static int bcm54xx_config_init(struct ph
55 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
56 bcm54xx_adjust_rxrefclk(phydev);
57
58 - if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
59 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
60 + err = bcm54210e_config_init(phydev);
61 + if (err)
62 + return err;
63 + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
64 + err = bcm54612e_config_init(phydev);
65 + if (err)
66 + return err;
67 + } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
68 err = bcm54810_config(phydev);
69 if (err)
70 return err;
71 @@ -375,41 +427,6 @@ static int bcm5481_config_aneg(struct ph
72 return ret;
73 }
74
75 -static int bcm54612e_config_aneg(struct phy_device *phydev)
76 -{
77 - int ret;
78 -
79 - /* First, auto-negotiate. */
80 - ret = genphy_config_aneg(phydev);
81 -
82 - /* Clear TX internal delay unless requested. */
83 - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
84 - (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
85 - /* Disable TXD to GTXCLK clock delay (default set) */
86 - /* Bit 9 is the only field in shadow register 00011 */
87 - bcm_phy_write_shadow(phydev, 0x03, 0);
88 - }
89 -
90 - /* Clear RX internal delay unless requested. */
91 - if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
92 - (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
93 - u16 reg;
94 -
95 - /* Errata: reads require filling in the write selector field */
96 - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
97 - MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
98 - reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
99 - /* Disable RXD to RXC delay (default set) */
100 - reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
101 - /* Clear shadow selector field */
102 - reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
103 - bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
104 - MII_BCM54XX_AUXCTL_MISC_WREN | reg);
105 - }
106 -
107 - return ret;
108 -}
109 -
110 static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
111 {
112 int val;
113 @@ -548,6 +565,19 @@ static struct phy_driver broadcom_driver
114 .config_intr = bcm_phy_config_intr,
115 .driver = { .owner = THIS_MODULE },
116 }, {
117 + .phy_id = PHY_ID_BCM54210E,
118 + .phy_id_mask = 0xfffffff0,
119 + .name = "Broadcom BCM54210E",
120 + .features = PHY_GBIT_FEATURES |
121 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
122 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
123 + .config_init = bcm54xx_config_init,
124 + .config_aneg = genphy_config_aneg,
125 + .read_status = genphy_read_status,
126 + .ack_interrupt = bcm_phy_ack_intr,
127 + .config_intr = bcm_phy_config_intr,
128 + .driver = { .owner = THIS_MODULE },
129 +}, {
130 .phy_id = PHY_ID_BCM5461,
131 .phy_id_mask = 0xfffffff0,
132 .name = "Broadcom BCM5461",
133 @@ -568,7 +598,7 @@ static struct phy_driver broadcom_driver
134 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
135 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
136 .config_init = bcm54xx_config_init,
137 - .config_aneg = bcm54612e_config_aneg,
138 + .config_aneg = genphy_config_aneg,
139 .read_status = genphy_read_status,
140 .ack_interrupt = bcm_phy_ack_intr,
141 .config_intr = bcm_phy_config_intr,
142 @@ -710,6 +740,7 @@ module_phy_driver(broadcom_drivers);
143 static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
144 { PHY_ID_BCM5411, 0xfffffff0 },
145 { PHY_ID_BCM5421, 0xfffffff0 },
146 + { PHY_ID_BCM54210E, 0xfffffff0 },
147 { PHY_ID_BCM5461, 0xfffffff0 },
148 { PHY_ID_BCM54612E, 0xfffffff0 },
149 { PHY_ID_BCM54616S, 0xfffffff0 },
150 --- a/include/linux/brcmphy.h
151 +++ b/include/linux/brcmphy.h
152 @@ -17,6 +17,7 @@
153 #define PHY_ID_BCM5482 0x0143bcb0
154 #define PHY_ID_BCM5411 0x00206070
155 #define PHY_ID_BCM5421 0x002060e0
156 +#define PHY_ID_BCM54210E 0x600d84a0
157 #define PHY_ID_BCM5464 0x002060b0
158 #define PHY_ID_BCM5461 0x002060c0
159 #define PHY_ID_BCM54612E 0x03625e60
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