git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Mon, 22 Apr 2024 10:15:14 +0300
   4 Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
   5  MT7530
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 On MT7530, the media-independent interfaces of port 5 and 6 are controlled
  11 by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
  12 these bits only when the relevant port is being enabled or disabled. This
  13 ensures that these ports will be disabled when they are not in use.
  14
  15 Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
  16 done on mt7530_setup().
  17
  18 Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
  19 on the appropriate case.
  20
  21 If PHY muxing is detected, clear MT7530_P5_DIS before calling
  22 mt7530_setup_port5().
  23
  24 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  25 ---
  26  drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
  27  1 file changed, 27 insertions(+), 11 deletions(-)
  28
  29 --- a/drivers/net/dsa/mt7530.c
  30 +++ b/drivers/net/dsa/mt7530.c
  31 @@ -887,8 +887,7 @@ static void mt7530_setup_port5(struct ds
  32
  33         val = mt7530_read(priv, MT753X_MTRAP);
  34
  35 -       val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
  36 -       val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
  37 +       val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
  38
  39         switch (priv->p5_mode) {
  40         /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
  41 @@ -898,15 +897,13 @@ static void mt7530_setup_port5(struct ds
  42
  43         /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
  44         case MUX_PHY_P4:
  45 -               val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
  46 -
  47                 /* Setup the MAC by default for the cpu port */
  48                 mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
  49                 break;
  50
  51         /* GMAC5: P5 -> SoC MAC or external PHY */
  52         default:
  53 -               val &= ~MT7530_P5_DIS;
  54 +               val |= MT7530_P5_MAC_SEL;
  55                 break;
  56         }
  57
  58 @@ -1200,6 +1197,14 @@ mt7530_port_enable(struct dsa_switch *ds
  59
  60         mutex_unlock(&priv->reg_mutex);
  61
  62 +       if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
  63 +               return 0;
  64 +
  65 +       if (port == 5)
  66 +               mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
  67 +       else if (port == 6)
  68 +               mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
  69 +
  70         return 0;
  71  }
  72
  73 @@ -1218,6 +1223,14 @@ mt7530_port_disable(struct dsa_switch *d
  74                    PCR_MATRIX_CLR);
  75
  76         mutex_unlock(&priv->reg_mutex);
  77 +
  78 +       if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
  79 +               return;
  80 +
  81 +       if (port == 5)
  82 +               mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
  83 +       else if (port == 6)
  84 +               mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
  85  }
  86
  87  static int
  88 @@ -2406,11 +2419,11 @@ mt7530_setup(struct dsa_switch *ds)
  89                 mt7530_rmw(priv, MT7530_TRGMII_RD(i),
  90                            RD_TAP_MASK, RD_TAP(16));
  91
  92 -       /* Enable port 6 */
  93 -       val = mt7530_read(priv, MT753X_MTRAP);
  94 -       val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
  95 -       val |= MT7530_CHG_TRAP;
  96 -       mt7530_write(priv, MT753X_MTRAP, val);
  97 +       /* Allow modifying the trap and directly access PHY registers via the
  98 +        * MDIO bus the switch is on.
  99 +        */
 100 +       mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
 101 +                  MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
 102
 103         if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
 104                 mt7530_pll_setup(priv);
 105 @@ -2493,8 +2506,11 @@ mt7530_setup(struct dsa_switch *ds)
 106                         break;
 107                 }
 108
 109 -               if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
 110 +               if (priv->p5_mode == MUX_PHY_P0 ||
 111 +                   priv->p5_mode == MUX_PHY_P4) {
 112 +                       mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
 113                         mt7530_setup_port5(ds, interface);
 114 +               }
 115         }
 116
 117  #ifdef CONFIG_GPIOLIB