git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
   2 From: Tianling Shen <cnsztl@gmail.com>
   3 Date: Sat, 25 Mar 2023 15:40:22 +0800
   4 Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
   5
   6 The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
   7 the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
   8 identical to OrangePi R1 Plus.
   9
  10 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
  11 Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
  12 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  13 ---
  14  arch/arm64/boot/dts/rockchip/Makefile         |  1 +
  15  .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 40 +++++++++++++++++++
  16  2 files changed, 41 insertions(+)
  17  create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
  18
  19 --- a/arch/arm64/boot/dts/rockchip/Makefile
  20 +++ b/arch/arm64/boot/dts/rockchip/Makefile
  21 @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
  22  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
  23  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
  24  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
  25 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
  26  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
  27  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
  28  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
  29 --- /dev/null
  30 +++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
  31 @@ -0,0 +1,40 @@
  32 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
  33 +/*
  34 + * Copyright (c) 2016 Xunlong Software. Co., Ltd.
  35 + * (http://www.orangepi.org)
  36 + *
  37 + * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
  38 + */
  39 +
  40 +/dts-v1/;
  41 +#include "rk3328-orangepi-r1-plus.dts"
  42 +
  43 +/ {
  44 +       model = "Xunlong Orange Pi R1 Plus LTS";
  45 +       compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
  46 +};
  47 +
  48 +&gmac2io {
  49 +       phy-handle = <&yt8531c>;
  50 +       tx_delay = <0x19>;
  51 +       rx_delay = <0x05>;
  52 +
  53 +       mdio {
  54 +               /delete-node/ ethernet-phy@1;
  55 +
  56 +               yt8531c: ethernet-phy@0 {
  57 +                       compatible = "ethernet-phy-ieee802.3-c22";
  58 +                       reg = <0>;
  59 +
  60 +                       motorcomm,clk-out-frequency-hz = <125000000>;
  61 +                       motorcomm,keep-pll-enabled;
  62 +                       motorcomm,auto-sleep-disabled;
  63 +
  64 +                       pinctrl-0 = <&eth_phy_reset_pin>;
  65 +                       pinctrl-names = "default";
  66 +                       reset-assert-us = <15000>;
  67 +                       reset-deassert-us = <50000>;
  68 +                       reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
  69 +               };
  70 +       };
  71 +};