git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From f79e871c8d9fbe90b351f61b052878d98b999b1b Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Mon, 26 Jul 2021 18:07:25 +0100
   4 Subject: [PATCH] drm/vc4: Increase the core clock to a minimum of 500MHz
   5
   6 The core clock needs to be raised temporarily during a modeset to
   7 500MHz. However, the HVS core clock requirement might be higher than
   8 500MHz. This rate will be enforced at the end of the mode setting,
   9 meaning that might might end up with a core clock rate lower than
  10 planned on the first mode set.
  11
  12 Use the maximum value of 500MHz and the HVS core clock rate for our
  13 temporary boost to fix this issue.
  14
  15 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  16 ---
  17  drivers/gpu/drm/vc4/vc4_kms.c | 8 +++++++-
  18  1 file changed, 7 insertions(+), 1 deletion(-)
  19
  20 --- a/drivers/gpu/drm/vc4/vc4_kms.c
  21 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
  22 @@ -348,11 +348,17 @@ vc4_atomic_complete_commit(struct drm_at
  23         }
  24
  25         if (vc4->hvs && vc4->hvs->hvs5) {
  26 +               unsigned long core_rate = max_t(unsigned long,
  27 +                                               500000000,
  28 +                                               hvs_state->core_clock_rate);
  29 +
  30 +               drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
  31 +
  32                 /*
  33                  * Do a temporary request on the core clock during the
  34                  * modeset.
  35                  */
  36 -               core_req = clk_request_start(hvs->core_clk, 500000000);
  37 +               core_req = clk_request_start(hvs->core_clk, core_rate);
  38
  39                 /*
  40                  * And remove the previous one based on the HVS