git.openwrt.org Git - openwrt/staging/dedeckeh.git/blob

   1 From 1d3e170344dff2cef8827db6c09909b78cbc11d7 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:05 +0100
   4 Subject: [PATCH] PCI: aardvark: Add support for DEVCAP2, DEVCTL2, LNKCAP2 and
   5  LNKCTL2 registers on emulated bridge
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 PCI aardvark hardware supports access to DEVCAP2, DEVCTL2, LNKCAP2 and
  11 LNKCTL2 configuration registers of PCIe core via PCIE_CORE_PCIEXP_CAP.
  12 Export them via emulated software root bridge.
  13
  14 Link: https://lore.kernel.org/r/20211130172913.9727-4-kabel@kernel.org
  15 Signed-off-by: Pali Rohár <pali@kernel.org>
  16 Signed-off-by: Marek Behún <kabel@kernel.org>
  17 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  18 ---
  19  drivers/pci/controller/pci-aardvark.c | 15 +++++++++++----
  20  1 file changed, 11 insertions(+), 4 deletions(-)
  21
  22 --- a/drivers/pci/controller/pci-aardvark.c
  23 +++ b/drivers/pci/controller/pci-aardvark.c
  24 @@ -881,8 +881,13 @@ advk_pci_bridge_emul_pcie_conf_read(stru
  25
  26         case PCI_EXP_DEVCAP:
  27         case PCI_EXP_DEVCTL:
  28 +       case PCI_EXP_DEVCAP2:
  29 +       case PCI_EXP_DEVCTL2:
  30 +       case PCI_EXP_LNKCAP2:
  31 +       case PCI_EXP_LNKCTL2:
  32                 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
  33                 return PCI_BRIDGE_EMUL_HANDLED;
  34 +
  35         default:
  36                 return PCI_BRIDGE_EMUL_NOT_HANDLED;
  37         }
  38 @@ -896,10 +901,6 @@ advk_pci_bridge_emul_pcie_conf_write(str
  39         struct advk_pcie *pcie = bridge->data;
  40
  41         switch (reg) {
  42 -       case PCI_EXP_DEVCTL:
  43 -               advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  44 -               break;
  45 -
  46         case PCI_EXP_LNKCTL:
  47                 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  48                 if (new & PCI_EXP_LNKCTL_RL)
  49 @@ -921,6 +922,12 @@ advk_pci_bridge_emul_pcie_conf_write(str
  50                 advk_writel(pcie, new, PCIE_ISR0_REG);
  51                 break;
  52
  53 +       case PCI_EXP_DEVCTL:
  54 +       case PCI_EXP_DEVCTL2:
  55 +       case PCI_EXP_LNKCTL2:
  56 +               advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
  57 +               break;
  58 +
  59         default:
  60                 break;
  61         }