git.openwrt.org Git - openwrt/staging/jogo.git/blob

   1 From 7237a6a0c020c05bb819774391154b40b2cfaabd Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:23:42 +0800
   4 Subject: [PATCH 19/25] net: mediatek: add support for MediaTek MT7621 SoC
   5
   6 This patch adds GMAC support for MediaTek MT7621 SoC.
   7 MT7621 has the same GMAC/Switch configuration as MT7623.
   8
   9 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
  10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  11 ---
  12  drivers/net/mtk_eth.c | 21 +++++++++++++++------
  13  1 file changed, 15 insertions(+), 6 deletions(-)
  14
  15 diff --git a/drivers/net/mtk_eth.c b/drivers/net/mtk_eth.c
  16 index ac1e8abd71..4fe7ee0d36 100644
  17 --- a/drivers/net/mtk_eth.c
  18 +++ b/drivers/net/mtk_eth.c
  19 @@ -145,7 +145,8 @@ enum mtk_switch {
  20  enum mtk_soc {
  21         SOC_MT7623,
  22         SOC_MT7629,
  23 -       SOC_MT7622
  24 +       SOC_MT7622,
  25 +       SOC_MT7621
  26  };
  27
  28  struct mtk_eth_priv {
  29 @@ -675,12 +676,18 @@ static int mt7530_pad_clk_setup(struct mtk_eth_priv *priv, int mode)
  30  static int mt7530_setup(struct mtk_eth_priv *priv)
  31  {
  32         u16 phy_addr, phy_val;
  33 -       u32 val;
  34 +       u32 val, txdrv;
  35         int i;
  36
  37 -       /* Select 250MHz clk for RGMII mode */
  38 -       mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  39 -                      ETHSYS_TRGMII_CLK_SEL362_5, 0);
  40 +       if (priv->soc != SOC_MT7621) {
  41 +               /* Select 250MHz clk for RGMII mode */
  42 +               mtk_ethsys_rmw(priv, ETHSYS_CLKCFG0_REG,
  43 +                              ETHSYS_TRGMII_CLK_SEL362_5, 0);
  44 +
  45 +               txdrv = 8;
  46 +       } else {
  47 +               txdrv = 4;
  48 +       }
  49
  50         /* Modify HWTRAP first to allow direct access to internal PHYs */
  51         mt753x_reg_read(priv, HWTRAP_REG, &val);
  52 @@ -738,7 +745,8 @@ static int mt7530_setup(struct mtk_eth_priv *priv)
  53         /* Lower Tx Driving for TRGMII path */
  54         for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
  55                 mt753x_reg_write(priv, MT7530_TRGMII_TD_ODT(i),
  56 -                                (8 << TD_DM_DRVP_S) | (8 << TD_DM_DRVN_S));
  57 +                                (txdrv << TD_DM_DRVP_S) |
  58 +                                (txdrv << TD_DM_DRVN_S));
  59
  60         for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
  61                 mt753x_reg_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_M, 16);
  62 @@ -1540,6 +1548,7 @@ static const struct udevice_id mtk_eth_ids[] = {
  63         { .compatible = "mediatek,mt7629-eth", .data = SOC_MT7629 },
  64         { .compatible = "mediatek,mt7623-eth", .data = SOC_MT7623 },
  65         { .compatible = "mediatek,mt7622-eth", .data = SOC_MT7622 },
  66 +       { .compatible = "mediatek,mt7621-eth", .data = SOC_MT7621 },
  67         {}
  68  };
  69
  70 --
  71 2.36.1
  72