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[openwrt/staging/dangole.git] /
1 From d525836896235c4678f6144cc4608d5b15e02660 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 31 Aug 2022 19:05:16 +0800
4 Subject: [PATCH 27/32] clk: mediatek: add clock driver support for MediaTek
5 MT7981 SoC
6
7 This patch adds clock driver support for MediaTek MT7981 SoC
8
9 Reviewed-by: Sean Anderson <seanga2@gmail.com>
10 Reviewed-by: Simon Glass <sjg@chromium.org>
11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
12 ---
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-mt7981.c | 683 +++++++++++++++++++++++++
15 include/dt-bindings/clock/mt7981-clk.h | 267 ++++++++++
16 3 files changed, 951 insertions(+)
17 create mode 100644 drivers/clk/mediatek/clk-mt7981.c
18 create mode 100644 include/dt-bindings/clock/mt7981-clk.h
19
20 --- a/drivers/clk/mediatek/Makefile
21 +++ b/drivers/clk/mediatek/Makefile
22 @@ -8,6 +8,7 @@ obj-$(CONFIG_TARGET_MT7623) += clk-mt762
23 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
24 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
25 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
26 +obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
27 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
28 obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
29 obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
30 --- /dev/null
31 +++ b/drivers/clk/mediatek/clk-mt7981.c
32 @@ -0,0 +1,683 @@
33 +// SPDX-License-Identifier: GPL-2.0
34 +/*
35 + * MediaTek clock driver for MT7981 SoC
36 + *
37 + * Copyright (C) 2022 MediaTek Inc.
38 + * Author: Sam Shih <sam.shih@mediatek.com>
39 + */
40 +
41 +#include <dm.h>
42 +#include <log.h>
43 +#include <asm/arch-mediatek/reset.h>
44 +#include <asm/io.h>
45 +#include <dt-bindings/clock/mt7981-clk.h>
46 +#include <linux/bitops.h>
47 +
48 +#include "clk-mtk.h"
49 +
50 +#define MT7981_CLK_PDN 0x250
51 +#define MT7981_CLK_PDN_EN_WRITE BIT(31)
52 +
53 +#define PLL_FACTOR(_id, _name, _parent, _mult, _div) \
54 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
55 +
56 +#define TOP_FACTOR(_id, _name, _parent, _mult, _div) \
57 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
58 +
59 +#define INFRA_FACTOR(_id, _name, _parent, _mult, _div) \
60 + FACTOR(_id, _parent, _mult, _div, CLK_PARENT_INFRASYS)
61 +
62 +/* FIXED PLLS */
63 +static const struct mtk_fixed_clk fixed_pll_clks[] = {
64 + FIXED_CLK(CK_APMIXED_ARMPLL, CLK_XTAL, 1300000000),
65 + FIXED_CLK(CK_APMIXED_NET2PLL, CLK_XTAL, 800000000),
66 + FIXED_CLK(CK_APMIXED_MMPLL, CLK_XTAL, 720000000),
67 + FIXED_CLK(CK_APMIXED_SGMPLL, CLK_XTAL, 325000000),
68 + FIXED_CLK(CK_APMIXED_WEDMCUPLL, CLK_XTAL, 208000000),
69 + FIXED_CLK(CK_APMIXED_NET1PLL, CLK_XTAL, 2500000000),
70 + FIXED_CLK(CK_APMIXED_MPLL, CLK_XTAL, 416000000),
71 + FIXED_CLK(CK_APMIXED_APLL2, CLK_XTAL, 196608000),
72 +};
73 +
74 +/* TOPCKGEN FIXED CLK */
75 +static const struct mtk_fixed_clk top_fixed_clks[] = {
76 + FIXED_CLK(CK_TOP_CB_CKSQ_40M, CLK_XTAL, 40000000),
77 +};
78 +
79 +/* TOPCKGEN FIXED DIV */
80 +static const struct mtk_fixed_factor top_fixed_divs[] = {
81 + PLL_FACTOR(CK_TOP_CB_M_416M, "cb_m_416m", CK_APMIXED_MPLL, 1, 1),
82 + PLL_FACTOR(CK_TOP_CB_M_D2, "cb_m_d2", CK_APMIXED_MPLL, 1, 2),
83 + PLL_FACTOR(CK_TOP_CB_M_D3, "cb_m_d3", CK_APMIXED_MPLL, 1, 3),
84 + PLL_FACTOR(CK_TOP_M_D3_D2, "m_d3_d2", CK_APMIXED_MPLL, 1, 2),
85 + PLL_FACTOR(CK_TOP_CB_M_D4, "cb_m_d4", CK_APMIXED_MPLL, 1, 4),
86 + PLL_FACTOR(CK_TOP_CB_M_D8, "cb_m_d8", CK_APMIXED_MPLL, 1, 8),
87 + PLL_FACTOR(CK_TOP_M_D8_D2, "m_d8_d2", CK_APMIXED_MPLL, 1, 16),
88 + PLL_FACTOR(CK_TOP_CB_MM_720M, "cb_mm_720m", CK_APMIXED_MMPLL, 1, 1),
89 + PLL_FACTOR(CK_TOP_CB_MM_D2, "cb_mm_d2", CK_APMIXED_MMPLL, 1, 2),
90 + PLL_FACTOR(CK_TOP_CB_MM_D3, "cb_mm_d3", CK_APMIXED_MMPLL, 1, 3),
91 + PLL_FACTOR(CK_TOP_CB_MM_D3_D5, "cb_mm_d3_d5", CK_APMIXED_MMPLL, 1, 15),
92 + PLL_FACTOR(CK_TOP_CB_MM_D4, "cb_mm_d4", CK_APMIXED_MMPLL, 1, 4),
93 + PLL_FACTOR(CK_TOP_CB_MM_D6, "cb_mm_d6", CK_APMIXED_MMPLL, 1, 6),
94 + PLL_FACTOR(CK_TOP_MM_D6_D2, "mm_d6_d2", CK_APMIXED_MMPLL, 1, 12),
95 + PLL_FACTOR(CK_TOP_CB_MM_D8, "cb_mm_d8", CK_APMIXED_MMPLL, 1, 8),
96 + PLL_FACTOR(CK_TOP_CB_APLL2_196M, "cb_apll2_196m", CK_APMIXED_APLL2, 1,
97 + 1),
98 + PLL_FACTOR(CK_TOP_APLL2_D2, "apll2_d2", CK_APMIXED_APLL2, 1, 2),
99 + PLL_FACTOR(CK_TOP_APLL2_D4, "apll2_d4", CK_APMIXED_APLL2, 1, 4),
100 + PLL_FACTOR(CK_TOP_NET1_2500M, "net1_2500m", CK_APMIXED_NET1PLL, 1, 1),
101 + PLL_FACTOR(CK_TOP_CB_NET1_D4, "cb_net1_d4", CK_APMIXED_NET1PLL, 1, 4),
102 + PLL_FACTOR(CK_TOP_CB_NET1_D5, "cb_net1_d5", CK_APMIXED_NET1PLL, 1, 5),
103 + PLL_FACTOR(CK_TOP_NET1_D5_D2, "net1_d5_d2", CK_APMIXED_NET1PLL, 1, 10),
104 + PLL_FACTOR(CK_TOP_NET1_D5_D4, "net1_d5_d4", CK_APMIXED_NET1PLL, 1, 20),
105 + PLL_FACTOR(CK_TOP_CB_NET1_D8, "cb_net1_d8", CK_APMIXED_NET1PLL, 1, 8),
106 + PLL_FACTOR(CK_TOP_NET1_D8_D2, "net1_d8_d2", CK_APMIXED_NET1PLL, 1, 16),
107 + PLL_FACTOR(CK_TOP_NET1_D8_D4, "net1_d8_d4", CK_APMIXED_NET1PLL, 1, 32),
108 + PLL_FACTOR(CK_TOP_CB_NET2_800M, "cb_net2_800m", CK_APMIXED_NET2PLL, 1,
109 + 1),
110 + PLL_FACTOR(CK_TOP_CB_NET2_D2, "cb_net2_d2", CK_APMIXED_NET2PLL, 1, 2),
111 + PLL_FACTOR(CK_TOP_CB_NET2_D4, "cb_net2_d4", CK_APMIXED_NET2PLL, 1, 4),
112 + PLL_FACTOR(CK_TOP_NET2_D4_D2, "net2_d4_d2", CK_APMIXED_NET2PLL, 1, 8),
113 + PLL_FACTOR(CK_TOP_NET2_D4_D4, "net2_d4_d4", CK_APMIXED_NET2PLL, 1, 16),
114 + PLL_FACTOR(CK_TOP_CB_NET2_D6, "cb_net2_d6", CK_APMIXED_NET2PLL, 1, 6),
115 + PLL_FACTOR(CK_TOP_CB_WEDMCU_208M, "cb_wedmcu_208m",
116 + CK_APMIXED_WEDMCUPLL, 1, 1),
117 + PLL_FACTOR(CK_TOP_CB_SGM_325M, "cb_sgm_325m", CK_APMIXED_SGMPLL, 1, 1),
118 + TOP_FACTOR(CK_TOP_CKSQ_40M_D2, "cksq_40m_d2", CK_TOP_CB_CKSQ_40M, 1, 2),
119 + TOP_FACTOR(CK_TOP_CB_RTC_32K, "cb_rtc_32k", CK_TOP_CB_CKSQ_40M, 1,
120 + 1250),
121 + TOP_FACTOR(CK_TOP_CB_RTC_32P7K, "cb_rtc_32p7k", CK_TOP_CB_CKSQ_40M, 1,
122 + 1220),
123 + TOP_FACTOR(CK_TOP_USB_TX250M, "usb_tx250m", CK_TOP_CB_CKSQ_40M, 1, 1),
124 + TOP_FACTOR(CK_TOP_FAUD, "faud", CK_TOP_CB_CKSQ_40M, 1, 1),
125 + TOP_FACTOR(CK_TOP_NFI1X, "nfi1x", CK_TOP_NFI1X_SEL, 1, 1),
126 + TOP_FACTOR(CK_TOP_USB_EQ_RX250M, "usb_eq_rx250m", CK_TOP_CB_CKSQ_40M, 1,
127 + 1),
128 + TOP_FACTOR(CK_TOP_USB_CDR_CK, "usb_cdr", CK_TOP_CB_CKSQ_40M, 1, 1),
129 + TOP_FACTOR(CK_TOP_USB_LN0_CK, "usb_ln0", CK_TOP_CB_CKSQ_40M, 1, 1),
130 + TOP_FACTOR(CK_TOP_SPINFI_BCK, "spinfi_bck", CK_TOP_SPINFI_SEL, 1, 1),
131 + TOP_FACTOR(CK_TOP_SPI, "spi", CK_TOP_SPI_SEL, 1, 1),
132 + TOP_FACTOR(CK_TOP_SPIM_MST, "spim_mst", CK_TOP_SPIM_MST_SEL, 1, 1),
133 + TOP_FACTOR(CK_TOP_UART_BCK, "uart_bck", CK_TOP_UART_SEL, 1, 1),
134 + TOP_FACTOR(CK_TOP_PWM_BCK, "pwm_bck", CK_TOP_PWM_SEL, 1, 1),
135 + TOP_FACTOR(CK_TOP_I2C_BCK, "i2c_bck", CK_TOP_I2C_SEL, 1, 1),
136 + TOP_FACTOR(CK_TOP_PEXTP_TL, "pextp_tl", CK_TOP_PEXTP_TL_SEL, 1, 1),
137 + TOP_FACTOR(CK_TOP_EMMC_208M, "emmc_208m", CK_TOP_EMMC_208M_SEL, 1, 1),
138 + TOP_FACTOR(CK_TOP_EMMC_400M, "emmc_400m", CK_TOP_EMMC_400M_SEL, 1, 1),
139 + TOP_FACTOR(CK_TOP_DRAMC_REF, "dramc_ref", CK_TOP_DRAMC_SEL, 1, 1),
140 + TOP_FACTOR(CK_TOP_DRAMC_MD32, "dramc_md32", CK_TOP_DRAMC_MD32_SEL, 1,
141 + 1),
142 + TOP_FACTOR(CK_TOP_SYSAXI, "sysaxi", CK_TOP_SYSAXI_SEL, 1, 1),
143 + TOP_FACTOR(CK_TOP_SYSAPB, "sysapb", CK_TOP_SYSAPB_SEL, 1, 1),
144 + TOP_FACTOR(CK_TOP_ARM_DB_MAIN, "arm_db_main", CK_TOP_ARM_DB_MAIN_SEL, 1,
145 + 1),
146 + TOP_FACTOR(CK_TOP_AP2CNN_HOST, "ap2cnn_host", CK_TOP_AP2CNN_HOST_SEL, 1,
147 + 1),
148 + TOP_FACTOR(CK_TOP_NETSYS, "netsys", CK_TOP_NETSYS_SEL, 1, 1),
149 + TOP_FACTOR(CK_TOP_NETSYS_500M, "netsys_500m", CK_TOP_NETSYS_500M_SEL, 1,
150 + 1),
151 + TOP_FACTOR(CK_TOP_NETSYS_WED_MCU, "netsys_wed_mcu",
152 + CK_TOP_NETSYS_MCU_SEL, 1, 1),
153 + TOP_FACTOR(CK_TOP_NETSYS_2X, "netsys_2x", CK_TOP_NETSYS_2X_SEL, 1, 1),
154 + TOP_FACTOR(CK_TOP_SGM_325M, "sgm_325m", CK_TOP_SGM_325M_SEL, 1, 1),
155 + TOP_FACTOR(CK_TOP_SGM_REG, "sgm_reg", CK_TOP_SGM_REG_SEL, 1, 1),
156 + TOP_FACTOR(CK_TOP_F26M, "csw_f26m", CK_TOP_F26M_SEL, 1, 1),
157 + TOP_FACTOR(CK_TOP_EIP97B, "eip97b", CK_TOP_EIP97B_SEL, 1, 1),
158 + TOP_FACTOR(CK_TOP_USB3_PHY, "usb3_phy", CK_TOP_USB3_PHY_SEL, 1, 1),
159 + TOP_FACTOR(CK_TOP_AUD, "aud", CK_TOP_FAUD, 1, 1),
160 + TOP_FACTOR(CK_TOP_A1SYS, "a1sys", CK_TOP_A1SYS_SEL, 1, 1),
161 + TOP_FACTOR(CK_TOP_AUD_L, "aud_l", CK_TOP_AUD_L_SEL, 1, 1),
162 + TOP_FACTOR(CK_TOP_A_TUNER, "a_tuner", CK_TOP_A_TUNER_SEL, 1, 1),
163 + TOP_FACTOR(CK_TOP_U2U3_REF, "u2u3_ref", CK_TOP_U2U3_SEL, 1, 1),
164 + TOP_FACTOR(CK_TOP_U2U3_SYS, "u2u3_sys", CK_TOP_U2U3_SYS_SEL, 1, 1),
165 + TOP_FACTOR(CK_TOP_U2U3_XHCI, "u2u3_xhci", CK_TOP_U2U3_XHCI_SEL, 1, 1),
166 + TOP_FACTOR(CK_TOP_USB_FRMCNT, "usb_frmcnt", CK_TOP_USB_FRMCNT_SEL, 1,
167 + 1),
168 +};
169 +
170 +/* TOPCKGEN MUX PARENTS */
171 +static const int nfi1x_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D4,
172 + CK_TOP_NET1_D8_D2, CK_TOP_CB_NET2_D6,
173 + CK_TOP_CB_M_D4, CK_TOP_CB_MM_D8,
174 + CK_TOP_NET1_D8_D4, CK_TOP_CB_M_D8 };
175 +
176 +static const int spinfi_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_CB_CKSQ_40M,
177 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
178 + CK_TOP_CB_MM_D8, CK_TOP_NET1_D8_D4,
179 + CK_TOP_MM_D6_D2, CK_TOP_CB_M_D8 };
180 +
181 +static const int spi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
182 + CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
183 + CK_TOP_CB_NET2_D6, CK_TOP_NET1_D5_D4,
184 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
185 +
186 +static const int uart_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D8,
187 + CK_TOP_M_D8_D2 };
188 +
189 +static const int pwm_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2,
190 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
191 + CK_TOP_M_D8_D2, CK_TOP_CB_RTC_32K };
192 +
193 +static const int i2c_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4,
194 + CK_TOP_CB_M_D4, CK_TOP_NET1_D8_D4 };
195 +
196 +static const int pextp_tl_ck_parents[] = { CK_TOP_CB_CKSQ_40M,
197 + CK_TOP_NET1_D5_D4, CK_TOP_CB_M_D4,
198 + CK_TOP_CB_RTC_32K };
199 +
200 +static const int emmc_208m_parents[] = {
201 + CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2, CK_TOP_CB_NET2_D4,
202 + CK_TOP_CB_APLL2_196M, CK_TOP_CB_MM_D4, CK_TOP_NET1_D8_D2,
203 + CK_TOP_CB_MM_D6
204 +};
205 +
206 +static const int emmc_400m_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D2,
207 + CK_TOP_CB_MM_D2, CK_TOP_CB_NET2_D2 };
208 +
209 +static const int csw_f26m_parents[] = { CK_TOP_CKSQ_40M_D2, CK_TOP_M_D8_D2 };
210 +
211 +static const int dramc_md32_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_M_D2,
212 + CK_TOP_CB_WEDMCU_208M };
213 +
214 +static const int sysaxi_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D8_D2 };
215 +
216 +static const int sysapb_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D3_D2 };
217 +
218 +static const int arm_db_main_parents[] = { CK_TOP_CB_CKSQ_40M,
219 + CK_TOP_CB_NET2_D6 };
220 +
221 +static const int ap2cnn_host_parents[] = { CK_TOP_CB_CKSQ_40M,
222 + CK_TOP_NET1_D8_D4 };
223 +
224 +static const int netsys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_D2 };
225 +
226 +static const int netsys_500m_parents[] = { CK_TOP_CB_CKSQ_40M,
227 + CK_TOP_CB_NET1_D5 };
228 +
229 +static const int netsys_mcu_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_MM_720M,
230 + CK_TOP_CB_NET1_D4, CK_TOP_CB_NET1_D5,
231 + CK_TOP_CB_M_416M };
232 +
233 +static const int netsys_2x_parents[] = { CK_TOP_CB_CKSQ_40M,
234 + CK_TOP_CB_NET2_800M,
235 + CK_TOP_CB_MM_720M };
236 +
237 +static const int sgm_325m_parents[] = { CK_TOP_CB_CKSQ_40M,
238 + CK_TOP_CB_SGM_325M };
239 +
240 +static const int sgm_reg_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET2_D4 };
241 +
242 +static const int eip97b_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_NET1_D5,
243 + CK_TOP_CB_M_416M, CK_TOP_CB_MM_D2,
244 + CK_TOP_NET1_D5_D2 };
245 +
246 +static const int aud_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M };
247 +
248 +static const int a1sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4 };
249 +
250 +static const int aud_l_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_CB_APLL2_196M,
251 + CK_TOP_M_D8_D2 };
252 +
253 +static const int a_tuner_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_APLL2_D4,
254 + CK_TOP_M_D8_D2 };
255 +
256 +static const int u2u3_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_M_D8_D2 };
257 +
258 +static const int u2u3_sys_parents[] = { CK_TOP_CB_CKSQ_40M, CK_TOP_NET1_D5_D4 };
259 +
260 +static const int usb_frmcnt_parents[] = { CK_TOP_CB_CKSQ_40M,
261 + CK_TOP_CB_MM_D3_D5 };
262 +
263 +#define TOP_MUX(_id, _name, _parents, _mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
264 + _shift, _width, _gate, _upd_ofs, _upd) \
265 + { \
266 + .id = _id, .mux_reg = _mux_ofs, .mux_set_reg = _mux_set_ofs, \
267 + .mux_clr_reg = _mux_clr_ofs, .upd_reg = _upd_ofs, \
268 + .upd_shift = _upd, .mux_shift = _shift, \
269 + .mux_mask = BIT(_width) - 1, .gate_reg = _mux_ofs, \
270 + .gate_shift = _gate, .parent = _parents, \
271 + .num_parents = ARRAY_SIZE(_parents), \
272 + .flags = CLK_MUX_SETCLR_UPD, \
273 + }
274 +
275 +/* TOPCKGEN MUX_GATE */
276 +static const struct mtk_composite top_muxes[] = {
277 + TOP_MUX(CK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents, 0x0, 0x4, 0x8, 0,
278 + 3, 7, 0x1c0, 0),
279 + TOP_MUX(CK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents, 0x0, 0x4, 0x8,
280 + 8, 3, 15, 0x1c0, 1),
281 + TOP_MUX(CK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0, 0x4, 0x8, 16, 3,
282 + 23, 0x1c0, 2),
283 + TOP_MUX(CK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents, 0x0, 0x4, 0x8,
284 + 24, 3, 31, 0x1c0, 3),
285 + TOP_MUX(CK_TOP_UART_SEL, "uart_sel", uart_parents, 0x10, 0x14, 0x18, 0,
286 + 2, 7, 0x1c0, 4),
287 + TOP_MUX(CK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x10, 0x14, 0x18, 8, 3,
288 + 15, 0x1c0, 5),
289 + TOP_MUX(CK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x10, 0x14, 0x18, 16, 2,
290 + 23, 0x1c0, 6),
291 + TOP_MUX(CK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel", pextp_tl_ck_parents,
292 + 0x10, 0x14, 0x18, 24, 2, 31, 0x1c0, 7),
293 + TOP_MUX(CK_TOP_EMMC_208M_SEL, "emmc_208m_sel", emmc_208m_parents, 0x20,
294 + 0x24, 0x28, 0, 3, 7, 0x1c0, 8),
295 + TOP_MUX(CK_TOP_EMMC_400M_SEL, "emmc_400m_sel", emmc_400m_parents, 0x20,
296 + 0x24, 0x28, 8, 2, 15, 0x1c0, 9),
297 + TOP_MUX(CK_TOP_F26M_SEL, "csw_f26m_sel", csw_f26m_parents, 0x20, 0x24,
298 + 0x28, 16, 1, 23, 0x1c0, 10),
299 + TOP_MUX(CK_TOP_DRAMC_SEL, "dramc_sel", csw_f26m_parents, 0x20, 0x24,
300 + 0x28, 24, 1, 31, 0x1c0, 11),
301 + TOP_MUX(CK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel", dramc_md32_parents,
302 + 0x30, 0x34, 0x38, 0, 2, 7, 0x1c0, 12),
303 + TOP_MUX(CK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents, 0x30, 0x34,
304 + 0x38, 8, 1, 15, 0x1c0, 13),
305 + TOP_MUX(CK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents, 0x30, 0x34,
306 + 0x38, 16, 1, 23, 0x1c0, 14),
307 + TOP_MUX(CK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel", arm_db_main_parents,
308 + 0x30, 0x34, 0x38, 24, 1, 31, 0x1c0, 15),
309 + TOP_MUX(CK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel", ap2cnn_host_parents,
310 + 0x40, 0x44, 0x48, 0, 1, 7, 0x1c0, 16),
311 + TOP_MUX(CK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x40, 0x44,
312 + 0x48, 8, 1, 15, 0x1c0, 17),
313 + TOP_MUX(CK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents,
314 + 0x40, 0x44, 0x48, 16, 1, 23, 0x1c0, 18),
315 + TOP_MUX(CK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel", netsys_mcu_parents,
316 + 0x40, 0x44, 0x48, 24, 3, 31, 0x1c0, 19),
317 + TOP_MUX(CK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x50,
318 + 0x54, 0x58, 0, 2, 7, 0x1c0, 20),
319 + TOP_MUX(CK_TOP_SGM_325M_SEL, "sgm_325m_sel", sgm_325m_parents, 0x50,
320 + 0x54, 0x58, 8, 1, 15, 0x1c0, 21),
321 + TOP_MUX(CK_TOP_SGM_REG_SEL, "sgm_reg_sel", sgm_reg_parents, 0x50, 0x54,
322 + 0x58, 16, 1, 23, 0x1c0, 22),
323 + TOP_MUX(CK_TOP_EIP97B_SEL, "eip97b_sel", eip97b_parents, 0x50, 0x54,
324 + 0x58, 24, 3, 31, 0x1c0, 23),
325 + TOP_MUX(CK_TOP_USB3_PHY_SEL, "usb3_phy_sel", csw_f26m_parents, 0x60,
326 + 0x64, 0x68, 0, 1, 7, 0x1c0, 24),
327 + TOP_MUX(CK_TOP_AUD_SEL, "aud_sel", aud_parents, 0x60, 0x64, 0x68, 8, 1,
328 + 15, 0x1c0, 25),
329 + TOP_MUX(CK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents, 0x60, 0x64, 0x68,
330 + 16, 1, 23, 0x1c0, 26),
331 + TOP_MUX(CK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents, 0x60, 0x64, 0x68,
332 + 24, 2, 31, 0x1c0, 27),
333 + TOP_MUX(CK_TOP_A_TUNER_SEL, "a_tuner_sel", a_tuner_parents, 0x70, 0x74,
334 + 0x78, 0, 2, 7, 0x1c0, 28),
335 + TOP_MUX(CK_TOP_U2U3_SEL, "u2u3_sel", u2u3_parents, 0x70, 0x74, 0x78, 8,
336 + 1, 15, 0x1c0, 29),
337 + TOP_MUX(CK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel", u2u3_sys_parents, 0x70,
338 + 0x74, 0x78, 16, 1, 23, 0x1c0, 30),
339 + TOP_MUX(CK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel", u2u3_sys_parents, 0x70,
340 + 0x74, 0x78, 24, 1, 31, 0x1c4, 0),
341 + TOP_MUX(CK_TOP_USB_FRMCNT_SEL, "usb_frmcnt_sel", usb_frmcnt_parents,
342 + 0x80, 0x84, 0x88, 0, 1, 7, 0x1c4, 1),
343 +};
344 +
345 +/* INFRA FIXED DIV */
346 +static const struct mtk_fixed_factor infra_fixed_divs[] = {
347 + TOP_FACTOR(CK_INFRA_CK_F26M, "infra_ck_f26m", CK_TOP_F26M_SEL, 1, 1),
348 + TOP_FACTOR(CK_INFRA_UART, "infra_uart", CK_TOP_UART_SEL, 1, 1),
349 + TOP_FACTOR(CK_INFRA_ISPI0, "infra_ispi0", CK_TOP_SPI_SEL, 1, 1),
350 + TOP_FACTOR(CK_INFRA_I2C, "infra_i2c", CK_TOP_I2C_SEL, 1, 1),
351 + TOP_FACTOR(CK_INFRA_ISPI1, "infra_ispi1", CK_TOP_SPIM_MST_SEL, 1, 1),
352 + TOP_FACTOR(CK_INFRA_PWM, "infra_pwm", CK_TOP_PWM_SEL, 1, 1),
353 + TOP_FACTOR(CK_INFRA_66M_MCK, "infra_66m_mck", CK_TOP_SYSAXI_SEL, 1, 2),
354 + TOP_FACTOR(CK_INFRA_CK_F32K, "infra_ck_f32k", CK_TOP_CB_RTC_32P7K, 1,
355 + 1),
356 + TOP_FACTOR(CK_INFRA_PCIE_CK, "infra_pcie", CK_TOP_PEXTP_TL_SEL, 1, 1),
357 + INFRA_FACTOR(CK_INFRA_PWM_BCK, "infra_pwm_bck", CK_INFRA_PWM_BSEL, 1,
358 + 1),
359 + INFRA_FACTOR(CK_INFRA_PWM_CK1, "infra_pwm_ck1", CK_INFRA_PWM1_SEL, 1,
360 + 1),
361 + INFRA_FACTOR(CK_INFRA_PWM_CK2, "infra_pwm_ck2", CK_INFRA_PWM2_SEL, 1,
362 + 1),
363 + TOP_FACTOR(CK_INFRA_133M_HCK, "infra_133m_hck", CK_TOP_SYSAXI, 1, 1),
364 + INFRA_FACTOR(CK_INFRA_66M_PHCK, "infra_66m_phck", CK_INFRA_133M_HCK, 1,
365 + 1),
366 + TOP_FACTOR(CK_INFRA_FAUD_L_CK, "infra_faud_l", CK_TOP_AUD_L, 1, 1),
367 + TOP_FACTOR(CK_INFRA_FAUD_AUD_CK, "infra_faud_aud", CK_TOP_A1SYS, 1, 1),
368 + TOP_FACTOR(CK_INFRA_FAUD_EG2_CK, "infra_faud_eg2", CK_TOP_A_TUNER, 1,
369 + 1),
370 + TOP_FACTOR(CK_INFRA_I2CS_CK, "infra_i2cs", CK_TOP_I2C_BCK, 1, 1),
371 + INFRA_FACTOR(CK_INFRA_MUX_UART0, "infra_mux_uart0", CK_INFRA_UART0_SEL,
372 + 1, 1),
373 + INFRA_FACTOR(CK_INFRA_MUX_UART1, "infra_mux_uart1", CK_INFRA_UART1_SEL,
374 + 1, 1),
375 + INFRA_FACTOR(CK_INFRA_MUX_UART2, "infra_mux_uart2", CK_INFRA_UART2_SEL,
376 + 1, 1),
377 + TOP_FACTOR(CK_INFRA_NFI_CK, "infra_nfi", CK_TOP_NFI1X, 1, 1),
378 + TOP_FACTOR(CK_INFRA_SPINFI_CK, "infra_spinfi", CK_TOP_SPINFI_BCK, 1, 1),
379 + INFRA_FACTOR(CK_INFRA_MUX_SPI0, "infra_mux_spi0", CK_INFRA_SPI0_SEL, 1,
380 + 1),
381 + INFRA_FACTOR(CK_INFRA_MUX_SPI1, "infra_mux_spi1", CK_INFRA_SPI1_SEL, 1,
382 + 1),
383 + INFRA_FACTOR(CK_INFRA_MUX_SPI2, "infra_mux_spi2", CK_INFRA_SPI2_SEL, 1,
384 + 1),
385 + TOP_FACTOR(CK_INFRA_RTC_32K, "infra_rtc_32k", CK_TOP_CB_RTC_32K, 1, 1),
386 + TOP_FACTOR(CK_INFRA_FMSDC_CK, "infra_fmsdc", CK_TOP_EMMC_400M, 1, 1),
387 + TOP_FACTOR(CK_INFRA_FMSDC_HCK_CK, "infra_fmsdc_hck", CK_TOP_EMMC_208M,
388 + 1, 1),
389 + TOP_FACTOR(CK_INFRA_PERI_133M, "infra_peri_133m", CK_TOP_SYSAXI, 1, 1),
390 + TOP_FACTOR(CK_INFRA_133M_PHCK, "infra_133m_phck", CK_TOP_SYSAXI, 1, 1),
391 + TOP_FACTOR(CK_INFRA_USB_SYS_CK, "infra_usb_sys", CK_TOP_U2U3_SYS, 1, 1),
392 + TOP_FACTOR(CK_INFRA_USB_CK, "infra_usb", CK_TOP_U2U3_REF, 1, 1),
393 + TOP_FACTOR(CK_INFRA_USB_XHCI_CK, "infra_usb_xhci", CK_TOP_U2U3_XHCI, 1,
394 + 1),
395 + TOP_FACTOR(CK_INFRA_PCIE_GFMUX_TL_O_PRE, "infra_pcie_mux",
396 + CK_TOP_PEXTP_TL, 1, 1),
397 + TOP_FACTOR(CK_INFRA_F26M_CK0, "infra_f26m_ck0", CK_TOP_F26M, 1, 1),
398 + TOP_FACTOR(CK_INFRA_133M_MCK, "infra_133m_mck", CK_TOP_SYSAXI, 1, 1),
399 +};
400 +
401 +/* INFRASYS MUX PARENTS */
402 +static const int infra_uart0_parents[] = { CK_INFRA_CK_F26M, CK_INFRA_UART };
403 +
404 +static const int infra_spi0_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI0 };
405 +
406 +static const int infra_spi1_parents[] = { CK_INFRA_I2C, CK_INFRA_ISPI1 };
407 +
408 +static const int infra_pwm1_parents[] = { -1, -1, -1, CK_INFRA_PWM };
409 +
410 +static const int infra_pwm_bsel_parents[] = { -1, -1, -1, CK_INFRA_PWM };
411 +
412 +static const int infra_pcie_parents[] = { CK_INFRA_CK_F32K, CK_INFRA_CK_F26M,
413 + CK_TOP_CB_CKSQ_40M, CK_INFRA_PCIE_CK};
414 +
415 +#define INFRA_MUX(_id, _name, _parents, _reg, _shift, _width) \
416 + { \
417 + .id = _id, .mux_reg = (_reg) + 0x8, \
418 + .mux_set_reg = (_reg) + 0x0, .mux_clr_reg = (_reg) + 0x4, \
419 + .mux_shift = _shift, .mux_mask = BIT(_width) - 1, \
420 + .parent = _parents, .num_parents = ARRAY_SIZE(_parents), \
421 + .flags = CLK_MUX_SETCLR_UPD | CLK_PARENT_INFRASYS, \
422 + }
423 +
424 +/* INFRA MUX */
425 +static const struct mtk_composite infra_muxes[] = {
426 + INFRA_MUX(CK_INFRA_UART0_SEL, "infra_uart0_sel", infra_uart0_parents,
427 + 0x10, 0, 1),
428 + INFRA_MUX(CK_INFRA_UART1_SEL, "infra_uart1_sel", infra_uart0_parents,
429 + 0x10, 1, 1),
430 + INFRA_MUX(CK_INFRA_UART2_SEL, "infra_uart2_sel", infra_uart0_parents,
431 + 0x10, 2, 1),
432 + INFRA_MUX(CK_INFRA_SPI0_SEL, "infra_spi0_sel", infra_spi0_parents, 0x10,
433 + 4, 1),
434 + INFRA_MUX(CK_INFRA_SPI1_SEL, "infra_spi1_sel", infra_spi1_parents, 0x10,
435 + 5, 1),
436 + INFRA_MUX(CK_INFRA_SPI2_SEL, "infra_spi2_sel", infra_spi0_parents, 0x10,
437 + 6, 1),
438 + INFRA_MUX(CK_INFRA_PWM1_SEL, "infra_pwm1_sel", infra_pwm1_parents, 0x10,
439 + 9, 2),
440 + INFRA_MUX(CK_INFRA_PWM2_SEL, "infra_pwm2_sel", infra_pwm1_parents, 0x10,
441 + 11, 2),
442 + INFRA_MUX(CK_INFRA_PWM_BSEL, "infra_pwm_bsel", infra_pwm_bsel_parents,
443 + 0x10, 13, 2),
444 + INFRA_MUX(CK_INFRA_PCIE_SEL, "infra_pcie_sel", infra_pcie_parents, 0x20,
445 + 0, 2),
446 +};
447 +
448 +static const struct mtk_gate_regs infra_0_cg_regs = {
449 + .set_ofs = 0x40,
450 + .clr_ofs = 0x44,
451 + .sta_ofs = 0x48,
452 +};
453 +
454 +static const struct mtk_gate_regs infra_1_cg_regs = {
455 + .set_ofs = 0x50,
456 + .clr_ofs = 0x54,
457 + .sta_ofs = 0x58,
458 +};
459 +
460 +static const struct mtk_gate_regs infra_2_cg_regs = {
461 + .set_ofs = 0x60,
462 + .clr_ofs = 0x64,
463 + .sta_ofs = 0x68,
464 +};
465 +
466 +#define GATE_INFRA0(_id, _name, _parent, _shift) \
467 + { \
468 + .id = _id, .parent = _parent, .regs = &infra_0_cg_regs, \
469 + .shift = _shift, \
470 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
471 + }
472 +
473 +#define GATE_INFRA1(_id, _name, _parent, _shift) \
474 + { \
475 + .id = _id, .parent = _parent, .regs = &infra_1_cg_regs, \
476 + .shift = _shift, \
477 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
478 + }
479 +
480 +#define GATE_INFRA2(_id, _name, _parent, _shift) \
481 + { \
482 + .id = _id, .parent = _parent, .regs = &infra_2_cg_regs, \
483 + .shift = _shift, \
484 + .flags = CLK_GATE_SETCLR | CLK_PARENT_INFRASYS, \
485 + }
486 +
487 +/* INFRA GATE */
488 +static const struct mtk_gate infracfg_ao_gates[] = {
489 + GATE_INFRA0(CK_INFRA_GPT_STA, "infra_gpt_sta", CK_INFRA_66M_MCK, 0),
490 + GATE_INFRA0(CK_INFRA_PWM_HCK, "infra_pwm_hck", CK_INFRA_66M_MCK, 1),
491 + GATE_INFRA0(CK_INFRA_PWM_STA, "infra_pwm_sta", CK_INFRA_PWM_BCK, 2),
492 + GATE_INFRA0(CK_INFRA_PWM1_CK, "infra_pwm1", CK_INFRA_PWM_CK1, 3),
493 + GATE_INFRA0(CK_INFRA_PWM2_CK, "infra_pwm2", CK_INFRA_PWM_CK2, 4),
494 + GATE_INFRA0(CK_INFRA_CQ_DMA_CK, "infra_cq_dma", CK_INFRA_133M_HCK, 6),
495 + GATE_INFRA0(CK_INFRA_AUD_BUS_CK, "infra_aud_bus", CK_INFRA_66M_PHCK, 8),
496 + GATE_INFRA0(CK_INFRA_AUD_26M_CK, "infra_aud_26m", CK_INFRA_CK_F26M, 9),
497 + GATE_INFRA0(CK_INFRA_AUD_L_CK, "infra_aud_l", CK_INFRA_FAUD_L_CK, 10),
498 + GATE_INFRA0(CK_INFRA_AUD_AUD_CK, "infra_aud_aud", CK_INFRA_FAUD_AUD_CK,
499 + 11),
500 + GATE_INFRA0(CK_INFRA_AUD_EG2_CK, "infra_aud_eg2", CK_INFRA_FAUD_EG2_CK,
501 + 13),
502 + GATE_INFRA0(CK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", CK_INFRA_CK_F26M,
503 + 14),
504 + GATE_INFRA0(CK_INFRA_DBG_CK, "infra_dbg", CK_INFRA_66M_MCK, 15),
505 + GATE_INFRA0(CK_INFRA_AP_DMA_CK, "infra_ap_dma", CK_INFRA_66M_MCK, 16),
506 + GATE_INFRA0(CK_INFRA_SEJ_CK, "infra_sej", CK_INFRA_66M_MCK, 24),
507 + GATE_INFRA0(CK_INFRA_SEJ_13M_CK, "infra_sej_13m", CK_INFRA_CK_F26M, 25),
508 + GATE_INFRA1(CK_INFRA_THERM_CK, "infra_therm", CK_INFRA_CK_F26M, 0),
509 + GATE_INFRA1(CK_INFRA_I2CO_CK, "infra_i2co", CK_INFRA_I2CS_CK, 1),
510 + GATE_INFRA1(CK_INFRA_UART0_CK, "infra_uart0", CK_INFRA_MUX_UART0, 2),
511 + GATE_INFRA1(CK_INFRA_UART1_CK, "infra_uart1", CK_INFRA_MUX_UART1, 3),
512 + GATE_INFRA1(CK_INFRA_UART2_CK, "infra_uart2", CK_INFRA_MUX_UART2, 4),
513 + GATE_INFRA1(CK_INFRA_SPI2_CK, "infra_spi2", CK_INFRA_MUX_SPI2, 6),
514 + GATE_INFRA1(CK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", CK_INFRA_66M_MCK,
515 + 7),
516 + GATE_INFRA1(CK_INFRA_NFI1_CK, "infra_nfi1", CK_INFRA_NFI_CK, 8),
517 + GATE_INFRA1(CK_INFRA_SPINFI1_CK, "infra_spinfi1", CK_INFRA_SPINFI_CK,
518 + 9),
519 + GATE_INFRA1(CK_INFRA_NFI_HCK_CK, "infra_nfi_hck", CK_INFRA_66M_MCK, 10),
520 + GATE_INFRA1(CK_INFRA_SPI0_CK, "infra_spi0", CK_INFRA_MUX_SPI0, 11),
521 + GATE_INFRA1(CK_INFRA_SPI1_CK, "infra_spi1", CK_INFRA_MUX_SPI1, 12),
522 + GATE_INFRA1(CK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", CK_INFRA_66M_MCK,
523 + 13),
524 + GATE_INFRA1(CK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", CK_INFRA_66M_MCK,
525 + 14),
526 + GATE_INFRA1(CK_INFRA_FRTC_CK, "infra_frtc", CK_INFRA_RTC_32K, 15),
527 + GATE_INFRA1(CK_INFRA_MSDC_CK, "infra_msdc", CK_INFRA_FMSDC_CK, 16),
528 + GATE_INFRA1(CK_INFRA_MSDC_HCK_CK, "infra_msdc_hck",
529 + CK_INFRA_FMSDC_HCK_CK, 17),
530 + GATE_INFRA1(CK_INFRA_MSDC_133M_CK, "infra_msdc_133m",
531 + CK_INFRA_PERI_133M, 18),
532 + GATE_INFRA1(CK_INFRA_MSDC_66M_CK, "infra_msdc_66m", CK_INFRA_66M_PHCK,
533 + 19),
534 + GATE_INFRA1(CK_INFRA_ADC_26M_CK, "infra_adc_26m", CK_TOP_F26M, 20),
535 + GATE_INFRA1(CK_INFRA_ADC_FRC_CK, "infra_adc_frc", CK_TOP_F26M, 21),
536 + GATE_INFRA1(CK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", CK_INFRA_NFI_CK,
537 + 23),
538 + GATE_INFRA1(CK_INFRA_I2C_MCK_CK, "infra_i2c_mck", CK_INFRA_133M_MCK,
539 + 25),
540 + GATE_INFRA1(CK_INFRA_I2C_PCK_CK, "infra_i2c_pck", CK_INFRA_66M_MCK, 26),
541 + GATE_INFRA2(CK_INFRA_IUSB_133_CK, "infra_iusb_133", CK_INFRA_133M_PHCK,
542 + 0),
543 + GATE_INFRA2(CK_INFRA_IUSB_66M_CK, "infra_iusb_66m", CK_INFRA_66M_PHCK,
544 + 1),
545 + GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
546 + 2),
547 + GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
548 + GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie",
549 + CK_INFRA_PCIE_GFMUX_TL_O_PRE, 12),
550 + GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
551 + GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
552 +};
553 +
554 +static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
555 + .fdivs_offs = CLK_APMIXED_NR_CLK,
556 + .xtal_rate = 40 * MHZ,
557 + .fclks = fixed_pll_clks,
558 +};
559 +
560 +static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
561 + .fdivs_offs = CK_TOP_CB_M_416M,
562 + .muxes_offs = CK_TOP_NFI1X_SEL,
563 + .fclks = top_fixed_clks,
564 + .fdivs = top_fixed_divs,
565 + .muxes = top_muxes,
566 + .flags = CLK_BYPASS_XTAL,
567 +};
568 +
569 +static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
570 + .fdivs_offs = CK_INFRA_CK_F26M,
571 + .muxes_offs = CK_INFRA_UART0_SEL,
572 + .fdivs = infra_fixed_divs,
573 + .muxes = infra_muxes,
574 +};
575 +
576 +static const struct udevice_id mt7981_fixed_pll_compat[] = {
577 + { .compatible = "mediatek,mt7981-fixed-plls" },
578 + {}
579 +};
580 +
581 +static const struct udevice_id mt7981_topckgen_compat[] = {
582 + { .compatible = "mediatek,mt7981-topckgen" },
583 + {}
584 +};
585 +
586 +static int mt7981_fixed_pll_probe(struct udevice *dev)
587 +{
588 + return mtk_common_clk_init(dev, &mt7981_fixed_pll_clk_tree);
589 +}
590 +
591 +static int mt7981_topckgen_probe(struct udevice *dev)
592 +{
593 + struct mtk_clk_priv *priv = dev_get_priv(dev);
594 +
595 + priv->base = dev_read_addr_ptr(dev);
596 + writel(MT7981_CLK_PDN_EN_WRITE, priv->base + MT7981_CLK_PDN);
597 +
598 + return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree);
599 +}
600 +
601 +U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
602 + .name = "mt7981-clock-fixed-pll",
603 + .id = UCLASS_CLK,
604 + .of_match = mt7981_fixed_pll_compat,
605 + .probe = mt7981_fixed_pll_probe,
606 + .priv_auto = sizeof(struct mtk_clk_priv),
607 + .ops = &mtk_clk_topckgen_ops,
608 + .flags = DM_FLAG_PRE_RELOC,
609 +};
610 +
611 +U_BOOT_DRIVER(mtk_clk_topckgen) = {
612 + .name = "mt7981-clock-topckgen",
613 + .id = UCLASS_CLK,
614 + .of_match = mt7981_topckgen_compat,
615 + .probe = mt7981_topckgen_probe,
616 + .priv_auto = sizeof(struct mtk_clk_priv),
617 + .ops = &mtk_clk_topckgen_ops,
618 + .flags = DM_FLAG_PRE_RELOC,
619 +};
620 +
621 +static const struct udevice_id mt7981_infracfg_compat[] = {
622 + { .compatible = "mediatek,mt7981-infracfg" },
623 + {}
624 +};
625 +
626 +static const struct udevice_id mt7981_infracfg_ao_compat[] = {
627 + { .compatible = "mediatek,mt7981-infracfg_ao" },
628 + {}
629 +};
630 +
631 +static int mt7981_infracfg_probe(struct udevice *dev)
632 +{
633 + return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
634 +}
635 +
636 +static int mt7981_infracfg_ao_probe(struct udevice *dev)
637 +{
638 + return mtk_common_clk_gate_init(dev, &mt7981_infracfg_clk_tree,
639 + infracfg_ao_gates);
640 +}
641 +
642 +U_BOOT_DRIVER(mtk_clk_infracfg) = {
643 + .name = "mt7981-clock-infracfg",
644 + .id = UCLASS_CLK,
645 + .of_match = mt7981_infracfg_compat,
646 + .probe = mt7981_infracfg_probe,
647 + .priv_auto = sizeof(struct mtk_clk_priv),
648 + .ops = &mtk_clk_infrasys_ops,
649 + .flags = DM_FLAG_PRE_RELOC,
650 +};
651 +
652 +U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
653 + .name = "mt7981-clock-infracfg-ao",
654 + .id = UCLASS_CLK,
655 + .of_match = mt7981_infracfg_ao_compat,
656 + .probe = mt7981_infracfg_ao_probe,
657 + .priv_auto = sizeof(struct mtk_cg_priv),
658 + .ops = &mtk_clk_gate_ops,
659 + .flags = DM_FLAG_PRE_RELOC,
660 +};
661 +
662 +/* ethsys */
663 +static const struct mtk_gate_regs eth_cg_regs = {
664 + .set_ofs = 0x30,
665 + .clr_ofs = 0x30,
666 + .sta_ofs = 0x30,
667 +};
668 +
669 +#define GATE_ETH(_id, _name, _parent, _shift) \
670 + { \
671 + .id = _id, .parent = _parent, .regs = &eth_cg_regs, \
672 + .shift = _shift, \
673 + .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
674 + }
675 +
676 +static const struct mtk_gate eth_cgs[] = {
677 + GATE_ETH(CK_ETH_FE_EN, "eth_fe_en", CK_TOP_NETSYS_2X, 6),
678 + GATE_ETH(CK_ETH_GP2_EN, "eth_gp2_en", CK_TOP_SGM_325M, 7),
679 + GATE_ETH(CK_ETH_GP1_EN, "eth_gp1_en", CK_TOP_SGM_325M, 8),
680 + GATE_ETH(CK_ETH_WOCPU0_EN, "eth_wocpu0_en", CK_TOP_NETSYS_WED_MCU, 15),
681 +};
682 +
683 +static int mt7981_ethsys_probe(struct udevice *dev)
684 +{
685 + return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
686 + eth_cgs);
687 +}
688 +
689 +static int mt7981_ethsys_bind(struct udevice *dev)
690 +{
691 + int ret = 0;
692 +
693 + if (CONFIG_IS_ENABLED(RESET_MEDIATEK)) {
694 + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
695 + if (ret)
696 + debug("Warning: failed to bind reset controller\n");
697 + }
698 +
699 + return ret;
700 +}
701 +
702 +static const struct udevice_id mt7981_ethsys_compat[] = {
703 + { .compatible = "mediatek,mt7981-ethsys", },
704 + {}
705 +};
706 +
707 +U_BOOT_DRIVER(mtk_clk_ethsys) = {
708 + .name = "mt7981-clock-ethsys",
709 + .id = UCLASS_CLK,
710 + .of_match = mt7981_ethsys_compat,
711 + .probe = mt7981_ethsys_probe,
712 + .bind = mt7981_ethsys_bind,
713 + .priv_auto = sizeof(struct mtk_cg_priv),
714 + .ops = &mtk_clk_gate_ops,
715 +};
716 --- /dev/null
717 +++ b/include/dt-bindings/clock/mt7981-clk.h
718 @@ -0,0 +1,267 @@
719 +/* SPDX-License-Identifier: GPL-2.0 */
720 +/*
721 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
722 + *
723 + * Author: Sam Shih <sam.shih@mediatek.com>
724 + */
725 +
726 +#ifndef _DT_BINDINGS_CLK_MT7981_H
727 +#define _DT_BINDINGS_CLK_MT7981_H
728 +
729 +/* INFRACFG */
730 +
731 +#define CK_INFRA_CK_F26M 0
732 +#define CK_INFRA_UART 1
733 +#define CK_INFRA_ISPI0 2
734 +#define CK_INFRA_I2C 3
735 +#define CK_INFRA_ISPI1 4
736 +#define CK_INFRA_PWM 5
737 +#define CK_INFRA_66M_MCK 6
738 +#define CK_INFRA_CK_F32K 7
739 +#define CK_INFRA_PCIE_CK 8
740 +#define CK_INFRA_PWM_BCK 9
741 +#define CK_INFRA_PWM_CK1 10
742 +#define CK_INFRA_PWM_CK2 11
743 +#define CK_INFRA_133M_HCK 12
744 +#define CK_INFRA_66M_PHCK 13
745 +#define CK_INFRA_FAUD_L_CK 14
746 +#define CK_INFRA_FAUD_AUD_CK 15
747 +#define CK_INFRA_FAUD_EG2_CK 16
748 +#define CK_INFRA_I2CS_CK 17
749 +#define CK_INFRA_MUX_UART0 18
750 +#define CK_INFRA_MUX_UART1 19
751 +#define CK_INFRA_MUX_UART2 20
752 +#define CK_INFRA_NFI_CK 21
753 +#define CK_INFRA_SPINFI_CK 22
754 +#define CK_INFRA_MUX_SPI0 23
755 +#define CK_INFRA_MUX_SPI1 24
756 +#define CK_INFRA_MUX_SPI2 25
757 +#define CK_INFRA_RTC_32K 26
758 +#define CK_INFRA_FMSDC_CK 27
759 +#define CK_INFRA_FMSDC_HCK_CK 28
760 +#define CK_INFRA_PERI_133M 29
761 +#define CK_INFRA_133M_PHCK 30
762 +#define CK_INFRA_USB_SYS_CK 31
763 +#define CK_INFRA_USB_CK 32
764 +#define CK_INFRA_USB_XHCI_CK 33
765 +#define CK_INFRA_PCIE_GFMUX_TL_O_PRE 34
766 +#define CK_INFRA_F26M_CK0 35
767 +#define CK_INFRA_133M_MCK 36
768 +#define CLK_INFRA_NR_CLK 37
769 +
770 +/* TOPCKGEN */
771 +
772 +#define CK_TOP_CB_CKSQ_40M 0
773 +#define CK_TOP_CB_M_416M 1
774 +#define CK_TOP_CB_M_D2 2
775 +#define CK_TOP_CB_M_D3 3
776 +#define CK_TOP_M_D3_D2 4
777 +#define CK_TOP_CB_M_D4 5
778 +#define CK_TOP_CB_M_D8 6
779 +#define CK_TOP_M_D8_D2 7
780 +#define CK_TOP_CB_MM_720M 8
781 +#define CK_TOP_CB_MM_D2 9
782 +#define CK_TOP_CB_MM_D3 10
783 +#define CK_TOP_CB_MM_D3_D5 11
784 +#define CK_TOP_CB_MM_D4 12
785 +#define CK_TOP_CB_MM_D6 13
786 +#define CK_TOP_MM_D6_D2 14
787 +#define CK_TOP_CB_MM_D8 15
788 +#define CK_TOP_CB_APLL2_196M 16
789 +#define CK_TOP_APLL2_D2 17
790 +#define CK_TOP_APLL2_D4 18
791 +#define CK_TOP_NET1_2500M 19
792 +#define CK_TOP_CB_NET1_D4 20
793 +#define CK_TOP_CB_NET1_D5 21
794 +#define CK_TOP_NET1_D5_D2 22
795 +#define CK_TOP_NET1_D5_D4 23
796 +#define CK_TOP_CB_NET1_D8 24
797 +#define CK_TOP_NET1_D8_D2 25
798 +#define CK_TOP_NET1_D8_D4 26
799 +#define CK_TOP_CB_NET2_800M 27
800 +#define CK_TOP_CB_NET2_D2 28
801 +#define CK_TOP_CB_NET2_D4 29
802 +#define CK_TOP_NET2_D4_D2 30
803 +#define CK_TOP_NET2_D4_D4 31
804 +#define CK_TOP_CB_NET2_D6 32
805 +#define CK_TOP_CB_WEDMCU_208M 33
806 +#define CK_TOP_CB_SGM_325M 34
807 +#define CK_TOP_CKSQ_40M_D2 35
808 +#define CK_TOP_CB_RTC_32K 36
809 +#define CK_TOP_CB_RTC_32P7K 37
810 +#define CK_TOP_USB_TX250M 38
811 +#define CK_TOP_FAUD 39
812 +#define CK_TOP_NFI1X 40
813 +#define CK_TOP_USB_EQ_RX250M 41
814 +#define CK_TOP_USB_CDR_CK 42
815 +#define CK_TOP_USB_LN0_CK 43
816 +#define CK_TOP_SPINFI_BCK 44
817 +#define CK_TOP_SPI 45
818 +#define CK_TOP_SPIM_MST 46
819 +#define CK_TOP_UART_BCK 47
820 +#define CK_TOP_PWM_BCK 48
821 +#define CK_TOP_I2C_BCK 49
822 +#define CK_TOP_PEXTP_TL 50
823 +#define CK_TOP_EMMC_208M 51
824 +#define CK_TOP_EMMC_400M 52
825 +#define CK_TOP_DRAMC_REF 53
826 +#define CK_TOP_DRAMC_MD32 54
827 +#define CK_TOP_SYSAXI 55
828 +#define CK_TOP_SYSAPB 56
829 +#define CK_TOP_ARM_DB_MAIN 57
830 +#define CK_TOP_AP2CNN_HOST 58
831 +#define CK_TOP_NETSYS 59
832 +#define CK_TOP_NETSYS_500M 60
833 +#define CK_TOP_NETSYS_WED_MCU 61
834 +#define CK_TOP_NETSYS_2X 62
835 +#define CK_TOP_SGM_325M 63
836 +#define CK_TOP_SGM_REG 64
837 +#define CK_TOP_F26M 65
838 +#define CK_TOP_EIP97B 66
839 +#define CK_TOP_USB3_PHY 67
840 +#define CK_TOP_AUD 68
841 +#define CK_TOP_A1SYS 69
842 +#define CK_TOP_AUD_L 70
843 +#define CK_TOP_A_TUNER 71
844 +#define CK_TOP_U2U3_REF 72
845 +#define CK_TOP_U2U3_SYS 73
846 +#define CK_TOP_U2U3_XHCI 74
847 +#define CK_TOP_USB_FRMCNT 75
848 +#define CK_TOP_NFI1X_SEL 76
849 +#define CK_TOP_SPINFI_SEL 77
850 +#define CK_TOP_SPI_SEL 78
851 +#define CK_TOP_SPIM_MST_SEL 79
852 +#define CK_TOP_UART_SEL 80
853 +#define CK_TOP_PWM_SEL 81
854 +#define CK_TOP_I2C_SEL 82
855 +#define CK_TOP_PEXTP_TL_SEL 83
856 +#define CK_TOP_EMMC_208M_SEL 84
857 +#define CK_TOP_EMMC_400M_SEL 85
858 +#define CK_TOP_F26M_SEL 86
859 +#define CK_TOP_DRAMC_SEL 87
860 +#define CK_TOP_DRAMC_MD32_SEL 88
861 +#define CK_TOP_SYSAXI_SEL 89
862 +#define CK_TOP_SYSAPB_SEL 90
863 +#define CK_TOP_ARM_DB_MAIN_SEL 91
864 +#define CK_TOP_AP2CNN_HOST_SEL 92
865 +#define CK_TOP_NETSYS_SEL 93
866 +#define CK_TOP_NETSYS_500M_SEL 94
867 +#define CK_TOP_NETSYS_MCU_SEL 95
868 +#define CK_TOP_NETSYS_2X_SEL 96
869 +#define CK_TOP_SGM_325M_SEL 97
870 +#define CK_TOP_SGM_REG_SEL 98
871 +#define CK_TOP_EIP97B_SEL 99
872 +#define CK_TOP_USB3_PHY_SEL 100
873 +#define CK_TOP_AUD_SEL 101
874 +#define CK_TOP_A1SYS_SEL 102
875 +#define CK_TOP_AUD_L_SEL 103
876 +#define CK_TOP_A_TUNER_SEL 104
877 +#define CK_TOP_U2U3_SEL 105
878 +#define CK_TOP_U2U3_SYS_SEL 106
879 +#define CK_TOP_U2U3_XHCI_SEL 107
880 +#define CK_TOP_USB_FRMCNT_SEL 108
881 +#define CLK_TOP_NR_CLK 109
882 +
883 +/*
884 + * INFRACFG_AO
885 + * clock muxes need to be append to infracfg domain, and clock gates
886 + * need to be keep in infracgh_ao domain
887 + */
888 +#define INFRACFG_AO_OFFSET 10
889 +
890 +#define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
891 +#define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
892 +#define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
893 +#define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
894 +#define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
895 +#define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
896 +#define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
897 +#define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
898 +#define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
899 +#define CK_INFRA_PCIE_SEL (9 + CLK_INFRA_NR_CLK)
900 +#define CK_INFRA_GPT_STA (10 - INFRACFG_AO_OFFSET)
901 +#define CK_INFRA_PWM_HCK (11 - INFRACFG_AO_OFFSET)
902 +#define CK_INFRA_PWM_STA (12 - INFRACFG_AO_OFFSET)
903 +#define CK_INFRA_PWM1_CK (13 - INFRACFG_AO_OFFSET)
904 +#define CK_INFRA_PWM2_CK (14 - INFRACFG_AO_OFFSET)
905 +#define CK_INFRA_CQ_DMA_CK (15 - INFRACFG_AO_OFFSET)
906 +#define CK_INFRA_AUD_BUS_CK (16 - INFRACFG_AO_OFFSET)
907 +#define CK_INFRA_AUD_26M_CK (17 - INFRACFG_AO_OFFSET)
908 +#define CK_INFRA_AUD_L_CK (18 - INFRACFG_AO_OFFSET)
909 +#define CK_INFRA_AUD_AUD_CK (19 - INFRACFG_AO_OFFSET)
910 +#define CK_INFRA_AUD_EG2_CK (20 - INFRACFG_AO_OFFSET)
911 +#define CK_INFRA_DRAMC_26M_CK (21 - INFRACFG_AO_OFFSET)
912 +#define CK_INFRA_DBG_CK (22 - INFRACFG_AO_OFFSET)
913 +#define CK_INFRA_AP_DMA_CK (23 - INFRACFG_AO_OFFSET)
914 +#define CK_INFRA_SEJ_CK (24 - INFRACFG_AO_OFFSET)
915 +#define CK_INFRA_SEJ_13M_CK (25 - INFRACFG_AO_OFFSET)
916 +#define CK_INFRA_THERM_CK (26 - INFRACFG_AO_OFFSET)
917 +#define CK_INFRA_I2CO_CK (27 - INFRACFG_AO_OFFSET)
918 +#define CK_INFRA_UART0_CK (28 - INFRACFG_AO_OFFSET)
919 +#define CK_INFRA_UART1_CK (29 - INFRACFG_AO_OFFSET)
920 +#define CK_INFRA_UART2_CK (30 - INFRACFG_AO_OFFSET)
921 +#define CK_INFRA_SPI2_CK (31 - INFRACFG_AO_OFFSET)
922 +#define CK_INFRA_SPI2_HCK_CK (32 - INFRACFG_AO_OFFSET)
923 +#define CK_INFRA_NFI1_CK (33 - INFRACFG_AO_OFFSET)
924 +#define CK_INFRA_SPINFI1_CK (34 - INFRACFG_AO_OFFSET)
925 +#define CK_INFRA_NFI_HCK_CK (35 - INFRACFG_AO_OFFSET)
926 +#define CK_INFRA_SPI0_CK (36 - INFRACFG_AO_OFFSET)
927 +#define CK_INFRA_SPI1_CK (37 - INFRACFG_AO_OFFSET)
928 +#define CK_INFRA_SPI0_HCK_CK (38 - INFRACFG_AO_OFFSET)
929 +#define CK_INFRA_SPI1_HCK_CK (39 - INFRACFG_AO_OFFSET)
930 +#define CK_INFRA_FRTC_CK (40 - INFRACFG_AO_OFFSET)
931 +#define CK_INFRA_MSDC_CK (41 - INFRACFG_AO_OFFSET)
932 +#define CK_INFRA_MSDC_HCK_CK (42 - INFRACFG_AO_OFFSET)
933 +#define CK_INFRA_MSDC_133M_CK (43 - INFRACFG_AO_OFFSET)
934 +#define CK_INFRA_MSDC_66M_CK (44 - INFRACFG_AO_OFFSET)
935 +#define CK_INFRA_ADC_26M_CK (45 - INFRACFG_AO_OFFSET)
936 +#define CK_INFRA_ADC_FRC_CK (46 - INFRACFG_AO_OFFSET)
937 +#define CK_INFRA_FBIST2FPC_CK (47 - INFRACFG_AO_OFFSET)
938 +#define CK_INFRA_I2C_MCK_CK (48 - INFRACFG_AO_OFFSET)
939 +#define CK_INFRA_I2C_PCK_CK (49 - INFRACFG_AO_OFFSET)
940 +#define CK_INFRA_IUSB_133_CK (50 - INFRACFG_AO_OFFSET)
941 +#define CK_INFRA_IUSB_66M_CK (51 - INFRACFG_AO_OFFSET)
942 +#define CK_INFRA_IUSB_SYS_CK (52 - INFRACFG_AO_OFFSET)
943 +#define CK_INFRA_IUSB_CK (53 - INFRACFG_AO_OFFSET)
944 +#define CK_INFRA_IPCIE_CK (54 - INFRACFG_AO_OFFSET)
945 +#define CK_INFRA_IPCIER_CK (55 - INFRACFG_AO_OFFSET)
946 +#define CK_INFRA_IPCIEB_CK (56 - INFRACFG_AO_OFFSET)
947 +#define CLK_INFRA_AO_NR_CLK (57 - INFRACFG_AO_OFFSET)
948 +
949 +/* APMIXEDSYS */
950 +
951 +#define CK_APMIXED_ARMPLL 0
952 +#define CK_APMIXED_NET2PLL 1
953 +#define CK_APMIXED_MMPLL 2
954 +#define CK_APMIXED_SGMPLL 3
955 +#define CK_APMIXED_WEDMCUPLL 4
956 +#define CK_APMIXED_NET1PLL 5
957 +#define CK_APMIXED_MPLL 6
958 +#define CK_APMIXED_APLL2 7
959 +#define CLK_APMIXED_NR_CLK 8
960 +
961 +/* SGMIISYS_0 */
962 +
963 +#define CK_SGM0_TX_EN 0
964 +#define CK_SGM0_RX_EN 1
965 +#define CK_SGM0_CK0_EN 2
966 +#define CK_SGM0_CDR_CK0_EN 3
967 +#define CLK_SGMII0_NR_CLK 4
968 +
969 +/* SGMIISYS_1 */
970 +
971 +#define CK_SGM1_TX_EN 0
972 +#define CK_SGM1_RX_EN 1
973 +#define CK_SGM1_CK1_EN 2
974 +#define CK_SGM1_CDR_CK1_EN 3
975 +#define CLK_SGMII1_NR_CLK 4
976 +
977 +/* ETHSYS */
978 +
979 +#define CK_ETH_FE_EN 0
980 +#define CK_ETH_GP2_EN 1
981 +#define CK_ETH_GP1_EN 2
982 +#define CK_ETH_WOCPU0_EN 3
983 +#define CLK_ETH_NR_CLK 4
984 +
985 +#endif /* _DT_BINDINGS_CLK_MT7981_H */
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