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1 From 86db870d9e00b71fb3bd2c8a1a72cda971d9a77d Mon Sep 17 00:00:00 2001
2 From: Devi Priya <quic_devipriy@quicinc.com>
3 Date: Fri, 25 Oct 2024 09:25:18 +0530
4 Subject: [PATCH 5/7] clk: qcom: Add NSS clock Controller driver for IPQ9574
5
6 Add Networking Sub System Clock Controller(NSSCC) driver for ipq9574 based
7 devices.
8
9 Reported-by: kernel test robot <lkp@intel.com>
10 Closes: https://lore.kernel.org/oe-kbuild-all/202410101431.tjpSRNTY-lkp@intel.com/
11 Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
12 Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
13 ---
14 drivers/clk/qcom/Kconfig | 7 +
15 drivers/clk/qcom/Makefile | 1 +
16 drivers/clk/qcom/nsscc-ipq9574.c | 3080 ++++++++++++++++++++++++++++++
17 3 files changed, 3088 insertions(+)
18 create mode 100644 drivers/clk/qcom/nsscc-ipq9574.c
19
20 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
21 index a3e2a09e2105..b9a5cc9fd8c8 100644
22 --- a/drivers/clk/qcom/Kconfig
23 +++ b/drivers/clk/qcom/Kconfig
24 @@ -255,6 +255,13 @@ config IPQ_GCC_9574
25 i2c, USB, SD/eMMC, etc. Select this for the root clock
26 of ipq9574.
27
28 +config IPQ_NSSCC_9574
29 + tristate "IPQ9574 NSS Clock Controller"
30 + depends on ARM64 || COMPILE_TEST
31 + depends on IPQ_GCC_9574
32 + help
33 + Support for NSS clock controller on ipq9574 devices.
34 +
35 config IPQ_NSSCC_QCA8K
36 tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller"
37 depends on MDIO_BUS
38 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
39 index 2b378667a63f..65b825a54c45 100644
40 --- a/drivers/clk/qcom/Makefile
41 +++ b/drivers/clk/qcom/Makefile
42 @@ -36,6 +36,7 @@ obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
43 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
44 obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
45 obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
46 +obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
47 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
48 obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
49 obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
50 diff --git a/drivers/clk/qcom/nsscc-ipq9574.c b/drivers/clk/qcom/nsscc-ipq9574.c
51 new file mode 100644
52 index 000000000000..d3e9aa391236
53 --- /dev/null
54 +++ b/drivers/clk/qcom/nsscc-ipq9574.c
55 @@ -0,0 +1,3080 @@
56 +// SPDX-License-Identifier: GPL-2.0-only
57 +/*
58 + * Copyright (c) 2021, The Linux Foundation. All rights reserved.
59 + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
60 + */
61 +
62 +#include <linux/clk.h>
63 +#include <linux/clk-provider.h>
64 +#include <linux/err.h>
65 +#include <linux/interconnect-provider.h>
66 +#include <linux/kernel.h>
67 +#include <linux/module.h>
68 +#include <linux/of.h>
69 +#include <linux/of_device.h>
70 +#include <linux/regmap.h>
71 +#include <linux/platform_device.h>
72 +
73 +#include <dt-bindings/clock/qcom,ipq9574-nsscc.h>
74 +#include <dt-bindings/interconnect/qcom,ipq9574.h>
75 +#include <dt-bindings/reset/qcom,ipq9574-nsscc.h>
76 +
77 +#include "clk-alpha-pll.h"
78 +#include "clk-branch.h"
79 +#include "clk-pll.h"
80 +#include "clk-rcg.h"
81 +#include "clk-regmap.h"
82 +#include "clk-regmap-divider.h"
83 +#include "clk-regmap-mux.h"
84 +#include "common.h"
85 +#include "reset.h"
86 +
87 +/* Need to match the order of clocks in DT binding */
88 +enum {
89 + DT_XO,
90 + DT_BIAS_PLL_CC_CLK,
91 + DT_BIAS_PLL_UBI_NC_CLK,
92 + DT_GCC_GPLL0_OUT_AUX,
93 + DT_UNIPHY0_NSS_RX_CLK,
94 + DT_UNIPHY0_NSS_TX_CLK,
95 + DT_UNIPHY1_NSS_RX_CLK,
96 + DT_UNIPHY1_NSS_TX_CLK,
97 + DT_UNIPHY2_NSS_RX_CLK,
98 + DT_UNIPHY2_NSS_TX_CLK,
99 +};
100 +
101 +enum {
102 + P_XO,
103 + P_BIAS_PLL_CC_CLK,
104 + P_BIAS_PLL_UBI_NC_CLK,
105 + P_GCC_GPLL0_OUT_AUX,
106 + P_UBI32_PLL_OUT_MAIN,
107 + P_UNIPHY0_NSS_RX_CLK,
108 + P_UNIPHY0_NSS_TX_CLK,
109 + P_UNIPHY1_NSS_RX_CLK,
110 + P_UNIPHY1_NSS_TX_CLK,
111 + P_UNIPHY2_NSS_RX_CLK,
112 + P_UNIPHY2_NSS_TX_CLK,
113 +};
114 +
115 +static const struct alpha_pll_config ubi32_pll_config = {
116 + .l = 0x3e,
117 + .alpha = 0x6666,
118 + .config_ctl_val = 0x200d4aa8,
119 + .config_ctl_hi_val = 0x3c,
120 + .main_output_mask = BIT(0),
121 + .aux_output_mask = BIT(1),
122 + .pre_div_val = 0x0,
123 + .pre_div_mask = BIT(12),
124 + .post_div_val = 0x0,
125 + .post_div_mask = GENMASK(9, 8),
126 + .alpha_en_mask = BIT(24),
127 + .test_ctl_val = 0x1c0000c0,
128 + .test_ctl_hi_val = 0x4000,
129 +};
130 +
131 +static struct clk_alpha_pll ubi32_pll_main = {
132 + .offset = 0x28000,
133 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
134 + .flags = SUPPORTS_DYNAMIC_UPDATE,
135 + .clkr = {
136 + .hw.init = &(const struct clk_init_data) {
137 + .name = "ubi32_pll_main",
138 + .parent_data = &(const struct clk_parent_data) {
139 + .index = DT_XO,
140 + },
141 + .num_parents = 1,
142 + .ops = &clk_alpha_pll_huayra_ops,
143 + },
144 + },
145 +};
146 +
147 +static struct clk_alpha_pll_postdiv ubi32_pll = {
148 + .offset = 0x28000,
149 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
150 + .width = 2,
151 + .clkr.hw.init = &(const struct clk_init_data) {
152 + .name = "ubi32_pll",
153 + .parent_hws = (const struct clk_hw *[]) {
154 + &ubi32_pll_main.clkr.hw
155 + },
156 + .num_parents = 1,
157 + .ops = &clk_alpha_pll_postdiv_ro_ops,
158 + .flags = CLK_SET_RATE_PARENT,
159 + },
160 +};
161 +
162 +static const struct parent_map nss_cc_parent_map_0[] = {
163 + { P_XO, 0 },
164 + { P_BIAS_PLL_CC_CLK, 1 },
165 + { P_UNIPHY0_NSS_RX_CLK, 2 },
166 + { P_UNIPHY0_NSS_TX_CLK, 3 },
167 + { P_UNIPHY1_NSS_RX_CLK, 4 },
168 + { P_UNIPHY1_NSS_TX_CLK, 5 },
169 +};
170 +
171 +static const struct clk_parent_data nss_cc_parent_data_0[] = {
172 + { .index = DT_XO },
173 + { .index = DT_BIAS_PLL_CC_CLK },
174 + { .index = DT_UNIPHY0_NSS_RX_CLK },
175 + { .index = DT_UNIPHY0_NSS_TX_CLK },
176 + { .index = DT_UNIPHY1_NSS_RX_CLK },
177 + { .index = DT_UNIPHY1_NSS_TX_CLK },
178 +};
179 +
180 +static const struct parent_map nss_cc_parent_map_1[] = {
181 + { P_XO, 0 },
182 + { P_BIAS_PLL_UBI_NC_CLK, 1 },
183 + { P_GCC_GPLL0_OUT_AUX, 2 },
184 + { P_BIAS_PLL_CC_CLK, 6 },
185 +};
186 +
187 +static const struct clk_parent_data nss_cc_parent_data_1[] = {
188 + { .index = DT_XO },
189 + { .index = DT_BIAS_PLL_UBI_NC_CLK },
190 + { .index = DT_GCC_GPLL0_OUT_AUX },
191 + { .index = DT_BIAS_PLL_CC_CLK },
192 +};
193 +
194 +static const struct parent_map nss_cc_parent_map_2[] = {
195 + { P_XO, 0 },
196 + { P_UBI32_PLL_OUT_MAIN, 1 },
197 + { P_GCC_GPLL0_OUT_AUX, 2 },
198 +};
199 +
200 +static const struct clk_parent_data nss_cc_parent_data_2[] = {
201 + { .index = DT_XO },
202 + { .hw = &ubi32_pll.clkr.hw },
203 + { .index = DT_GCC_GPLL0_OUT_AUX },
204 +};
205 +
206 +static const struct parent_map nss_cc_parent_map_3[] = {
207 + { P_XO, 0 },
208 + { P_BIAS_PLL_CC_CLK, 1 },
209 + { P_GCC_GPLL0_OUT_AUX, 2 },
210 +};
211 +
212 +static const struct clk_parent_data nss_cc_parent_data_3[] = {
213 + { .index = DT_XO },
214 + { .index = DT_BIAS_PLL_CC_CLK },
215 + { .index = DT_GCC_GPLL0_OUT_AUX },
216 +};
217 +
218 +static const struct parent_map nss_cc_parent_map_4[] = {
219 + { P_XO, 0 },
220 + { P_BIAS_PLL_CC_CLK, 1 },
221 + { P_UNIPHY0_NSS_RX_CLK, 2 },
222 + { P_UNIPHY0_NSS_TX_CLK, 3 },
223 +};
224 +
225 +static const struct clk_parent_data nss_cc_parent_data_4[] = {
226 + { .index = DT_XO },
227 + { .index = DT_BIAS_PLL_CC_CLK },
228 + { .index = DT_UNIPHY0_NSS_RX_CLK },
229 + { .index = DT_UNIPHY0_NSS_TX_CLK },
230 +};
231 +
232 +static const struct parent_map nss_cc_parent_map_5[] = {
233 + { P_XO, 0 },
234 + { P_BIAS_PLL_CC_CLK, 1 },
235 + { P_UNIPHY2_NSS_RX_CLK, 2 },
236 + { P_UNIPHY2_NSS_TX_CLK, 3 },
237 +};
238 +
239 +static const struct clk_parent_data nss_cc_parent_data_5[] = {
240 + { .index = DT_XO },
241 + { .index = DT_BIAS_PLL_CC_CLK },
242 + { .index = DT_UNIPHY2_NSS_RX_CLK },
243 + { .index = DT_UNIPHY2_NSS_TX_CLK },
244 +};
245 +
246 +static const struct parent_map nss_cc_parent_map_6[] = {
247 + { P_XO, 0 },
248 + { P_GCC_GPLL0_OUT_AUX, 2 },
249 + { P_BIAS_PLL_CC_CLK, 6 },
250 +};
251 +
252 +static const struct clk_parent_data nss_cc_parent_data_6[] = {
253 + { .index = DT_XO },
254 + { .index = DT_GCC_GPLL0_OUT_AUX },
255 + { .index = DT_BIAS_PLL_CC_CLK },
256 +};
257 +
258 +static const struct parent_map nss_cc_parent_map_7[] = {
259 + { P_XO, 0 },
260 + { P_UBI32_PLL_OUT_MAIN, 1 },
261 + { P_GCC_GPLL0_OUT_AUX, 2 },
262 + { P_BIAS_PLL_CC_CLK, 6 },
263 +};
264 +
265 +static const struct clk_parent_data nss_cc_parent_data_7[] = {
266 + { .index = DT_XO },
267 + { .hw = &ubi32_pll.clkr.hw },
268 + { .index = DT_GCC_GPLL0_OUT_AUX },
269 + { .index = DT_BIAS_PLL_CC_CLK },
270 +};
271 +
272 +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
273 + F(24000000, P_XO, 1, 0, 0),
274 + F(353000000, P_BIAS_PLL_UBI_NC_CLK, 1, 0, 0),
275 + { }
276 +};
277 +
278 +static struct clk_rcg2 nss_cc_ce_clk_src = {
279 + .cmd_rcgr = 0x28404,
280 + .mnd_width = 0,
281 + .hid_width = 5,
282 + .parent_map = nss_cc_parent_map_1,
283 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
284 + .clkr.hw.init = &(const struct clk_init_data) {
285 + .name = "nss_cc_ce_clk_src",
286 + .parent_data = nss_cc_parent_data_1,
287 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
288 + .ops = &clk_rcg2_ops,
289 + },
290 +};
291 +
292 +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
293 + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
294 + { }
295 +};
296 +
297 +static struct clk_rcg2 nss_cc_cfg_clk_src = {
298 + .cmd_rcgr = 0x28104,
299 + .mnd_width = 0,
300 + .hid_width = 5,
301 + .parent_map = nss_cc_parent_map_3,
302 + .freq_tbl = ftbl_nss_cc_cfg_clk_src,
303 + .clkr.hw.init = &(const struct clk_init_data) {
304 + .name = "nss_cc_cfg_clk_src",
305 + .parent_data = nss_cc_parent_data_3,
306 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
307 + .ops = &clk_rcg2_ops,
308 + },
309 +};
310 +
311 +static const struct freq_tbl ftbl_nss_cc_clc_clk_src[] = {
312 + F(533333333, P_GCC_GPLL0_OUT_AUX, 1.5, 0, 0),
313 + { }
314 +};
315 +
316 +static struct clk_rcg2 nss_cc_clc_clk_src = {
317 + .cmd_rcgr = 0x28604,
318 + .mnd_width = 0,
319 + .hid_width = 5,
320 + .parent_map = nss_cc_parent_map_6,
321 + .freq_tbl = ftbl_nss_cc_clc_clk_src,
322 + .clkr.hw.init = &(const struct clk_init_data) {
323 + .name = "nss_cc_clc_clk_src",
324 + .parent_data = nss_cc_parent_data_6,
325 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_6),
326 + .ops = &clk_rcg2_ops,
327 + },
328 +};
329 +
330 +static const struct freq_tbl ftbl_nss_cc_crypto_clk_src[] = {
331 + F(24000000, P_XO, 1, 0, 0),
332 + F(300000000, P_BIAS_PLL_CC_CLK, 4, 0, 0),
333 + F(600000000, P_BIAS_PLL_CC_CLK, 2, 0, 0),
334 + { }
335 +};
336 +
337 +static struct clk_rcg2 nss_cc_crypto_clk_src = {
338 + .cmd_rcgr = 0x16008,
339 + .mnd_width = 16,
340 + .hid_width = 5,
341 + .parent_map = nss_cc_parent_map_3,
342 + .freq_tbl = ftbl_nss_cc_crypto_clk_src,
343 + .clkr.hw.init = &(const struct clk_init_data) {
344 + .name = "nss_cc_crypto_clk_src",
345 + .parent_data = nss_cc_parent_data_3,
346 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
347 + .flags = CLK_SET_RATE_PARENT,
348 + .ops = &clk_rcg2_ops,
349 + },
350 +};
351 +
352 +static struct clk_rcg2 nss_cc_haq_clk_src = {
353 + .cmd_rcgr = 0x28304,
354 + .mnd_width = 0,
355 + .hid_width = 5,
356 + .parent_map = nss_cc_parent_map_1,
357 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
358 + .clkr.hw.init = &(const struct clk_init_data) {
359 + .name = "nss_cc_haq_clk_src",
360 + .parent_data = nss_cc_parent_data_1,
361 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
362 + .ops = &clk_rcg2_ops,
363 + },
364 +};
365 +
366 +static struct clk_rcg2 nss_cc_imem_clk_src = {
367 + .cmd_rcgr = 0xe008,
368 + .mnd_width = 0,
369 + .hid_width = 5,
370 + .parent_map = nss_cc_parent_map_1,
371 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
372 + .clkr.hw.init = &(const struct clk_init_data) {
373 + .name = "nss_cc_imem_clk_src",
374 + .parent_data = nss_cc_parent_data_1,
375 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
376 + .ops = &clk_rcg2_ops,
377 + },
378 +};
379 +
380 +static const struct freq_tbl ftbl_nss_cc_int_cfg_clk_src[] = {
381 + F(200000000, P_GCC_GPLL0_OUT_AUX, 4, 0, 0),
382 + { }
383 +};
384 +
385 +static struct clk_rcg2 nss_cc_int_cfg_clk_src = {
386 + .cmd_rcgr = 0x287b4,
387 + .mnd_width = 0,
388 + .hid_width = 5,
389 + .parent_map = nss_cc_parent_map_3,
390 + .freq_tbl = ftbl_nss_cc_int_cfg_clk_src,
391 + .clkr.hw.init = &(const struct clk_init_data) {
392 + .name = "nss_cc_int_cfg_clk_src",
393 + .parent_data = nss_cc_parent_data_3,
394 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
395 + .ops = &clk_rcg2_ops,
396 + },
397 +};
398 +
399 +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
400 + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
401 + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
402 +};
403 +
404 +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
405 + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
406 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
407 +};
408 +
409 +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
410 + FMS(24000000, P_XO, 1, 0, 0),
411 + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
412 + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
413 + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
414 + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
415 + { }
416 +};
417 +
418 +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
419 + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
420 + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
421 +};
422 +
423 +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
424 + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
425 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
426 +};
427 +
428 +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
429 + FMS(24000000, P_XO, 1, 0, 0),
430 + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
431 + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
432 + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
433 + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
434 + { }
435 +};
436 +
437 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
438 + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
439 + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
440 +};
441 +
442 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
443 + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
444 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
445 +};
446 +
447 +static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_312p5[] = {
448 + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
449 + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
450 +};
451 +
452 +static const struct freq_multi_tbl ftbl_nss_cc_port5_rx_clk_src[] = {
453 + FMS(24000000, P_XO, 1, 0, 0),
454 + FM(25000000, ftbl_nss_cc_port5_rx_clk_src_25),
455 + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
456 + FM(125000000, ftbl_nss_cc_port5_rx_clk_src_125),
457 + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
458 + FM(312500000, ftbl_nss_cc_port5_rx_clk_src_312p5),
459 + { }
460 +};
461 +
462 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
463 + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
464 + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
465 +};
466 +
467 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
468 + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
469 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
470 +};
471 +
472 +static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_312p5[] = {
473 + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
474 + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
475 +};
476 +
477 +static const struct freq_multi_tbl ftbl_nss_cc_port5_tx_clk_src[] = {
478 + FMS(24000000, P_XO, 1, 0, 0),
479 + FM(25000000, ftbl_nss_cc_port5_tx_clk_src_25),
480 + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
481 + FM(125000000, ftbl_nss_cc_port5_tx_clk_src_125),
482 + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
483 + FM(312500000, ftbl_nss_cc_port5_tx_clk_src_312p5),
484 + { }
485 +};
486 +
487 +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_25[] = {
488 + C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
489 + C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
490 +};
491 +
492 +static const struct freq_conf ftbl_nss_cc_port6_rx_clk_src_125[] = {
493 + C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
494 + C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
495 +};
496 +
497 +static const struct freq_multi_tbl ftbl_nss_cc_port6_rx_clk_src[] = {
498 + FMS(24000000, P_XO, 1, 0, 0),
499 + FM(25000000, ftbl_nss_cc_port6_rx_clk_src_25),
500 + FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
501 + FM(125000000, ftbl_nss_cc_port6_rx_clk_src_125),
502 + FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
503 + FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
504 + { }
505 +};
506 +
507 +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_25[] = {
508 + C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
509 + C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
510 +};
511 +
512 +static const struct freq_conf ftbl_nss_cc_port6_tx_clk_src_125[] = {
513 + C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
514 + C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
515 +};
516 +
517 +static const struct freq_multi_tbl ftbl_nss_cc_port6_tx_clk_src[] = {
518 + FMS(24000000, P_XO, 1, 0, 0),
519 + FM(25000000, ftbl_nss_cc_port6_tx_clk_src_25),
520 + FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
521 + FM(125000000, ftbl_nss_cc_port6_tx_clk_src_125),
522 + FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
523 + FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
524 + { }
525 +};
526 +
527 +static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
528 + .cmd_rcgr = 0x28110,
529 + .mnd_width = 0,
530 + .hid_width = 5,
531 + .parent_map = nss_cc_parent_map_4,
532 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
533 + .clkr.hw.init = &(const struct clk_init_data) {
534 + .name = "nss_cc_port1_rx_clk_src",
535 + .parent_data = nss_cc_parent_data_4,
536 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
537 + .ops = &clk_rcg2_fm_ops,
538 + },
539 +};
540 +
541 +static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
542 + .cmd_rcgr = 0x2811c,
543 + .mnd_width = 0,
544 + .hid_width = 5,
545 + .parent_map = nss_cc_parent_map_4,
546 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
547 + .clkr.hw.init = &(const struct clk_init_data) {
548 + .name = "nss_cc_port1_tx_clk_src",
549 + .parent_data = nss_cc_parent_data_4,
550 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
551 + .ops = &clk_rcg2_fm_ops,
552 + },
553 +};
554 +
555 +static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
556 + .cmd_rcgr = 0x28128,
557 + .mnd_width = 0,
558 + .hid_width = 5,
559 + .parent_map = nss_cc_parent_map_4,
560 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
561 + .clkr.hw.init = &(const struct clk_init_data) {
562 + .name = "nss_cc_port2_rx_clk_src",
563 + .parent_data = nss_cc_parent_data_4,
564 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
565 + .ops = &clk_rcg2_fm_ops,
566 + },
567 +};
568 +
569 +static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
570 + .cmd_rcgr = 0x28134,
571 + .mnd_width = 0,
572 + .hid_width = 5,
573 + .parent_map = nss_cc_parent_map_4,
574 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
575 + .clkr.hw.init = &(const struct clk_init_data) {
576 + .name = "nss_cc_port2_tx_clk_src",
577 + .parent_data = nss_cc_parent_data_4,
578 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
579 + .ops = &clk_rcg2_fm_ops,
580 + },
581 +};
582 +
583 +static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
584 + .cmd_rcgr = 0x28140,
585 + .mnd_width = 0,
586 + .hid_width = 5,
587 + .parent_map = nss_cc_parent_map_4,
588 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
589 + .clkr.hw.init = &(const struct clk_init_data) {
590 + .name = "nss_cc_port3_rx_clk_src",
591 + .parent_data = nss_cc_parent_data_4,
592 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
593 + .ops = &clk_rcg2_fm_ops,
594 + },
595 +};
596 +
597 +static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
598 + .cmd_rcgr = 0x2814c,
599 + .mnd_width = 0,
600 + .hid_width = 5,
601 + .parent_map = nss_cc_parent_map_4,
602 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
603 + .clkr.hw.init = &(const struct clk_init_data) {
604 + .name = "nss_cc_port3_tx_clk_src",
605 + .parent_data = nss_cc_parent_data_4,
606 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
607 + .ops = &clk_rcg2_fm_ops,
608 + },
609 +};
610 +
611 +static struct clk_rcg2 nss_cc_port4_rx_clk_src = {
612 + .cmd_rcgr = 0x28158,
613 + .mnd_width = 0,
614 + .hid_width = 5,
615 + .parent_map = nss_cc_parent_map_4,
616 + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
617 + .clkr.hw.init = &(const struct clk_init_data) {
618 + .name = "nss_cc_port4_rx_clk_src",
619 + .parent_data = nss_cc_parent_data_4,
620 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
621 + .ops = &clk_rcg2_fm_ops,
622 + },
623 +};
624 +
625 +static struct clk_rcg2 nss_cc_port4_tx_clk_src = {
626 + .cmd_rcgr = 0x28164,
627 + .mnd_width = 0,
628 + .hid_width = 5,
629 + .parent_map = nss_cc_parent_map_4,
630 + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
631 + .clkr.hw.init = &(const struct clk_init_data) {
632 + .name = "nss_cc_port4_tx_clk_src",
633 + .parent_data = nss_cc_parent_data_4,
634 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_4),
635 + .ops = &clk_rcg2_fm_ops,
636 + },
637 +};
638 +
639 +static struct clk_rcg2 nss_cc_port5_rx_clk_src = {
640 + .cmd_rcgr = 0x28170,
641 + .mnd_width = 0,
642 + .hid_width = 5,
643 + .parent_map = nss_cc_parent_map_0,
644 + .freq_multi_tbl = ftbl_nss_cc_port5_rx_clk_src,
645 + .clkr.hw.init = &(const struct clk_init_data) {
646 + .name = "nss_cc_port5_rx_clk_src",
647 + .parent_data = nss_cc_parent_data_0,
648 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
649 + .ops = &clk_rcg2_fm_ops,
650 + },
651 +};
652 +
653 +static struct clk_rcg2 nss_cc_port5_tx_clk_src = {
654 + .cmd_rcgr = 0x2817c,
655 + .mnd_width = 0,
656 + .hid_width = 5,
657 + .parent_map = nss_cc_parent_map_0,
658 + .freq_multi_tbl = ftbl_nss_cc_port5_tx_clk_src,
659 + .clkr.hw.init = &(const struct clk_init_data) {
660 + .name = "nss_cc_port5_tx_clk_src",
661 + .parent_data = nss_cc_parent_data_0,
662 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
663 + .ops = &clk_rcg2_fm_ops,
664 + },
665 +};
666 +
667 +static struct clk_rcg2 nss_cc_port6_rx_clk_src = {
668 + .cmd_rcgr = 0x28188,
669 + .mnd_width = 0,
670 + .hid_width = 5,
671 + .parent_map = nss_cc_parent_map_5,
672 + .freq_multi_tbl = ftbl_nss_cc_port6_rx_clk_src,
673 + .clkr.hw.init = &(const struct clk_init_data) {
674 + .name = "nss_cc_port6_rx_clk_src",
675 + .parent_data = nss_cc_parent_data_5,
676 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
677 + .ops = &clk_rcg2_fm_ops,
678 + },
679 +};
680 +
681 +static struct clk_rcg2 nss_cc_port6_tx_clk_src = {
682 + .cmd_rcgr = 0x28194,
683 + .mnd_width = 0,
684 + .hid_width = 5,
685 + .parent_map = nss_cc_parent_map_5,
686 + .freq_multi_tbl = ftbl_nss_cc_port6_tx_clk_src,
687 + .clkr.hw.init = &(const struct clk_init_data) {
688 + .name = "nss_cc_port6_tx_clk_src",
689 + .parent_data = nss_cc_parent_data_5,
690 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_5),
691 + .ops = &clk_rcg2_fm_ops,
692 + },
693 +};
694 +
695 +static struct clk_rcg2 nss_cc_ppe_clk_src = {
696 + .cmd_rcgr = 0x28204,
697 + .mnd_width = 0,
698 + .hid_width = 5,
699 + .parent_map = nss_cc_parent_map_1,
700 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
701 + .clkr.hw.init = &(const struct clk_init_data) {
702 + .name = "nss_cc_ppe_clk_src",
703 + .parent_data = nss_cc_parent_data_1,
704 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
705 + .flags = CLK_SET_RATE_PARENT,
706 + .ops = &clk_rcg2_ops,
707 + },
708 +};
709 +
710 +static const struct freq_tbl ftbl_nss_cc_ubi0_clk_src[] = {
711 + F(24000000, P_XO, 1, 0, 0),
712 + F(187200000, P_UBI32_PLL_OUT_MAIN, 8, 0, 0),
713 + F(748800000, P_UBI32_PLL_OUT_MAIN, 2, 0, 0),
714 + F(1497600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
715 + F(1689600000, P_UBI32_PLL_OUT_MAIN, 1, 0, 0),
716 + { }
717 +};
718 +
719 +static struct clk_rcg2 nss_cc_ubi0_clk_src = {
720 + .cmd_rcgr = 0x28704,
721 + .mnd_width = 0,
722 + .hid_width = 5,
723 + .parent_map = nss_cc_parent_map_2,
724 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
725 + .clkr.hw.init = &(const struct clk_init_data) {
726 + .name = "nss_cc_ubi0_clk_src",
727 + .parent_data = nss_cc_parent_data_2,
728 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
729 + .flags = CLK_SET_RATE_PARENT,
730 + .ops = &clk_rcg2_ops,
731 + },
732 +};
733 +
734 +static struct clk_rcg2 nss_cc_ubi1_clk_src = {
735 + .cmd_rcgr = 0x2870c,
736 + .mnd_width = 0,
737 + .hid_width = 5,
738 + .parent_map = nss_cc_parent_map_2,
739 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
740 + .clkr.hw.init = &(const struct clk_init_data) {
741 + .name = "nss_cc_ubi1_clk_src",
742 + .parent_data = nss_cc_parent_data_2,
743 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
744 + .flags = CLK_SET_RATE_PARENT,
745 + .ops = &clk_rcg2_ops,
746 + },
747 +};
748 +
749 +static struct clk_rcg2 nss_cc_ubi2_clk_src = {
750 + .cmd_rcgr = 0x28714,
751 + .mnd_width = 0,
752 + .hid_width = 5,
753 + .parent_map = nss_cc_parent_map_2,
754 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
755 + .clkr.hw.init = &(const struct clk_init_data) {
756 + .name = "nss_cc_ubi2_clk_src",
757 + .parent_data = nss_cc_parent_data_2,
758 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
759 + .flags = CLK_SET_RATE_PARENT,
760 + .ops = &clk_rcg2_ops,
761 + },
762 +};
763 +
764 +static struct clk_rcg2 nss_cc_ubi3_clk_src = {
765 + .cmd_rcgr = 0x2871c,
766 + .mnd_width = 0,
767 + .hid_width = 5,
768 + .parent_map = nss_cc_parent_map_2,
769 + .freq_tbl = ftbl_nss_cc_ubi0_clk_src,
770 + .clkr.hw.init = &(const struct clk_init_data) {
771 + .name = "nss_cc_ubi3_clk_src",
772 + .parent_data = nss_cc_parent_data_2,
773 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
774 + .flags = CLK_SET_RATE_PARENT,
775 + .ops = &clk_rcg2_ops,
776 + },
777 +};
778 +
779 +static struct clk_rcg2 nss_cc_ubi_axi_clk_src = {
780 + .cmd_rcgr = 0x28724,
781 + .mnd_width = 0,
782 + .hid_width = 5,
783 + .parent_map = nss_cc_parent_map_7,
784 + .freq_tbl = ftbl_nss_cc_clc_clk_src,
785 + .clkr.hw.init = &(const struct clk_init_data) {
786 + .name = "nss_cc_ubi_axi_clk_src",
787 + .parent_data = nss_cc_parent_data_7,
788 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_7),
789 + .ops = &clk_rcg2_ops,
790 + },
791 +};
792 +
793 +static struct clk_rcg2 nss_cc_ubi_nc_axi_bfdcd_clk_src = {
794 + .cmd_rcgr = 0x2872c,
795 + .mnd_width = 0,
796 + .hid_width = 5,
797 + .parent_map = nss_cc_parent_map_1,
798 + .freq_tbl = ftbl_nss_cc_ce_clk_src,
799 + .clkr.hw.init = &(const struct clk_init_data) {
800 + .name = "nss_cc_ubi_nc_axi_bfdcd_clk_src",
801 + .parent_data = nss_cc_parent_data_1,
802 + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
803 + .flags = CLK_SET_RATE_PARENT,
804 + .ops = &clk_rcg2_ops,
805 + },
806 +};
807 +
808 +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
809 + .reg = 0x28118,
810 + .shift = 0,
811 + .width = 9,
812 + .clkr.hw.init = &(const struct clk_init_data) {
813 + .name = "nss_cc_port1_rx_div_clk_src",
814 + .parent_data = &(const struct clk_parent_data) {
815 + .hw = &nss_cc_port1_rx_clk_src.clkr.hw,
816 + },
817 + .num_parents = 1,
818 + .flags = CLK_SET_RATE_PARENT,
819 + .ops = &clk_regmap_div_ops,
820 + },
821 +};
822 +
823 +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
824 + .reg = 0x28124,
825 + .shift = 0,
826 + .width = 9,
827 + .clkr.hw.init = &(const struct clk_init_data) {
828 + .name = "nss_cc_port1_tx_div_clk_src",
829 + .parent_data = &(const struct clk_parent_data) {
830 + .hw = &nss_cc_port1_tx_clk_src.clkr.hw,
831 + },
832 + .num_parents = 1,
833 + .flags = CLK_SET_RATE_PARENT,
834 + .ops = &clk_regmap_div_ops,
835 + },
836 +};
837 +
838 +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
839 + .reg = 0x28130,
840 + .shift = 0,
841 + .width = 9,
842 + .clkr.hw.init = &(const struct clk_init_data) {
843 + .name = "nss_cc_port2_rx_div_clk_src",
844 + .parent_data = &(const struct clk_parent_data) {
845 + .hw = &nss_cc_port2_rx_clk_src.clkr.hw,
846 + },
847 + .num_parents = 1,
848 + .flags = CLK_SET_RATE_PARENT,
849 + .ops = &clk_regmap_div_ops,
850 + },
851 +};
852 +
853 +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
854 + .reg = 0x2813c,
855 + .shift = 0,
856 + .width = 9,
857 + .clkr.hw.init = &(const struct clk_init_data) {
858 + .name = "nss_cc_port2_tx_div_clk_src",
859 + .parent_data = &(const struct clk_parent_data) {
860 + .hw = &nss_cc_port2_tx_clk_src.clkr.hw,
861 + },
862 + .num_parents = 1,
863 + .flags = CLK_SET_RATE_PARENT,
864 + .ops = &clk_regmap_div_ops,
865 + },
866 +};
867 +
868 +static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
869 + .reg = 0x28148,
870 + .shift = 0,
871 + .width = 9,
872 + .clkr.hw.init = &(const struct clk_init_data) {
873 + .name = "nss_cc_port3_rx_div_clk_src",
874 + .parent_data = &(const struct clk_parent_data) {
875 + .hw = &nss_cc_port3_rx_clk_src.clkr.hw,
876 + },
877 + .num_parents = 1,
878 + .flags = CLK_SET_RATE_PARENT,
879 + .ops = &clk_regmap_div_ops,
880 + },
881 +};
882 +
883 +static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
884 + .reg = 0x28154,
885 + .shift = 0,
886 + .width = 9,
887 + .clkr.hw.init = &(const struct clk_init_data) {
888 + .name = "nss_cc_port3_tx_div_clk_src",
889 + .parent_data = &(const struct clk_parent_data) {
890 + .hw = &nss_cc_port3_tx_clk_src.clkr.hw,
891 + },
892 + .num_parents = 1,
893 + .flags = CLK_SET_RATE_PARENT,
894 + .ops = &clk_regmap_div_ops,
895 + },
896 +};
897 +
898 +static struct clk_regmap_div nss_cc_port4_rx_div_clk_src = {
899 + .reg = 0x28160,
900 + .shift = 0,
901 + .width = 9,
902 + .clkr.hw.init = &(const struct clk_init_data) {
903 + .name = "nss_cc_port4_rx_div_clk_src",
904 + .parent_data = &(const struct clk_parent_data) {
905 + .hw = &nss_cc_port4_rx_clk_src.clkr.hw,
906 + },
907 + .num_parents = 1,
908 + .flags = CLK_SET_RATE_PARENT,
909 + .ops = &clk_regmap_div_ops,
910 + },
911 +};
912 +
913 +static struct clk_regmap_div nss_cc_port4_tx_div_clk_src = {
914 + .reg = 0x2816c,
915 + .shift = 0,
916 + .width = 9,
917 + .clkr.hw.init = &(const struct clk_init_data) {
918 + .name = "nss_cc_port4_tx_div_clk_src",
919 + .parent_data = &(const struct clk_parent_data) {
920 + .hw = &nss_cc_port4_tx_clk_src.clkr.hw,
921 + },
922 + .num_parents = 1,
923 + .flags = CLK_SET_RATE_PARENT,
924 + .ops = &clk_regmap_div_ops,
925 + },
926 +};
927 +
928 +static struct clk_regmap_div nss_cc_port5_rx_div_clk_src = {
929 + .reg = 0x28178,
930 + .shift = 0,
931 + .width = 9,
932 + .clkr.hw.init = &(const struct clk_init_data) {
933 + .name = "nss_cc_port5_rx_div_clk_src",
934 + .parent_data = &(const struct clk_parent_data) {
935 + .hw = &nss_cc_port5_rx_clk_src.clkr.hw,
936 + },
937 + .num_parents = 1,
938 + .flags = CLK_SET_RATE_PARENT,
939 + .ops = &clk_regmap_div_ops,
940 + },
941 +};
942 +
943 +static struct clk_regmap_div nss_cc_port5_tx_div_clk_src = {
944 + .reg = 0x28184,
945 + .shift = 0,
946 + .width = 9,
947 + .clkr.hw.init = &(const struct clk_init_data) {
948 + .name = "nss_cc_port5_tx_div_clk_src",
949 + .parent_data = &(const struct clk_parent_data) {
950 + .hw = &nss_cc_port5_tx_clk_src.clkr.hw,
951 + },
952 + .num_parents = 1,
953 + .flags = CLK_SET_RATE_PARENT,
954 + .ops = &clk_regmap_div_ops,
955 + },
956 +};
957 +
958 +static struct clk_regmap_div nss_cc_port6_rx_div_clk_src = {
959 + .reg = 0x28190,
960 + .shift = 0,
961 + .width = 9,
962 + .clkr.hw.init = &(const struct clk_init_data) {
963 + .name = "nss_cc_port6_rx_div_clk_src",
964 + .parent_data = &(const struct clk_parent_data) {
965 + .hw = &nss_cc_port6_rx_clk_src.clkr.hw,
966 + },
967 + .num_parents = 1,
968 + .flags = CLK_SET_RATE_PARENT,
969 + .ops = &clk_regmap_div_ops,
970 + },
971 +};
972 +
973 +static struct clk_regmap_div nss_cc_port6_tx_div_clk_src = {
974 + .reg = 0x2819c,
975 + .shift = 0,
976 + .width = 9,
977 + .clkr.hw.init = &(const struct clk_init_data) {
978 + .name = "nss_cc_port6_tx_div_clk_src",
979 + .parent_data = &(const struct clk_parent_data) {
980 + .hw = &nss_cc_port6_tx_clk_src.clkr.hw,
981 + },
982 + .num_parents = 1,
983 + .flags = CLK_SET_RATE_PARENT,
984 + .ops = &clk_regmap_div_ops,
985 + },
986 +};
987 +
988 +static struct clk_regmap_div nss_cc_ubi0_div_clk_src = {
989 + .reg = 0x287a4,
990 + .shift = 0,
991 + .width = 4,
992 + .clkr.hw.init = &(const struct clk_init_data) {
993 + .name = "nss_cc_ubi0_div_clk_src",
994 + .parent_data = &(const struct clk_parent_data) {
995 + .hw = &nss_cc_ubi0_clk_src.clkr.hw,
996 + },
997 + .num_parents = 1,
998 + .flags = CLK_SET_RATE_PARENT,
999 + .ops = &clk_regmap_div_ro_ops,
1000 + },
1001 +};
1002 +
1003 +static struct clk_regmap_div nss_cc_ubi1_div_clk_src = {
1004 + .reg = 0x287a8,
1005 + .shift = 0,
1006 + .width = 4,
1007 + .clkr.hw.init = &(const struct clk_init_data) {
1008 + .name = "nss_cc_ubi1_div_clk_src",
1009 + .parent_data = &(const struct clk_parent_data) {
1010 + .hw = &nss_cc_ubi1_clk_src.clkr.hw,
1011 + },
1012 + .num_parents = 1,
1013 + .flags = CLK_SET_RATE_PARENT,
1014 + .ops = &clk_regmap_div_ro_ops,
1015 + },
1016 +};
1017 +
1018 +static struct clk_regmap_div nss_cc_ubi2_div_clk_src = {
1019 + .reg = 0x287ac,
1020 + .shift = 0,
1021 + .width = 4,
1022 + .clkr.hw.init = &(const struct clk_init_data) {
1023 + .name = "nss_cc_ubi2_div_clk_src",
1024 + .parent_data = &(const struct clk_parent_data) {
1025 + .hw = &nss_cc_ubi2_clk_src.clkr.hw,
1026 + },
1027 + .num_parents = 1,
1028 + .flags = CLK_SET_RATE_PARENT,
1029 + .ops = &clk_regmap_div_ro_ops,
1030 + },
1031 +};
1032 +
1033 +static struct clk_regmap_div nss_cc_ubi3_div_clk_src = {
1034 + .reg = 0x287b0,
1035 + .shift = 0,
1036 + .width = 4,
1037 + .clkr.hw.init = &(const struct clk_init_data) {
1038 + .name = "nss_cc_ubi3_div_clk_src",
1039 + .parent_data = &(const struct clk_parent_data) {
1040 + .hw = &nss_cc_ubi3_clk_src.clkr.hw,
1041 + },
1042 + .num_parents = 1,
1043 + .flags = CLK_SET_RATE_PARENT,
1044 + .ops = &clk_regmap_div_ro_ops,
1045 + },
1046 +};
1047 +
1048 +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
1049 + .reg = 0x28214,
1050 + .shift = 0,
1051 + .width = 4,
1052 + .clkr.hw.init = &(const struct clk_init_data) {
1053 + .name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
1054 + .parent_data = &(const struct clk_parent_data) {
1055 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1056 + },
1057 + .num_parents = 1,
1058 + .flags = CLK_SET_RATE_PARENT,
1059 + .ops = &clk_regmap_div_ro_ops,
1060 + },
1061 +};
1062 +
1063 +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
1064 + .reg = 0x28218,
1065 + .shift = 0,
1066 + .width = 4,
1067 + .clkr.hw.init = &(const struct clk_init_data) {
1068 + .name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
1069 + .parent_data = &(const struct clk_parent_data) {
1070 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1071 + },
1072 + .num_parents = 1,
1073 + .flags = CLK_SET_RATE_PARENT,
1074 + .ops = &clk_regmap_div_ro_ops,
1075 + },
1076 +};
1077 +
1078 +static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
1079 + .reg = 0x2821c,
1080 + .shift = 0,
1081 + .width = 4,
1082 + .clkr.hw.init = &(const struct clk_init_data) {
1083 + .name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
1084 + .parent_data = &(const struct clk_parent_data) {
1085 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1086 + },
1087 + .num_parents = 1,
1088 + .flags = CLK_SET_RATE_PARENT,
1089 + .ops = &clk_regmap_div_ro_ops,
1090 + },
1091 +};
1092 +
1093 +static struct clk_regmap_div nss_cc_xgmac3_ptp_ref_div_clk_src = {
1094 + .reg = 0x28220,
1095 + .shift = 0,
1096 + .width = 4,
1097 + .clkr.hw.init = &(const struct clk_init_data) {
1098 + .name = "nss_cc_xgmac3_ptp_ref_div_clk_src",
1099 + .parent_data = &(const struct clk_parent_data) {
1100 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1101 + },
1102 + .num_parents = 1,
1103 + .flags = CLK_SET_RATE_PARENT,
1104 + .ops = &clk_regmap_div_ro_ops,
1105 + },
1106 +};
1107 +
1108 +static struct clk_regmap_div nss_cc_xgmac4_ptp_ref_div_clk_src = {
1109 + .reg = 0x28224,
1110 + .shift = 0,
1111 + .width = 4,
1112 + .clkr.hw.init = &(const struct clk_init_data) {
1113 + .name = "nss_cc_xgmac4_ptp_ref_div_clk_src",
1114 + .parent_data = &(const struct clk_parent_data) {
1115 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1116 + },
1117 + .num_parents = 1,
1118 + .flags = CLK_SET_RATE_PARENT,
1119 + .ops = &clk_regmap_div_ro_ops,
1120 + },
1121 +};
1122 +
1123 +static struct clk_regmap_div nss_cc_xgmac5_ptp_ref_div_clk_src = {
1124 + .reg = 0x28228,
1125 + .shift = 0,
1126 + .width = 4,
1127 + .clkr.hw.init = &(const struct clk_init_data) {
1128 + .name = "nss_cc_xgmac5_ptp_ref_div_clk_src",
1129 + .parent_data = &(const struct clk_parent_data) {
1130 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1131 + },
1132 + .num_parents = 1,
1133 + .flags = CLK_SET_RATE_PARENT,
1134 + .ops = &clk_regmap_div_ro_ops,
1135 + },
1136 +};
1137 +
1138 +static struct clk_branch nss_cc_ce_apb_clk = {
1139 + .halt_reg = 0x2840c,
1140 + .clkr = {
1141 + .enable_reg = 0x2840c,
1142 + .enable_mask = BIT(0),
1143 + .hw.init = &(const struct clk_init_data) {
1144 + .name = "nss_cc_ce_apb_clk",
1145 + .parent_data = &(const struct clk_parent_data) {
1146 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1147 + },
1148 + .num_parents = 1,
1149 + .flags = CLK_SET_RATE_PARENT,
1150 + .ops = &clk_branch2_ops,
1151 + },
1152 + },
1153 +};
1154 +
1155 +static struct clk_branch nss_cc_ce_axi_clk = {
1156 + .halt_reg = 0x28410,
1157 + .halt_check = BRANCH_HALT,
1158 + .clkr = {
1159 + .enable_reg = 0x28410,
1160 + .enable_mask = BIT(0),
1161 + .hw.init = &(const struct clk_init_data) {
1162 + .name = "nss_cc_ce_axi_clk",
1163 + .parent_data = &(const struct clk_parent_data) {
1164 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1165 + },
1166 + .num_parents = 1,
1167 + .flags = CLK_SET_RATE_PARENT,
1168 + .ops = &clk_branch2_ops,
1169 + },
1170 + },
1171 +};
1172 +
1173 +static struct clk_branch nss_cc_clc_axi_clk = {
1174 + .halt_reg = 0x2860c,
1175 + .halt_check = BRANCH_HALT,
1176 + .clkr = {
1177 + .enable_reg = 0x2860c,
1178 + .enable_mask = BIT(0),
1179 + .hw.init = &(const struct clk_init_data) {
1180 + .name = "nss_cc_clc_axi_clk",
1181 + .parent_data = &(const struct clk_parent_data) {
1182 + .hw = &nss_cc_clc_clk_src.clkr.hw,
1183 + },
1184 + .num_parents = 1,
1185 + .flags = CLK_SET_RATE_PARENT,
1186 + .ops = &clk_branch2_ops,
1187 + },
1188 + },
1189 +};
1190 +
1191 +static struct clk_branch nss_cc_crypto_clk = {
1192 + .halt_reg = 0x1601c,
1193 + .halt_check = BRANCH_HALT,
1194 + .clkr = {
1195 + .enable_reg = 0x1601c,
1196 + .enable_mask = BIT(0),
1197 + .hw.init = &(const struct clk_init_data) {
1198 + .name = "nss_cc_crypto_clk",
1199 + .parent_data = &(const struct clk_parent_data) {
1200 + .hw = &nss_cc_crypto_clk_src.clkr.hw,
1201 + },
1202 + .num_parents = 1,
1203 + .flags = CLK_SET_RATE_PARENT,
1204 + .ops = &clk_branch2_ops,
1205 + },
1206 + },
1207 +};
1208 +
1209 +static struct clk_branch nss_cc_crypto_ppe_clk = {
1210 + .halt_reg = 0x28240,
1211 + .halt_check = BRANCH_HALT,
1212 + .clkr = {
1213 + .enable_reg = 0x28240,
1214 + .enable_mask = BIT(0),
1215 + .hw.init = &(const struct clk_init_data) {
1216 + .name = "nss_cc_crypto_ppe_clk",
1217 + .parent_data = &(const struct clk_parent_data) {
1218 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1219 + },
1220 + .num_parents = 1,
1221 + .flags = CLK_SET_RATE_PARENT,
1222 + .ops = &clk_branch2_ops,
1223 + },
1224 + },
1225 +};
1226 +
1227 +static struct clk_branch nss_cc_haq_ahb_clk = {
1228 + .halt_reg = 0x2830c,
1229 + .halt_check = BRANCH_HALT,
1230 + .clkr = {
1231 + .enable_reg = 0x2830c,
1232 + .enable_mask = BIT(0),
1233 + .hw.init = &(const struct clk_init_data) {
1234 + .name = "nss_cc_haq_ahb_clk",
1235 + .parent_data = &(const struct clk_parent_data) {
1236 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1237 + },
1238 + .num_parents = 1,
1239 + .flags = CLK_SET_RATE_PARENT,
1240 + .ops = &clk_branch2_ops,
1241 + },
1242 + },
1243 +};
1244 +
1245 +static struct clk_branch nss_cc_haq_axi_clk = {
1246 + .halt_reg = 0x28310,
1247 + .halt_check = BRANCH_HALT,
1248 + .clkr = {
1249 + .enable_reg = 0x28310,
1250 + .enable_mask = BIT(0),
1251 + .hw.init = &(const struct clk_init_data) {
1252 + .name = "nss_cc_haq_axi_clk",
1253 + .parent_data = &(const struct clk_parent_data) {
1254 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1255 + },
1256 + .num_parents = 1,
1257 + .flags = CLK_SET_RATE_PARENT,
1258 + .ops = &clk_branch2_ops,
1259 + },
1260 + },
1261 +};
1262 +
1263 +static struct clk_branch nss_cc_imem_ahb_clk = {
1264 + .halt_reg = 0xe018,
1265 + .halt_check = BRANCH_HALT,
1266 + .clkr = {
1267 + .enable_reg = 0xe018,
1268 + .enable_mask = BIT(0),
1269 + .hw.init = &(const struct clk_init_data) {
1270 + .name = "nss_cc_imem_ahb_clk",
1271 + .parent_data = &(const struct clk_parent_data) {
1272 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1273 + },
1274 + .num_parents = 1,
1275 + .flags = CLK_SET_RATE_PARENT,
1276 + .ops = &clk_branch2_ops,
1277 + },
1278 + },
1279 +};
1280 +
1281 +static struct clk_branch nss_cc_imem_qsb_clk = {
1282 + .halt_reg = 0xe010,
1283 + .halt_check = BRANCH_HALT,
1284 + .clkr = {
1285 + .enable_reg = 0xe010,
1286 + .enable_mask = BIT(0),
1287 + .hw.init = &(const struct clk_init_data) {
1288 + .name = "nss_cc_imem_qsb_clk",
1289 + .parent_data = &(const struct clk_parent_data) {
1290 + .hw = &nss_cc_imem_clk_src.clkr.hw,
1291 + },
1292 + .num_parents = 1,
1293 + .flags = CLK_SET_RATE_PARENT,
1294 + .ops = &clk_branch2_ops,
1295 + },
1296 + },
1297 +};
1298 +
1299 +static struct clk_branch nss_cc_nss_csr_clk = {
1300 + .halt_reg = 0x281d0,
1301 + .halt_check = BRANCH_HALT,
1302 + .clkr = {
1303 + .enable_reg = 0x281d0,
1304 + .enable_mask = BIT(0),
1305 + .hw.init = &(const struct clk_init_data) {
1306 + .name = "nss_cc_nss_csr_clk",
1307 + .parent_data = &(const struct clk_parent_data) {
1308 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1309 + },
1310 + .num_parents = 1,
1311 + .flags = CLK_SET_RATE_PARENT,
1312 + .ops = &clk_branch2_ops,
1313 + },
1314 + },
1315 +};
1316 +
1317 +static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
1318 + .halt_reg = 0x28414,
1319 + .halt_check = BRANCH_HALT,
1320 + .clkr = {
1321 + .enable_reg = 0x28414,
1322 + .enable_mask = BIT(0),
1323 + .hw.init = &(const struct clk_init_data) {
1324 + .name = "nss_cc_nssnoc_ce_apb_clk",
1325 + .parent_data = &(const struct clk_parent_data) {
1326 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1327 + },
1328 + .num_parents = 1,
1329 + .flags = CLK_SET_RATE_PARENT,
1330 + .ops = &clk_branch2_ops,
1331 + },
1332 + },
1333 +};
1334 +
1335 +static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
1336 + .halt_reg = 0x28418,
1337 + .halt_check = BRANCH_HALT,
1338 + .clkr = {
1339 + .enable_reg = 0x28418,
1340 + .enable_mask = BIT(0),
1341 + .hw.init = &(const struct clk_init_data) {
1342 + .name = "nss_cc_nssnoc_ce_axi_clk",
1343 + .parent_data = &(const struct clk_parent_data) {
1344 + .hw = &nss_cc_ce_clk_src.clkr.hw,
1345 + },
1346 + .num_parents = 1,
1347 + .flags = CLK_SET_RATE_PARENT,
1348 + .ops = &clk_branch2_ops,
1349 + },
1350 + },
1351 +};
1352 +
1353 +static struct clk_branch nss_cc_nssnoc_clc_axi_clk = {
1354 + .halt_reg = 0x28610,
1355 + .halt_check = BRANCH_HALT,
1356 + .clkr = {
1357 + .enable_reg = 0x28610,
1358 + .enable_mask = BIT(0),
1359 + .hw.init = &(const struct clk_init_data) {
1360 + .name = "nss_cc_nssnoc_clc_axi_clk",
1361 + .parent_data = &(const struct clk_parent_data) {
1362 + .hw = &nss_cc_clc_clk_src.clkr.hw,
1363 + },
1364 + .num_parents = 1,
1365 + .flags = CLK_SET_RATE_PARENT,
1366 + .ops = &clk_branch2_ops,
1367 + },
1368 + },
1369 +};
1370 +
1371 +static struct clk_branch nss_cc_nssnoc_crypto_clk = {
1372 + .halt_reg = 0x16020,
1373 + .halt_check = BRANCH_HALT,
1374 + .clkr = {
1375 + .enable_reg = 0x16020,
1376 + .enable_mask = BIT(0),
1377 + .hw.init = &(const struct clk_init_data) {
1378 + .name = "nss_cc_nssnoc_crypto_clk",
1379 + .parent_data = &(const struct clk_parent_data) {
1380 + .hw = &nss_cc_crypto_clk_src.clkr.hw,
1381 + },
1382 + .num_parents = 1,
1383 + .flags = CLK_SET_RATE_PARENT,
1384 + .ops = &clk_branch2_ops,
1385 + },
1386 + },
1387 +};
1388 +
1389 +static struct clk_branch nss_cc_nssnoc_haq_ahb_clk = {
1390 + .halt_reg = 0x28314,
1391 + .halt_check = BRANCH_HALT,
1392 + .clkr = {
1393 + .enable_reg = 0x28314,
1394 + .enable_mask = BIT(0),
1395 + .hw.init = &(const struct clk_init_data) {
1396 + .name = "nss_cc_nssnoc_haq_ahb_clk",
1397 + .parent_data = &(const struct clk_parent_data) {
1398 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1399 + },
1400 + .num_parents = 1,
1401 + .flags = CLK_SET_RATE_PARENT,
1402 + .ops = &clk_branch2_ops,
1403 + },
1404 + },
1405 +};
1406 +
1407 +static struct clk_branch nss_cc_nssnoc_haq_axi_clk = {
1408 + .halt_reg = 0x28318,
1409 + .halt_check = BRANCH_HALT,
1410 + .clkr = {
1411 + .enable_reg = 0x28318,
1412 + .enable_mask = BIT(0),
1413 + .hw.init = &(const struct clk_init_data) {
1414 + .name = "nss_cc_nssnoc_haq_axi_clk",
1415 + .parent_data = &(const struct clk_parent_data) {
1416 + .hw = &nss_cc_haq_clk_src.clkr.hw,
1417 + },
1418 + .num_parents = 1,
1419 + .flags = CLK_SET_RATE_PARENT,
1420 + .ops = &clk_branch2_ops,
1421 + },
1422 + },
1423 +};
1424 +
1425 +static struct clk_branch nss_cc_nssnoc_imem_ahb_clk = {
1426 + .halt_reg = 0xe01c,
1427 + .halt_check = BRANCH_HALT,
1428 + .clkr = {
1429 + .enable_reg = 0xe01c,
1430 + .enable_mask = BIT(0),
1431 + .hw.init = &(const struct clk_init_data) {
1432 + .name = "nss_cc_nssnoc_imem_ahb_clk",
1433 + .parent_data = &(const struct clk_parent_data) {
1434 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1435 + },
1436 + .num_parents = 1,
1437 + .flags = CLK_SET_RATE_PARENT,
1438 + .ops = &clk_branch2_ops,
1439 + },
1440 + },
1441 +};
1442 +
1443 +static struct clk_branch nss_cc_nssnoc_imem_qsb_clk = {
1444 + .halt_reg = 0xe014,
1445 + .halt_check = BRANCH_HALT,
1446 + .clkr = {
1447 + .enable_reg = 0xe014,
1448 + .enable_mask = BIT(0),
1449 + .hw.init = &(const struct clk_init_data) {
1450 + .name = "nss_cc_nssnoc_imem_qsb_clk",
1451 + .parent_data = &(const struct clk_parent_data) {
1452 + .hw = &nss_cc_imem_clk_src.clkr.hw,
1453 + },
1454 + .num_parents = 1,
1455 + .flags = CLK_SET_RATE_PARENT,
1456 + .ops = &clk_branch2_ops,
1457 + },
1458 + },
1459 +};
1460 +
1461 +static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
1462 + .halt_reg = 0x281d4,
1463 + .halt_check = BRANCH_HALT,
1464 + .clkr = {
1465 + .enable_reg = 0x281d4,
1466 + .enable_mask = BIT(0),
1467 + .hw.init = &(const struct clk_init_data) {
1468 + .name = "nss_cc_nssnoc_nss_csr_clk",
1469 + .parent_data = &(const struct clk_parent_data) {
1470 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1471 + },
1472 + .num_parents = 1,
1473 + .flags = CLK_SET_RATE_PARENT,
1474 + .ops = &clk_branch2_ops,
1475 + },
1476 + },
1477 +};
1478 +
1479 +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
1480 + .halt_reg = 0x28248,
1481 + .halt_check = BRANCH_HALT,
1482 + .clkr = {
1483 + .enable_reg = 0x28248,
1484 + .enable_mask = BIT(0),
1485 + .hw.init = &(const struct clk_init_data) {
1486 + .name = "nss_cc_nssnoc_ppe_cfg_clk",
1487 + .parent_data = &(const struct clk_parent_data) {
1488 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1489 + },
1490 + .num_parents = 1,
1491 + .flags = CLK_SET_RATE_PARENT,
1492 + .ops = &clk_branch2_ops,
1493 + },
1494 + },
1495 +};
1496 +
1497 +static struct clk_branch nss_cc_nssnoc_ppe_clk = {
1498 + .halt_reg = 0x28244,
1499 + .halt_check = BRANCH_HALT,
1500 + .clkr = {
1501 + .enable_reg = 0x28244,
1502 + .enable_mask = BIT(0),
1503 + .hw.init = &(const struct clk_init_data) {
1504 + .name = "nss_cc_nssnoc_ppe_clk",
1505 + .parent_data = &(const struct clk_parent_data) {
1506 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1507 + },
1508 + .num_parents = 1,
1509 + .flags = CLK_SET_RATE_PARENT,
1510 + .ops = &clk_branch2_ops,
1511 + },
1512 + },
1513 +};
1514 +
1515 +static struct clk_branch nss_cc_nssnoc_ubi32_ahb0_clk = {
1516 + .halt_reg = 0x28788,
1517 + .halt_check = BRANCH_HALT,
1518 + .clkr = {
1519 + .enable_reg = 0x28788,
1520 + .enable_mask = BIT(0),
1521 + .hw.init = &(const struct clk_init_data) {
1522 + .name = "nss_cc_nssnoc_ubi32_ahb0_clk",
1523 + .parent_data = &(const struct clk_parent_data) {
1524 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
1525 + },
1526 + .num_parents = 1,
1527 + .flags = CLK_SET_RATE_PARENT,
1528 + .ops = &clk_branch2_ops,
1529 + },
1530 + },
1531 +};
1532 +
1533 +static struct clk_branch nss_cc_nssnoc_ubi32_axi0_clk = {
1534 + .halt_reg = 0x287a0,
1535 + .halt_check = BRANCH_HALT,
1536 + .clkr = {
1537 + .enable_reg = 0x287a0,
1538 + .enable_mask = BIT(0),
1539 + .hw.init = &(const struct clk_init_data) {
1540 + .name = "nss_cc_nssnoc_ubi32_axi0_clk",
1541 + .parent_data = &(const struct clk_parent_data) {
1542 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
1543 + },
1544 + .num_parents = 1,
1545 + .flags = CLK_SET_RATE_PARENT,
1546 + .ops = &clk_branch2_ops,
1547 + },
1548 + },
1549 +};
1550 +
1551 +static struct clk_branch nss_cc_nssnoc_ubi32_int0_ahb_clk = {
1552 + .halt_reg = 0x2878c,
1553 + .halt_check = BRANCH_HALT,
1554 + .clkr = {
1555 + .enable_reg = 0x2878c,
1556 + .enable_mask = BIT(0),
1557 + .hw.init = &(const struct clk_init_data) {
1558 + .name = "nss_cc_nssnoc_ubi32_int0_ahb_clk",
1559 + .parent_data = &(const struct clk_parent_data) {
1560 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
1561 + },
1562 + .num_parents = 1,
1563 + .flags = CLK_SET_RATE_PARENT,
1564 + .ops = &clk_branch2_ops,
1565 + },
1566 + },
1567 +};
1568 +
1569 +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_1_clk = {
1570 + .halt_reg = 0x287bc,
1571 + .halt_check = BRANCH_HALT,
1572 + .clkr = {
1573 + .enable_reg = 0x287bc,
1574 + .enable_mask = BIT(0),
1575 + .hw.init = &(const struct clk_init_data) {
1576 + .name = "nss_cc_nssnoc_ubi32_nc_axi0_1_clk",
1577 + .parent_data = &(const struct clk_parent_data) {
1578 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1579 + },
1580 + .num_parents = 1,
1581 + .flags = CLK_SET_RATE_PARENT,
1582 + .ops = &clk_branch2_ops,
1583 + },
1584 + },
1585 +};
1586 +
1587 +static struct clk_branch nss_cc_nssnoc_ubi32_nc_axi0_clk = {
1588 + .halt_reg = 0x28764,
1589 + .halt_check = BRANCH_HALT,
1590 + .clkr = {
1591 + .enable_reg = 0x28764,
1592 + .enable_mask = BIT(0),
1593 + .hw.init = &(const struct clk_init_data) {
1594 + .name = "nss_cc_nssnoc_ubi32_nc_axi0_clk",
1595 + .parent_data = &(const struct clk_parent_data) {
1596 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
1597 + },
1598 + .num_parents = 1,
1599 + .flags = CLK_SET_RATE_PARENT,
1600 + .ops = &clk_branch2_ops,
1601 + },
1602 + },
1603 +};
1604 +
1605 +static struct clk_branch nss_cc_port1_mac_clk = {
1606 + .halt_reg = 0x2824c,
1607 + .halt_check = BRANCH_HALT,
1608 + .clkr = {
1609 + .enable_reg = 0x2824c,
1610 + .enable_mask = BIT(0),
1611 + .hw.init = &(const struct clk_init_data) {
1612 + .name = "nss_cc_port1_mac_clk",
1613 + .parent_data = &(const struct clk_parent_data) {
1614 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1615 + },
1616 + .num_parents = 1,
1617 + .flags = CLK_SET_RATE_PARENT,
1618 + .ops = &clk_branch2_ops,
1619 + },
1620 + },
1621 +};
1622 +
1623 +static struct clk_branch nss_cc_port1_rx_clk = {
1624 + .halt_reg = 0x281a0,
1625 + .halt_check = BRANCH_HALT,
1626 + .clkr = {
1627 + .enable_reg = 0x281a0,
1628 + .enable_mask = BIT(0),
1629 + .hw.init = &(const struct clk_init_data) {
1630 + .name = "nss_cc_port1_rx_clk",
1631 + .parent_data = &(const struct clk_parent_data) {
1632 + .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
1633 + },
1634 + .num_parents = 1,
1635 + .flags = CLK_SET_RATE_PARENT,
1636 + .ops = &clk_branch2_ops,
1637 + },
1638 + },
1639 +};
1640 +
1641 +static struct clk_branch nss_cc_port1_tx_clk = {
1642 + .halt_reg = 0x281a4,
1643 + .halt_check = BRANCH_HALT,
1644 + .clkr = {
1645 + .enable_reg = 0x281a4,
1646 + .enable_mask = BIT(0),
1647 + .hw.init = &(const struct clk_init_data) {
1648 + .name = "nss_cc_port1_tx_clk",
1649 + .parent_data = &(const struct clk_parent_data) {
1650 + .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
1651 + },
1652 + .num_parents = 1,
1653 + .flags = CLK_SET_RATE_PARENT,
1654 + .ops = &clk_branch2_ops,
1655 + },
1656 + },
1657 +};
1658 +
1659 +static struct clk_branch nss_cc_port2_mac_clk = {
1660 + .halt_reg = 0x28250,
1661 + .halt_check = BRANCH_HALT,
1662 + .clkr = {
1663 + .enable_reg = 0x28250,
1664 + .enable_mask = BIT(0),
1665 + .hw.init = &(const struct clk_init_data) {
1666 + .name = "nss_cc_port2_mac_clk",
1667 + .parent_data = &(const struct clk_parent_data) {
1668 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1669 + },
1670 + .num_parents = 1,
1671 + .flags = CLK_SET_RATE_PARENT,
1672 + .ops = &clk_branch2_ops,
1673 + },
1674 + },
1675 +};
1676 +
1677 +static struct clk_branch nss_cc_port2_rx_clk = {
1678 + .halt_reg = 0x281a8,
1679 + .halt_check = BRANCH_HALT,
1680 + .clkr = {
1681 + .enable_reg = 0x281a8,
1682 + .enable_mask = BIT(0),
1683 + .hw.init = &(const struct clk_init_data) {
1684 + .name = "nss_cc_port2_rx_clk",
1685 + .parent_data = &(const struct clk_parent_data) {
1686 + .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
1687 + },
1688 + .num_parents = 1,
1689 + .flags = CLK_SET_RATE_PARENT,
1690 + .ops = &clk_branch2_ops,
1691 + },
1692 + },
1693 +};
1694 +
1695 +static struct clk_branch nss_cc_port2_tx_clk = {
1696 + .halt_reg = 0x281ac,
1697 + .halt_check = BRANCH_HALT,
1698 + .clkr = {
1699 + .enable_reg = 0x281ac,
1700 + .enable_mask = BIT(0),
1701 + .hw.init = &(const struct clk_init_data) {
1702 + .name = "nss_cc_port2_tx_clk",
1703 + .parent_data = &(const struct clk_parent_data) {
1704 + .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
1705 + },
1706 + .num_parents = 1,
1707 + .flags = CLK_SET_RATE_PARENT,
1708 + .ops = &clk_branch2_ops,
1709 + },
1710 + },
1711 +};
1712 +
1713 +static struct clk_branch nss_cc_port3_mac_clk = {
1714 + .halt_reg = 0x28254,
1715 + .halt_check = BRANCH_HALT,
1716 + .clkr = {
1717 + .enable_reg = 0x28254,
1718 + .enable_mask = BIT(0),
1719 + .hw.init = &(const struct clk_init_data) {
1720 + .name = "nss_cc_port3_mac_clk",
1721 + .parent_data = &(const struct clk_parent_data) {
1722 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1723 + },
1724 + .num_parents = 1,
1725 + .flags = CLK_SET_RATE_PARENT,
1726 + .ops = &clk_branch2_ops,
1727 + },
1728 + },
1729 +};
1730 +
1731 +static struct clk_branch nss_cc_port3_rx_clk = {
1732 + .halt_reg = 0x281b0,
1733 + .halt_check = BRANCH_HALT,
1734 + .clkr = {
1735 + .enable_reg = 0x281b0,
1736 + .enable_mask = BIT(0),
1737 + .hw.init = &(const struct clk_init_data) {
1738 + .name = "nss_cc_port3_rx_clk",
1739 + .parent_data = &(const struct clk_parent_data) {
1740 + .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
1741 + },
1742 + .num_parents = 1,
1743 + .flags = CLK_SET_RATE_PARENT,
1744 + .ops = &clk_branch2_ops,
1745 + },
1746 + },
1747 +};
1748 +
1749 +static struct clk_branch nss_cc_port3_tx_clk = {
1750 + .halt_reg = 0x281b4,
1751 + .halt_check = BRANCH_HALT,
1752 + .clkr = {
1753 + .enable_reg = 0x281b4,
1754 + .enable_mask = BIT(0),
1755 + .hw.init = &(const struct clk_init_data) {
1756 + .name = "nss_cc_port3_tx_clk",
1757 + .parent_data = &(const struct clk_parent_data) {
1758 + .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
1759 + },
1760 + .num_parents = 1,
1761 + .flags = CLK_SET_RATE_PARENT,
1762 + .ops = &clk_branch2_ops,
1763 + },
1764 + },
1765 +};
1766 +
1767 +static struct clk_branch nss_cc_port4_mac_clk = {
1768 + .halt_reg = 0x28258,
1769 + .halt_check = BRANCH_HALT,
1770 + .clkr = {
1771 + .enable_reg = 0x28258,
1772 + .enable_mask = BIT(0),
1773 + .hw.init = &(const struct clk_init_data) {
1774 + .name = "nss_cc_port4_mac_clk",
1775 + .parent_data = &(const struct clk_parent_data) {
1776 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1777 + },
1778 + .num_parents = 1,
1779 + .flags = CLK_SET_RATE_PARENT,
1780 + .ops = &clk_branch2_ops,
1781 + },
1782 + },
1783 +};
1784 +
1785 +static struct clk_branch nss_cc_port4_rx_clk = {
1786 + .halt_reg = 0x281b8,
1787 + .halt_check = BRANCH_HALT,
1788 + .clkr = {
1789 + .enable_reg = 0x281b8,
1790 + .enable_mask = BIT(0),
1791 + .hw.init = &(const struct clk_init_data) {
1792 + .name = "nss_cc_port4_rx_clk",
1793 + .parent_data = &(const struct clk_parent_data) {
1794 + .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
1795 + },
1796 + .num_parents = 1,
1797 + .flags = CLK_SET_RATE_PARENT,
1798 + .ops = &clk_branch2_ops,
1799 + },
1800 + },
1801 +};
1802 +
1803 +static struct clk_branch nss_cc_port4_tx_clk = {
1804 + .halt_reg = 0x281bc,
1805 + .halt_check = BRANCH_HALT,
1806 + .clkr = {
1807 + .enable_reg = 0x281bc,
1808 + .enable_mask = BIT(0),
1809 + .hw.init = &(const struct clk_init_data) {
1810 + .name = "nss_cc_port4_tx_clk",
1811 + .parent_data = &(const struct clk_parent_data) {
1812 + .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
1813 + },
1814 + .num_parents = 1,
1815 + .flags = CLK_SET_RATE_PARENT,
1816 + .ops = &clk_branch2_ops,
1817 + },
1818 + },
1819 +};
1820 +
1821 +static struct clk_branch nss_cc_port5_mac_clk = {
1822 + .halt_reg = 0x2825c,
1823 + .halt_check = BRANCH_HALT,
1824 + .clkr = {
1825 + .enable_reg = 0x2825c,
1826 + .enable_mask = BIT(0),
1827 + .hw.init = &(const struct clk_init_data) {
1828 + .name = "nss_cc_port5_mac_clk",
1829 + .parent_data = &(const struct clk_parent_data) {
1830 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1831 + },
1832 + .num_parents = 1,
1833 + .flags = CLK_SET_RATE_PARENT,
1834 + .ops = &clk_branch2_ops,
1835 + },
1836 + },
1837 +};
1838 +
1839 +static struct clk_branch nss_cc_port5_rx_clk = {
1840 + .halt_reg = 0x281c0,
1841 + .halt_check = BRANCH_HALT,
1842 + .clkr = {
1843 + .enable_reg = 0x281c0,
1844 + .enable_mask = BIT(0),
1845 + .hw.init = &(const struct clk_init_data) {
1846 + .name = "nss_cc_port5_rx_clk",
1847 + .parent_data = &(const struct clk_parent_data) {
1848 + .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
1849 + },
1850 + .num_parents = 1,
1851 + .flags = CLK_SET_RATE_PARENT,
1852 + .ops = &clk_branch2_ops,
1853 + },
1854 + },
1855 +};
1856 +
1857 +static struct clk_branch nss_cc_port5_tx_clk = {
1858 + .halt_reg = 0x281c4,
1859 + .halt_check = BRANCH_HALT,
1860 + .clkr = {
1861 + .enable_reg = 0x281c4,
1862 + .enable_mask = BIT(0),
1863 + .hw.init = &(const struct clk_init_data) {
1864 + .name = "nss_cc_port5_tx_clk",
1865 + .parent_data = &(const struct clk_parent_data) {
1866 + .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
1867 + },
1868 + .num_parents = 1,
1869 + .flags = CLK_SET_RATE_PARENT,
1870 + .ops = &clk_branch2_ops,
1871 + },
1872 + },
1873 +};
1874 +
1875 +static struct clk_branch nss_cc_port6_mac_clk = {
1876 + .halt_reg = 0x28260,
1877 + .halt_check = BRANCH_HALT,
1878 + .clkr = {
1879 + .enable_reg = 0x28260,
1880 + .enable_mask = BIT(0),
1881 + .hw.init = &(const struct clk_init_data) {
1882 + .name = "nss_cc_port6_mac_clk",
1883 + .parent_data = &(const struct clk_parent_data) {
1884 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1885 + },
1886 + .num_parents = 1,
1887 + .flags = CLK_SET_RATE_PARENT,
1888 + .ops = &clk_branch2_ops,
1889 + },
1890 + },
1891 +};
1892 +
1893 +static struct clk_branch nss_cc_port6_rx_clk = {
1894 + .halt_reg = 0x281c8,
1895 + .halt_check = BRANCH_HALT,
1896 + .clkr = {
1897 + .enable_reg = 0x281c8,
1898 + .enable_mask = BIT(0),
1899 + .hw.init = &(const struct clk_init_data) {
1900 + .name = "nss_cc_port6_rx_clk",
1901 + .parent_data = &(const struct clk_parent_data) {
1902 + .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
1903 + },
1904 + .num_parents = 1,
1905 + .flags = CLK_SET_RATE_PARENT,
1906 + .ops = &clk_branch2_ops,
1907 + },
1908 + },
1909 +};
1910 +
1911 +static struct clk_branch nss_cc_port6_tx_clk = {
1912 + .halt_reg = 0x281cc,
1913 + .halt_check = BRANCH_HALT,
1914 + .clkr = {
1915 + .enable_reg = 0x281cc,
1916 + .enable_mask = BIT(0),
1917 + .hw.init = &(const struct clk_init_data) {
1918 + .name = "nss_cc_port6_tx_clk",
1919 + .parent_data = &(const struct clk_parent_data) {
1920 + .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
1921 + },
1922 + .num_parents = 1,
1923 + .flags = CLK_SET_RATE_PARENT,
1924 + .ops = &clk_branch2_ops,
1925 + },
1926 + },
1927 +};
1928 +
1929 +static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
1930 + .halt_reg = 0x2823c,
1931 + .halt_check = BRANCH_HALT,
1932 + .clkr = {
1933 + .enable_reg = 0x2823c,
1934 + .enable_mask = BIT(0),
1935 + .hw.init = &(const struct clk_init_data) {
1936 + .name = "nss_cc_ppe_edma_cfg_clk",
1937 + .parent_data = &(const struct clk_parent_data) {
1938 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1939 + },
1940 + .num_parents = 1,
1941 + .flags = CLK_SET_RATE_PARENT,
1942 + .ops = &clk_branch2_ops,
1943 + },
1944 + },
1945 +};
1946 +
1947 +static struct clk_branch nss_cc_ppe_edma_clk = {
1948 + .halt_reg = 0x28238,
1949 + .halt_check = BRANCH_HALT,
1950 + .clkr = {
1951 + .enable_reg = 0x28238,
1952 + .enable_mask = BIT(0),
1953 + .hw.init = &(const struct clk_init_data) {
1954 + .name = "nss_cc_ppe_edma_clk",
1955 + .parent_data = &(const struct clk_parent_data) {
1956 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1957 + },
1958 + .num_parents = 1,
1959 + .flags = CLK_SET_RATE_PARENT,
1960 + .ops = &clk_branch2_ops,
1961 + },
1962 + },
1963 +};
1964 +
1965 +static struct clk_branch nss_cc_ppe_switch_btq_clk = {
1966 + .halt_reg = 0x2827c,
1967 + .halt_check = BRANCH_HALT,
1968 + .clkr = {
1969 + .enable_reg = 0x2827c,
1970 + .enable_mask = BIT(0),
1971 + .hw.init = &(const struct clk_init_data) {
1972 + .name = "nss_cc_ppe_switch_btq_clk",
1973 + .parent_data = &(const struct clk_parent_data) {
1974 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1975 + },
1976 + .num_parents = 1,
1977 + .flags = CLK_SET_RATE_PARENT,
1978 + .ops = &clk_branch2_ops,
1979 + },
1980 + },
1981 +};
1982 +
1983 +static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
1984 + .halt_reg = 0x28234,
1985 + .halt_check = BRANCH_HALT,
1986 + .clkr = {
1987 + .enable_reg = 0x28234,
1988 + .enable_mask = BIT(0),
1989 + .hw.init = &(const struct clk_init_data) {
1990 + .name = "nss_cc_ppe_switch_cfg_clk",
1991 + .parent_data = &(const struct clk_parent_data) {
1992 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
1993 + },
1994 + .num_parents = 1,
1995 + .flags = CLK_SET_RATE_PARENT,
1996 + .ops = &clk_branch2_ops,
1997 + },
1998 + },
1999 +};
2000 +
2001 +static struct clk_branch nss_cc_ppe_switch_clk = {
2002 + .halt_reg = 0x28230,
2003 + .halt_check = BRANCH_HALT,
2004 + .clkr = {
2005 + .enable_reg = 0x28230,
2006 + .enable_mask = BIT(0),
2007 + .hw.init = &(const struct clk_init_data) {
2008 + .name = "nss_cc_ppe_switch_clk",
2009 + .parent_data = &(const struct clk_parent_data) {
2010 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
2011 + },
2012 + .num_parents = 1,
2013 + .flags = CLK_SET_RATE_PARENT,
2014 + .ops = &clk_branch2_ops,
2015 + },
2016 + },
2017 +};
2018 +
2019 +static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
2020 + .halt_reg = 0x2822c,
2021 + .halt_check = BRANCH_HALT,
2022 + .clkr = {
2023 + .enable_reg = 0x2822c,
2024 + .enable_mask = BIT(0),
2025 + .hw.init = &(const struct clk_init_data) {
2026 + .name = "nss_cc_ppe_switch_ipe_clk",
2027 + .parent_data = &(const struct clk_parent_data) {
2028 + .hw = &nss_cc_ppe_clk_src.clkr.hw,
2029 + },
2030 + .num_parents = 1,
2031 + .flags = CLK_SET_RATE_PARENT,
2032 + .ops = &clk_branch2_ops,
2033 + },
2034 + },
2035 +};
2036 +
2037 +static struct clk_branch nss_cc_ubi32_ahb0_clk = {
2038 + .halt_reg = 0x28768,
2039 + .halt_check = BRANCH_HALT,
2040 + .clkr = {
2041 + .enable_reg = 0x28768,
2042 + .enable_mask = BIT(0),
2043 + .hw.init = &(const struct clk_init_data) {
2044 + .name = "nss_cc_ubi32_ahb0_clk",
2045 + .parent_data = &(const struct clk_parent_data) {
2046 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2047 + },
2048 + .num_parents = 1,
2049 + .flags = CLK_SET_RATE_PARENT,
2050 + .ops = &clk_branch2_ops,
2051 + },
2052 + },
2053 +};
2054 +
2055 +static struct clk_branch nss_cc_ubi32_ahb1_clk = {
2056 + .halt_reg = 0x28770,
2057 + .halt_check = BRANCH_HALT,
2058 + .clkr = {
2059 + .enable_reg = 0x28770,
2060 + .enable_mask = BIT(0),
2061 + .hw.init = &(const struct clk_init_data) {
2062 + .name = "nss_cc_ubi32_ahb1_clk",
2063 + .parent_data = &(const struct clk_parent_data) {
2064 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2065 + },
2066 + .num_parents = 1,
2067 + .flags = CLK_SET_RATE_PARENT,
2068 + .ops = &clk_branch2_ops,
2069 + },
2070 + },
2071 +};
2072 +
2073 +static struct clk_branch nss_cc_ubi32_ahb2_clk = {
2074 + .halt_reg = 0x28778,
2075 + .halt_check = BRANCH_HALT,
2076 + .clkr = {
2077 + .enable_reg = 0x28778,
2078 + .enable_mask = BIT(0),
2079 + .hw.init = &(const struct clk_init_data) {
2080 + .name = "nss_cc_ubi32_ahb2_clk",
2081 + .parent_data = &(const struct clk_parent_data) {
2082 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2083 + },
2084 + .num_parents = 1,
2085 + .flags = CLK_SET_RATE_PARENT,
2086 + .ops = &clk_branch2_ops,
2087 + },
2088 + },
2089 +};
2090 +
2091 +static struct clk_branch nss_cc_ubi32_ahb3_clk = {
2092 + .halt_reg = 0x28780,
2093 + .halt_check = BRANCH_HALT,
2094 + .clkr = {
2095 + .enable_reg = 0x28780,
2096 + .enable_mask = BIT(0),
2097 + .hw.init = &(const struct clk_init_data) {
2098 + .name = "nss_cc_ubi32_ahb3_clk",
2099 + .parent_data = &(const struct clk_parent_data) {
2100 + .hw = &nss_cc_cfg_clk_src.clkr.hw,
2101 + },
2102 + .num_parents = 1,
2103 + .flags = CLK_SET_RATE_PARENT,
2104 + .ops = &clk_branch2_ops,
2105 + },
2106 + },
2107 +};
2108 +
2109 +static struct clk_branch nss_cc_ubi32_axi0_clk = {
2110 + .halt_reg = 0x28790,
2111 + .halt_check = BRANCH_HALT,
2112 + .clkr = {
2113 + .enable_reg = 0x28790,
2114 + .enable_mask = BIT(0),
2115 + .hw.init = &(const struct clk_init_data) {
2116 + .name = "nss_cc_ubi32_axi0_clk",
2117 + .parent_data = &(const struct clk_parent_data) {
2118 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2119 + },
2120 + .num_parents = 1,
2121 + .flags = CLK_SET_RATE_PARENT,
2122 + .ops = &clk_branch2_ops,
2123 + },
2124 + },
2125 +};
2126 +
2127 +static struct clk_branch nss_cc_ubi32_axi1_clk = {
2128 + .halt_reg = 0x28794,
2129 + .halt_check = BRANCH_HALT,
2130 + .clkr = {
2131 + .enable_reg = 0x28794,
2132 + .enable_mask = BIT(0),
2133 + .hw.init = &(const struct clk_init_data) {
2134 + .name = "nss_cc_ubi32_axi1_clk",
2135 + .parent_data = &(const struct clk_parent_data) {
2136 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2137 + },
2138 + .num_parents = 1,
2139 + .flags = CLK_SET_RATE_PARENT,
2140 + .ops = &clk_branch2_ops,
2141 + },
2142 + },
2143 +};
2144 +
2145 +static struct clk_branch nss_cc_ubi32_axi2_clk = {
2146 + .halt_reg = 0x28798,
2147 + .halt_check = BRANCH_HALT,
2148 + .clkr = {
2149 + .enable_reg = 0x28798,
2150 + .enable_mask = BIT(0),
2151 + .hw.init = &(const struct clk_init_data) {
2152 + .name = "nss_cc_ubi32_axi2_clk",
2153 + .parent_data = &(const struct clk_parent_data) {
2154 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2155 + },
2156 + .num_parents = 1,
2157 + .flags = CLK_SET_RATE_PARENT,
2158 + .ops = &clk_branch2_ops,
2159 + },
2160 + },
2161 +};
2162 +
2163 +static struct clk_branch nss_cc_ubi32_axi3_clk = {
2164 + .halt_reg = 0x2879c,
2165 + .halt_check = BRANCH_HALT,
2166 + .clkr = {
2167 + .enable_reg = 0x2879c,
2168 + .enable_mask = BIT(0),
2169 + .hw.init = &(const struct clk_init_data) {
2170 + .name = "nss_cc_ubi32_axi3_clk",
2171 + .parent_data = &(const struct clk_parent_data) {
2172 + .hw = &nss_cc_ubi_axi_clk_src.clkr.hw,
2173 + },
2174 + .num_parents = 1,
2175 + .flags = CLK_SET_RATE_PARENT,
2176 + .ops = &clk_branch2_ops,
2177 + },
2178 + },
2179 +};
2180 +
2181 +static struct clk_branch nss_cc_ubi32_core0_clk = {
2182 + .halt_reg = 0x28734,
2183 + .halt_check = BRANCH_HALT,
2184 + .clkr = {
2185 + .enable_reg = 0x28734,
2186 + .enable_mask = BIT(0),
2187 + .hw.init = &(const struct clk_init_data) {
2188 + .name = "nss_cc_ubi32_core0_clk",
2189 + .parent_data = &(const struct clk_parent_data) {
2190 + .hw = &nss_cc_ubi0_div_clk_src.clkr.hw,
2191 + },
2192 + .num_parents = 1,
2193 + .flags = CLK_SET_RATE_PARENT,
2194 + .ops = &clk_branch2_ops,
2195 + },
2196 + },
2197 +};
2198 +
2199 +static struct clk_branch nss_cc_ubi32_core1_clk = {
2200 + .halt_reg = 0x28738,
2201 + .halt_check = BRANCH_HALT,
2202 + .clkr = {
2203 + .enable_reg = 0x28738,
2204 + .enable_mask = BIT(0),
2205 + .hw.init = &(const struct clk_init_data) {
2206 + .name = "nss_cc_ubi32_core1_clk",
2207 + .parent_data = &(const struct clk_parent_data) {
2208 + .hw = &nss_cc_ubi1_div_clk_src.clkr.hw,
2209 + },
2210 + .num_parents = 1,
2211 + .flags = CLK_SET_RATE_PARENT,
2212 + .ops = &clk_branch2_ops,
2213 + },
2214 + },
2215 +};
2216 +
2217 +static struct clk_branch nss_cc_ubi32_core2_clk = {
2218 + .halt_reg = 0x2873c,
2219 + .halt_check = BRANCH_HALT,
2220 + .clkr = {
2221 + .enable_reg = 0x2873c,
2222 + .enable_mask = BIT(0),
2223 + .hw.init = &(const struct clk_init_data) {
2224 + .name = "nss_cc_ubi32_core2_clk",
2225 + .parent_data = &(const struct clk_parent_data) {
2226 + .hw = &nss_cc_ubi2_div_clk_src.clkr.hw,
2227 + },
2228 + .num_parents = 1,
2229 + .flags = CLK_SET_RATE_PARENT,
2230 + .ops = &clk_branch2_ops,
2231 + },
2232 + },
2233 +};
2234 +
2235 +static struct clk_branch nss_cc_ubi32_core3_clk = {
2236 + .halt_reg = 0x28740,
2237 + .halt_check = BRANCH_HALT,
2238 + .clkr = {
2239 + .enable_reg = 0x28740,
2240 + .enable_mask = BIT(0),
2241 + .hw.init = &(const struct clk_init_data) {
2242 + .name = "nss_cc_ubi32_core3_clk",
2243 + .parent_data = &(const struct clk_parent_data) {
2244 + .hw = &nss_cc_ubi3_div_clk_src.clkr.hw,
2245 + },
2246 + .num_parents = 1,
2247 + .flags = CLK_SET_RATE_PARENT,
2248 + .ops = &clk_branch2_ops,
2249 + },
2250 + },
2251 +};
2252 +
2253 +static struct clk_branch nss_cc_ubi32_intr0_ahb_clk = {
2254 + .halt_reg = 0x2876c,
2255 + .halt_check = BRANCH_HALT,
2256 + .clkr = {
2257 + .enable_reg = 0x2876c,
2258 + .enable_mask = BIT(0),
2259 + .hw.init = &(const struct clk_init_data) {
2260 + .name = "nss_cc_ubi32_intr0_ahb_clk",
2261 + .parent_data = &(const struct clk_parent_data) {
2262 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2263 + },
2264 + .num_parents = 1,
2265 + .flags = CLK_SET_RATE_PARENT,
2266 + .ops = &clk_branch2_ops,
2267 + },
2268 + },
2269 +};
2270 +
2271 +static struct clk_branch nss_cc_ubi32_intr1_ahb_clk = {
2272 + .halt_reg = 0x28774,
2273 + .halt_check = BRANCH_HALT,
2274 + .clkr = {
2275 + .enable_reg = 0x28774,
2276 + .enable_mask = BIT(0),
2277 + .hw.init = &(const struct clk_init_data) {
2278 + .name = "nss_cc_ubi32_intr1_ahb_clk",
2279 + .parent_data = &(const struct clk_parent_data) {
2280 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2281 + },
2282 + .num_parents = 1,
2283 + .flags = CLK_SET_RATE_PARENT,
2284 + .ops = &clk_branch2_ops,
2285 + },
2286 + },
2287 +};
2288 +
2289 +static struct clk_branch nss_cc_ubi32_intr2_ahb_clk = {
2290 + .halt_reg = 0x2877c,
2291 + .halt_check = BRANCH_HALT,
2292 + .clkr = {
2293 + .enable_reg = 0x2877c,
2294 + .enable_mask = BIT(0),
2295 + .hw.init = &(const struct clk_init_data) {
2296 + .name = "nss_cc_ubi32_intr2_ahb_clk",
2297 + .parent_data = &(const struct clk_parent_data) {
2298 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2299 + },
2300 + .num_parents = 1,
2301 + .flags = CLK_SET_RATE_PARENT,
2302 + .ops = &clk_branch2_ops,
2303 + },
2304 + },
2305 +};
2306 +
2307 +static struct clk_branch nss_cc_ubi32_intr3_ahb_clk = {
2308 + .halt_reg = 0x28784,
2309 + .halt_check = BRANCH_HALT,
2310 + .clkr = {
2311 + .enable_reg = 0x28784,
2312 + .enable_mask = BIT(0),
2313 + .hw.init = &(const struct clk_init_data) {
2314 + .name = "nss_cc_ubi32_intr3_ahb_clk",
2315 + .parent_data = &(const struct clk_parent_data) {
2316 + .hw = &nss_cc_int_cfg_clk_src.clkr.hw,
2317 + },
2318 + .num_parents = 1,
2319 + .flags = CLK_SET_RATE_PARENT,
2320 + .ops = &clk_branch2_ops,
2321 + },
2322 + },
2323 +};
2324 +
2325 +static struct clk_branch nss_cc_ubi32_nc_axi0_clk = {
2326 + .halt_reg = 0x28744,
2327 + .halt_check = BRANCH_HALT,
2328 + .clkr = {
2329 + .enable_reg = 0x28744,
2330 + .enable_mask = BIT(0),
2331 + .hw.init = &(const struct clk_init_data) {
2332 + .name = "nss_cc_ubi32_nc_axi0_clk",
2333 + .parent_data = &(const struct clk_parent_data) {
2334 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2335 + },
2336 + .num_parents = 1,
2337 + .flags = CLK_SET_RATE_PARENT,
2338 + .ops = &clk_branch2_ops,
2339 + },
2340 + },
2341 +};
2342 +
2343 +static struct clk_branch nss_cc_ubi32_nc_axi1_clk = {
2344 + .halt_reg = 0x2874c,
2345 + .halt_check = BRANCH_HALT,
2346 + .clkr = {
2347 + .enable_reg = 0x2874c,
2348 + .enable_mask = BIT(0),
2349 + .hw.init = &(const struct clk_init_data) {
2350 + .name = "nss_cc_ubi32_nc_axi1_clk",
2351 + .parent_data = &(const struct clk_parent_data) {
2352 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2353 + },
2354 + .num_parents = 1,
2355 + .flags = CLK_SET_RATE_PARENT,
2356 + .ops = &clk_branch2_ops,
2357 + },
2358 + },
2359 +};
2360 +
2361 +static struct clk_branch nss_cc_ubi32_nc_axi2_clk = {
2362 + .halt_reg = 0x28754,
2363 + .halt_check = BRANCH_HALT,
2364 + .clkr = {
2365 + .enable_reg = 0x28754,
2366 + .enable_mask = BIT(0),
2367 + .hw.init = &(const struct clk_init_data) {
2368 + .name = "nss_cc_ubi32_nc_axi2_clk",
2369 + .parent_data = &(const struct clk_parent_data) {
2370 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2371 + },
2372 + .num_parents = 1,
2373 + .flags = CLK_SET_RATE_PARENT,
2374 + .ops = &clk_branch2_ops,
2375 + },
2376 + },
2377 +};
2378 +
2379 +static struct clk_branch nss_cc_ubi32_nc_axi3_clk = {
2380 + .halt_reg = 0x2875c,
2381 + .halt_check = BRANCH_HALT,
2382 + .clkr = {
2383 + .enable_reg = 0x2875c,
2384 + .enable_mask = BIT(0),
2385 + .hw.init = &(const struct clk_init_data) {
2386 + .name = "nss_cc_ubi32_nc_axi3_clk",
2387 + .parent_data = &(const struct clk_parent_data) {
2388 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2389 + },
2390 + .num_parents = 1,
2391 + .flags = CLK_SET_RATE_PARENT,
2392 + .ops = &clk_branch2_ops,
2393 + },
2394 + },
2395 +};
2396 +
2397 +static struct clk_branch nss_cc_ubi32_utcm0_clk = {
2398 + .halt_reg = 0x28748,
2399 + .halt_check = BRANCH_HALT,
2400 + .clkr = {
2401 + .enable_reg = 0x28748,
2402 + .enable_mask = BIT(0),
2403 + .hw.init = &(const struct clk_init_data) {
2404 + .name = "nss_cc_ubi32_utcm0_clk",
2405 + .parent_data = &(const struct clk_parent_data) {
2406 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2407 + },
2408 + .num_parents = 1,
2409 + .flags = CLK_SET_RATE_PARENT,
2410 + .ops = &clk_branch2_ops,
2411 + },
2412 + },
2413 +};
2414 +
2415 +static struct clk_branch nss_cc_ubi32_utcm1_clk = {
2416 + .halt_reg = 0x28750,
2417 + .halt_check = BRANCH_HALT,
2418 + .clkr = {
2419 + .enable_reg = 0x28750,
2420 + .enable_mask = BIT(0),
2421 + .hw.init = &(const struct clk_init_data) {
2422 + .name = "nss_cc_ubi32_utcm1_clk",
2423 + .parent_data = &(const struct clk_parent_data) {
2424 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2425 + },
2426 + .num_parents = 1,
2427 + .flags = CLK_SET_RATE_PARENT,
2428 + .ops = &clk_branch2_ops,
2429 + },
2430 + },
2431 +};
2432 +
2433 +static struct clk_branch nss_cc_ubi32_utcm2_clk = {
2434 + .halt_reg = 0x28758,
2435 + .halt_check = BRANCH_HALT,
2436 + .clkr = {
2437 + .enable_reg = 0x28758,
2438 + .enable_mask = BIT(0),
2439 + .hw.init = &(const struct clk_init_data) {
2440 + .name = "nss_cc_ubi32_utcm2_clk",
2441 + .parent_data = &(const struct clk_parent_data) {
2442 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2443 + },
2444 + .num_parents = 1,
2445 + .flags = CLK_SET_RATE_PARENT,
2446 + .ops = &clk_branch2_ops,
2447 + },
2448 + },
2449 +};
2450 +
2451 +static struct clk_branch nss_cc_ubi32_utcm3_clk = {
2452 + .halt_reg = 0x28760,
2453 + .halt_check = BRANCH_HALT,
2454 + .clkr = {
2455 + .enable_reg = 0x28760,
2456 + .enable_mask = BIT(0),
2457 + .hw.init = &(const struct clk_init_data) {
2458 + .name = "nss_cc_ubi32_utcm3_clk",
2459 + .parent_data = &(const struct clk_parent_data) {
2460 + .hw = &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr.hw,
2461 + },
2462 + .num_parents = 1,
2463 + .flags = CLK_SET_RATE_PARENT,
2464 + .ops = &clk_branch2_ops,
2465 + },
2466 + },
2467 +};
2468 +
2469 +static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
2470 + .halt_reg = 0x28904,
2471 + .halt_check = BRANCH_HALT,
2472 + .clkr = {
2473 + .enable_reg = 0x28904,
2474 + .enable_mask = BIT(0),
2475 + .hw.init = &(const struct clk_init_data) {
2476 + .name = "nss_cc_uniphy_port1_rx_clk",
2477 + .parent_data = &(const struct clk_parent_data) {
2478 + .hw = &nss_cc_port1_rx_div_clk_src.clkr.hw,
2479 + },
2480 + .num_parents = 1,
2481 + .flags = CLK_SET_RATE_PARENT,
2482 + .ops = &clk_branch2_ops,
2483 + },
2484 + },
2485 +};
2486 +
2487 +static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
2488 + .halt_reg = 0x28908,
2489 + .halt_check = BRANCH_HALT,
2490 + .clkr = {
2491 + .enable_reg = 0x28908,
2492 + .enable_mask = BIT(0),
2493 + .hw.init = &(const struct clk_init_data) {
2494 + .name = "nss_cc_uniphy_port1_tx_clk",
2495 + .parent_data = &(const struct clk_parent_data) {
2496 + .hw = &nss_cc_port1_tx_div_clk_src.clkr.hw,
2497 + },
2498 + .num_parents = 1,
2499 + .flags = CLK_SET_RATE_PARENT,
2500 + .ops = &clk_branch2_ops,
2501 + },
2502 + },
2503 +};
2504 +
2505 +static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
2506 + .halt_reg = 0x2890c,
2507 + .halt_check = BRANCH_HALT,
2508 + .clkr = {
2509 + .enable_reg = 0x2890c,
2510 + .enable_mask = BIT(0),
2511 + .hw.init = &(const struct clk_init_data) {
2512 + .name = "nss_cc_uniphy_port2_rx_clk",
2513 + .parent_data = &(const struct clk_parent_data) {
2514 + .hw = &nss_cc_port2_rx_div_clk_src.clkr.hw,
2515 + },
2516 + .num_parents = 1,
2517 + .flags = CLK_SET_RATE_PARENT,
2518 + .ops = &clk_branch2_ops,
2519 + },
2520 + },
2521 +};
2522 +
2523 +static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
2524 + .halt_reg = 0x28910,
2525 + .halt_check = BRANCH_HALT,
2526 + .clkr = {
2527 + .enable_reg = 0x28910,
2528 + .enable_mask = BIT(0),
2529 + .hw.init = &(const struct clk_init_data) {
2530 + .name = "nss_cc_uniphy_port2_tx_clk",
2531 + .parent_data = &(const struct clk_parent_data) {
2532 + .hw = &nss_cc_port2_tx_div_clk_src.clkr.hw,
2533 + },
2534 + .num_parents = 1,
2535 + .flags = CLK_SET_RATE_PARENT,
2536 + .ops = &clk_branch2_ops,
2537 + },
2538 + },
2539 +};
2540 +
2541 +static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
2542 + .halt_reg = 0x28914,
2543 + .halt_check = BRANCH_HALT,
2544 + .clkr = {
2545 + .enable_reg = 0x28914,
2546 + .enable_mask = BIT(0),
2547 + .hw.init = &(const struct clk_init_data) {
2548 + .name = "nss_cc_uniphy_port3_rx_clk",
2549 + .parent_data = &(const struct clk_parent_data) {
2550 + .hw = &nss_cc_port3_rx_div_clk_src.clkr.hw,
2551 + },
2552 + .num_parents = 1,
2553 + .flags = CLK_SET_RATE_PARENT,
2554 + .ops = &clk_branch2_ops,
2555 + },
2556 + },
2557 +};
2558 +
2559 +static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
2560 + .halt_reg = 0x28918,
2561 + .halt_check = BRANCH_HALT,
2562 + .clkr = {
2563 + .enable_reg = 0x28918,
2564 + .enable_mask = BIT(0),
2565 + .hw.init = &(const struct clk_init_data) {
2566 + .name = "nss_cc_uniphy_port3_tx_clk",
2567 + .parent_data = &(const struct clk_parent_data) {
2568 + .hw = &nss_cc_port3_tx_div_clk_src.clkr.hw,
2569 + },
2570 + .num_parents = 1,
2571 + .flags = CLK_SET_RATE_PARENT,
2572 + .ops = &clk_branch2_ops,
2573 + },
2574 + },
2575 +};
2576 +
2577 +static struct clk_branch nss_cc_uniphy_port4_rx_clk = {
2578 + .halt_reg = 0x2891c,
2579 + .halt_check = BRANCH_HALT,
2580 + .clkr = {
2581 + .enable_reg = 0x2891c,
2582 + .enable_mask = BIT(0),
2583 + .hw.init = &(const struct clk_init_data) {
2584 + .name = "nss_cc_uniphy_port4_rx_clk",
2585 + .parent_data = &(const struct clk_parent_data) {
2586 + .hw = &nss_cc_port4_rx_div_clk_src.clkr.hw,
2587 + },
2588 + .num_parents = 1,
2589 + .flags = CLK_SET_RATE_PARENT,
2590 + .ops = &clk_branch2_ops,
2591 + },
2592 + },
2593 +};
2594 +
2595 +static struct clk_branch nss_cc_uniphy_port4_tx_clk = {
2596 + .halt_reg = 0x28920,
2597 + .halt_check = BRANCH_HALT,
2598 + .clkr = {
2599 + .enable_reg = 0x28920,
2600 + .enable_mask = BIT(0),
2601 + .hw.init = &(const struct clk_init_data) {
2602 + .name = "nss_cc_uniphy_port4_tx_clk",
2603 + .parent_data = &(const struct clk_parent_data) {
2604 + .hw = &nss_cc_port4_tx_div_clk_src.clkr.hw,
2605 + },
2606 + .num_parents = 1,
2607 + .flags = CLK_SET_RATE_PARENT,
2608 + .ops = &clk_branch2_ops,
2609 + },
2610 + },
2611 +};
2612 +
2613 +static struct clk_branch nss_cc_uniphy_port5_rx_clk = {
2614 + .halt_reg = 0x28924,
2615 + .halt_check = BRANCH_HALT,
2616 + .clkr = {
2617 + .enable_reg = 0x28924,
2618 + .enable_mask = BIT(0),
2619 + .hw.init = &(const struct clk_init_data) {
2620 + .name = "nss_cc_uniphy_port5_rx_clk",
2621 + .parent_data = &(const struct clk_parent_data) {
2622 + .hw = &nss_cc_port5_rx_div_clk_src.clkr.hw,
2623 + },
2624 + .num_parents = 1,
2625 + .flags = CLK_SET_RATE_PARENT,
2626 + .ops = &clk_branch2_ops,
2627 + },
2628 + },
2629 +};
2630 +
2631 +static struct clk_branch nss_cc_uniphy_port5_tx_clk = {
2632 + .halt_reg = 0x28928,
2633 + .halt_check = BRANCH_HALT,
2634 + .clkr = {
2635 + .enable_reg = 0x28928,
2636 + .enable_mask = BIT(0),
2637 + .hw.init = &(const struct clk_init_data) {
2638 + .name = "nss_cc_uniphy_port5_tx_clk",
2639 + .parent_data = &(const struct clk_parent_data) {
2640 + .hw = &nss_cc_port5_tx_div_clk_src.clkr.hw,
2641 + },
2642 + .num_parents = 1,
2643 + .flags = CLK_SET_RATE_PARENT,
2644 + .ops = &clk_branch2_ops,
2645 + },
2646 + },
2647 +};
2648 +
2649 +static struct clk_branch nss_cc_uniphy_port6_rx_clk = {
2650 + .halt_reg = 0x2892c,
2651 + .halt_check = BRANCH_HALT,
2652 + .clkr = {
2653 + .enable_reg = 0x2892c,
2654 + .enable_mask = BIT(0),
2655 + .hw.init = &(const struct clk_init_data) {
2656 + .name = "nss_cc_uniphy_port6_rx_clk",
2657 + .parent_data = &(const struct clk_parent_data) {
2658 + .hw = &nss_cc_port6_rx_div_clk_src.clkr.hw,
2659 + },
2660 + .num_parents = 1,
2661 + .flags = CLK_SET_RATE_PARENT,
2662 + .ops = &clk_branch2_ops,
2663 + },
2664 + },
2665 +};
2666 +
2667 +static struct clk_branch nss_cc_uniphy_port6_tx_clk = {
2668 + .halt_reg = 0x28930,
2669 + .halt_check = BRANCH_HALT,
2670 + .clkr = {
2671 + .enable_reg = 0x28930,
2672 + .enable_mask = BIT(0),
2673 + .hw.init = &(const struct clk_init_data) {
2674 + .name = "nss_cc_uniphy_port6_tx_clk",
2675 + .parent_data = &(const struct clk_parent_data) {
2676 + .hw = &nss_cc_port6_tx_div_clk_src.clkr.hw,
2677 + },
2678 + .num_parents = 1,
2679 + .flags = CLK_SET_RATE_PARENT,
2680 + .ops = &clk_branch2_ops,
2681 + },
2682 + },
2683 +};
2684 +
2685 +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
2686 + .halt_reg = 0x28264,
2687 + .halt_check = BRANCH_HALT,
2688 + .clkr = {
2689 + .enable_reg = 0x28264,
2690 + .enable_mask = BIT(0),
2691 + .hw.init = &(const struct clk_init_data) {
2692 + .name = "nss_cc_xgmac0_ptp_ref_clk",
2693 + .parent_data = &(const struct clk_parent_data) {
2694 + .hw = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
2695 + },
2696 + .num_parents = 1,
2697 + .flags = CLK_SET_RATE_PARENT,
2698 + .ops = &clk_branch2_ops,
2699 + },
2700 + },
2701 +};
2702 +
2703 +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
2704 + .halt_reg = 0x28268,
2705 + .halt_check = BRANCH_HALT,
2706 + .clkr = {
2707 + .enable_reg = 0x28268,
2708 + .enable_mask = BIT(0),
2709 + .hw.init = &(const struct clk_init_data) {
2710 + .name = "nss_cc_xgmac1_ptp_ref_clk",
2711 + .parent_data = &(const struct clk_parent_data) {
2712 + .hw = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
2713 + },
2714 + .num_parents = 1,
2715 + .flags = CLK_SET_RATE_PARENT,
2716 + .ops = &clk_branch2_ops,
2717 + },
2718 + },
2719 +};
2720 +
2721 +static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
2722 + .halt_reg = 0x2826c,
2723 + .halt_check = BRANCH_HALT,
2724 + .clkr = {
2725 + .enable_reg = 0x2826c,
2726 + .enable_mask = BIT(0),
2727 + .hw.init = &(const struct clk_init_data) {
2728 + .name = "nss_cc_xgmac2_ptp_ref_clk",
2729 + .parent_data = &(const struct clk_parent_data) {
2730 + .hw = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
2731 + },
2732 + .num_parents = 1,
2733 + .flags = CLK_SET_RATE_PARENT,
2734 + .ops = &clk_branch2_ops,
2735 + },
2736 + },
2737 +};
2738 +
2739 +static struct clk_branch nss_cc_xgmac3_ptp_ref_clk = {
2740 + .halt_reg = 0x28270,
2741 + .halt_check = BRANCH_HALT,
2742 + .clkr = {
2743 + .enable_reg = 0x28270,
2744 + .enable_mask = BIT(0),
2745 + .hw.init = &(const struct clk_init_data) {
2746 + .name = "nss_cc_xgmac3_ptp_ref_clk",
2747 + .parent_data = &(const struct clk_parent_data) {
2748 + .hw = &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr.hw,
2749 + },
2750 + .num_parents = 1,
2751 + .flags = CLK_SET_RATE_PARENT,
2752 + .ops = &clk_branch2_ops,
2753 + },
2754 + },
2755 +};
2756 +
2757 +static struct clk_branch nss_cc_xgmac4_ptp_ref_clk = {
2758 + .halt_reg = 0x28274,
2759 + .halt_check = BRANCH_HALT,
2760 + .clkr = {
2761 + .enable_reg = 0x28274,
2762 + .enable_mask = BIT(0),
2763 + .hw.init = &(const struct clk_init_data) {
2764 + .name = "nss_cc_xgmac4_ptp_ref_clk",
2765 + .parent_data = &(const struct clk_parent_data) {
2766 + .hw = &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr.hw,
2767 + },
2768 + .num_parents = 1,
2769 + .flags = CLK_SET_RATE_PARENT,
2770 + .ops = &clk_branch2_ops,
2771 + },
2772 + },
2773 +};
2774 +
2775 +static struct clk_branch nss_cc_xgmac5_ptp_ref_clk = {
2776 + .halt_reg = 0x28278,
2777 + .halt_check = BRANCH_HALT,
2778 + .clkr = {
2779 + .enable_reg = 0x28278,
2780 + .enable_mask = BIT(0),
2781 + .hw.init = &(const struct clk_init_data) {
2782 + .name = "nss_cc_xgmac5_ptp_ref_clk",
2783 + .parent_data = &(const struct clk_parent_data) {
2784 + .hw = &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr.hw,
2785 + },
2786 + .num_parents = 1,
2787 + .flags = CLK_SET_RATE_PARENT,
2788 + .ops = &clk_branch2_ops,
2789 + },
2790 + },
2791 +};
2792 +
2793 +static struct clk_regmap *nss_cc_ipq9574_clocks[] = {
2794 + [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
2795 + [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
2796 + [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
2797 + [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
2798 + [NSS_CC_CLC_AXI_CLK] = &nss_cc_clc_axi_clk.clkr,
2799 + [NSS_CC_CLC_CLK_SRC] = &nss_cc_clc_clk_src.clkr,
2800 + [NSS_CC_CRYPTO_CLK] = &nss_cc_crypto_clk.clkr,
2801 + [NSS_CC_CRYPTO_CLK_SRC] = &nss_cc_crypto_clk_src.clkr,
2802 + [NSS_CC_CRYPTO_PPE_CLK] = &nss_cc_crypto_ppe_clk.clkr,
2803 + [NSS_CC_HAQ_AHB_CLK] = &nss_cc_haq_ahb_clk.clkr,
2804 + [NSS_CC_HAQ_AXI_CLK] = &nss_cc_haq_axi_clk.clkr,
2805 + [NSS_CC_HAQ_CLK_SRC] = &nss_cc_haq_clk_src.clkr,
2806 + [NSS_CC_IMEM_AHB_CLK] = &nss_cc_imem_ahb_clk.clkr,
2807 + [NSS_CC_IMEM_CLK_SRC] = &nss_cc_imem_clk_src.clkr,
2808 + [NSS_CC_IMEM_QSB_CLK] = &nss_cc_imem_qsb_clk.clkr,
2809 + [NSS_CC_INT_CFG_CLK_SRC] = &nss_cc_int_cfg_clk_src.clkr,
2810 + [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
2811 + [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
2812 + [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
2813 + [NSS_CC_NSSNOC_CLC_AXI_CLK] = &nss_cc_nssnoc_clc_axi_clk.clkr,
2814 + [NSS_CC_NSSNOC_CRYPTO_CLK] = &nss_cc_nssnoc_crypto_clk.clkr,
2815 + [NSS_CC_NSSNOC_HAQ_AHB_CLK] = &nss_cc_nssnoc_haq_ahb_clk.clkr,
2816 + [NSS_CC_NSSNOC_HAQ_AXI_CLK] = &nss_cc_nssnoc_haq_axi_clk.clkr,
2817 + [NSS_CC_NSSNOC_IMEM_AHB_CLK] = &nss_cc_nssnoc_imem_ahb_clk.clkr,
2818 + [NSS_CC_NSSNOC_IMEM_QSB_CLK] = &nss_cc_nssnoc_imem_qsb_clk.clkr,
2819 + [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
2820 + [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
2821 + [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
2822 + [NSS_CC_NSSNOC_UBI32_AHB0_CLK] = &nss_cc_nssnoc_ubi32_ahb0_clk.clkr,
2823 + [NSS_CC_NSSNOC_UBI32_AXI0_CLK] = &nss_cc_nssnoc_ubi32_axi0_clk.clkr,
2824 + [NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK] =
2825 + &nss_cc_nssnoc_ubi32_int0_ahb_clk.clkr,
2826 + [NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK] =
2827 + &nss_cc_nssnoc_ubi32_nc_axi0_1_clk.clkr,
2828 + [NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK] =
2829 + &nss_cc_nssnoc_ubi32_nc_axi0_clk.clkr,
2830 + [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
2831 + [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
2832 + [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
2833 + [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
2834 + [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
2835 + [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
2836 + [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
2837 + [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
2838 + [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
2839 + [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
2840 + [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
2841 + [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
2842 + [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
2843 + [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
2844 + [NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
2845 + [NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
2846 + [NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
2847 + [NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
2848 + [NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
2849 + [NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
2850 + [NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
2851 + [NSS_CC_PORT4_MAC_CLK] = &nss_cc_port4_mac_clk.clkr,
2852 + [NSS_CC_PORT4_RX_CLK] = &nss_cc_port4_rx_clk.clkr,
2853 + [NSS_CC_PORT4_RX_CLK_SRC] = &nss_cc_port4_rx_clk_src.clkr,
2854 + [NSS_CC_PORT4_RX_DIV_CLK_SRC] = &nss_cc_port4_rx_div_clk_src.clkr,
2855 + [NSS_CC_PORT4_TX_CLK] = &nss_cc_port4_tx_clk.clkr,
2856 + [NSS_CC_PORT4_TX_CLK_SRC] = &nss_cc_port4_tx_clk_src.clkr,
2857 + [NSS_CC_PORT4_TX_DIV_CLK_SRC] = &nss_cc_port4_tx_div_clk_src.clkr,
2858 + [NSS_CC_PORT5_MAC_CLK] = &nss_cc_port5_mac_clk.clkr,
2859 + [NSS_CC_PORT5_RX_CLK] = &nss_cc_port5_rx_clk.clkr,
2860 + [NSS_CC_PORT5_RX_CLK_SRC] = &nss_cc_port5_rx_clk_src.clkr,
2861 + [NSS_CC_PORT5_RX_DIV_CLK_SRC] = &nss_cc_port5_rx_div_clk_src.clkr,
2862 + [NSS_CC_PORT5_TX_CLK] = &nss_cc_port5_tx_clk.clkr,
2863 + [NSS_CC_PORT5_TX_CLK_SRC] = &nss_cc_port5_tx_clk_src.clkr,
2864 + [NSS_CC_PORT5_TX_DIV_CLK_SRC] = &nss_cc_port5_tx_div_clk_src.clkr,
2865 + [NSS_CC_PORT6_MAC_CLK] = &nss_cc_port6_mac_clk.clkr,
2866 + [NSS_CC_PORT6_RX_CLK] = &nss_cc_port6_rx_clk.clkr,
2867 + [NSS_CC_PORT6_RX_CLK_SRC] = &nss_cc_port6_rx_clk_src.clkr,
2868 + [NSS_CC_PORT6_RX_DIV_CLK_SRC] = &nss_cc_port6_rx_div_clk_src.clkr,
2869 + [NSS_CC_PORT6_TX_CLK] = &nss_cc_port6_tx_clk.clkr,
2870 + [NSS_CC_PORT6_TX_CLK_SRC] = &nss_cc_port6_tx_clk_src.clkr,
2871 + [NSS_CC_PORT6_TX_DIV_CLK_SRC] = &nss_cc_port6_tx_div_clk_src.clkr,
2872 + [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
2873 + [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
2874 + [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
2875 + [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
2876 + [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
2877 + [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
2878 + [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
2879 + [NSS_CC_UBI0_CLK_SRC] = &nss_cc_ubi0_clk_src.clkr,
2880 + [NSS_CC_UBI0_DIV_CLK_SRC] = &nss_cc_ubi0_div_clk_src.clkr,
2881 + [NSS_CC_UBI1_CLK_SRC] = &nss_cc_ubi1_clk_src.clkr,
2882 + [NSS_CC_UBI1_DIV_CLK_SRC] = &nss_cc_ubi1_div_clk_src.clkr,
2883 + [NSS_CC_UBI2_CLK_SRC] = &nss_cc_ubi2_clk_src.clkr,
2884 + [NSS_CC_UBI2_DIV_CLK_SRC] = &nss_cc_ubi2_div_clk_src.clkr,
2885 + [NSS_CC_UBI32_AHB0_CLK] = &nss_cc_ubi32_ahb0_clk.clkr,
2886 + [NSS_CC_UBI32_AHB1_CLK] = &nss_cc_ubi32_ahb1_clk.clkr,
2887 + [NSS_CC_UBI32_AHB2_CLK] = &nss_cc_ubi32_ahb2_clk.clkr,
2888 + [NSS_CC_UBI32_AHB3_CLK] = &nss_cc_ubi32_ahb3_clk.clkr,
2889 + [NSS_CC_UBI32_AXI0_CLK] = &nss_cc_ubi32_axi0_clk.clkr,
2890 + [NSS_CC_UBI32_AXI1_CLK] = &nss_cc_ubi32_axi1_clk.clkr,
2891 + [NSS_CC_UBI32_AXI2_CLK] = &nss_cc_ubi32_axi2_clk.clkr,
2892 + [NSS_CC_UBI32_AXI3_CLK] = &nss_cc_ubi32_axi3_clk.clkr,
2893 + [NSS_CC_UBI32_CORE0_CLK] = &nss_cc_ubi32_core0_clk.clkr,
2894 + [NSS_CC_UBI32_CORE1_CLK] = &nss_cc_ubi32_core1_clk.clkr,
2895 + [NSS_CC_UBI32_CORE2_CLK] = &nss_cc_ubi32_core2_clk.clkr,
2896 + [NSS_CC_UBI32_CORE3_CLK] = &nss_cc_ubi32_core3_clk.clkr,
2897 + [NSS_CC_UBI32_INTR0_AHB_CLK] = &nss_cc_ubi32_intr0_ahb_clk.clkr,
2898 + [NSS_CC_UBI32_INTR1_AHB_CLK] = &nss_cc_ubi32_intr1_ahb_clk.clkr,
2899 + [NSS_CC_UBI32_INTR2_AHB_CLK] = &nss_cc_ubi32_intr2_ahb_clk.clkr,
2900 + [NSS_CC_UBI32_INTR3_AHB_CLK] = &nss_cc_ubi32_intr3_ahb_clk.clkr,
2901 + [NSS_CC_UBI32_NC_AXI0_CLK] = &nss_cc_ubi32_nc_axi0_clk.clkr,
2902 + [NSS_CC_UBI32_NC_AXI1_CLK] = &nss_cc_ubi32_nc_axi1_clk.clkr,
2903 + [NSS_CC_UBI32_NC_AXI2_CLK] = &nss_cc_ubi32_nc_axi2_clk.clkr,
2904 + [NSS_CC_UBI32_NC_AXI3_CLK] = &nss_cc_ubi32_nc_axi3_clk.clkr,
2905 + [NSS_CC_UBI32_UTCM0_CLK] = &nss_cc_ubi32_utcm0_clk.clkr,
2906 + [NSS_CC_UBI32_UTCM1_CLK] = &nss_cc_ubi32_utcm1_clk.clkr,
2907 + [NSS_CC_UBI32_UTCM2_CLK] = &nss_cc_ubi32_utcm2_clk.clkr,
2908 + [NSS_CC_UBI32_UTCM3_CLK] = &nss_cc_ubi32_utcm3_clk.clkr,
2909 + [NSS_CC_UBI3_CLK_SRC] = &nss_cc_ubi3_clk_src.clkr,
2910 + [NSS_CC_UBI3_DIV_CLK_SRC] = &nss_cc_ubi3_div_clk_src.clkr,
2911 + [NSS_CC_UBI_AXI_CLK_SRC] = &nss_cc_ubi_axi_clk_src.clkr,
2912 + [NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC] =
2913 + &nss_cc_ubi_nc_axi_bfdcd_clk_src.clkr,
2914 + [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
2915 + [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
2916 + [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
2917 + [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
2918 + [NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
2919 + [NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
2920 + [NSS_CC_UNIPHY_PORT4_RX_CLK] = &nss_cc_uniphy_port4_rx_clk.clkr,
2921 + [NSS_CC_UNIPHY_PORT4_TX_CLK] = &nss_cc_uniphy_port4_tx_clk.clkr,
2922 + [NSS_CC_UNIPHY_PORT5_RX_CLK] = &nss_cc_uniphy_port5_rx_clk.clkr,
2923 + [NSS_CC_UNIPHY_PORT5_TX_CLK] = &nss_cc_uniphy_port5_tx_clk.clkr,
2924 + [NSS_CC_UNIPHY_PORT6_RX_CLK] = &nss_cc_uniphy_port6_rx_clk.clkr,
2925 + [NSS_CC_UNIPHY_PORT6_TX_CLK] = &nss_cc_uniphy_port6_tx_clk.clkr,
2926 + [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
2927 + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] =
2928 + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
2929 + [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
2930 + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] =
2931 + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
2932 + [NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
2933 + [NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] =
2934 + &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
2935 + [NSS_CC_XGMAC3_PTP_REF_CLK] = &nss_cc_xgmac3_ptp_ref_clk.clkr,
2936 + [NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC] =
2937 + &nss_cc_xgmac3_ptp_ref_div_clk_src.clkr,
2938 + [NSS_CC_XGMAC4_PTP_REF_CLK] = &nss_cc_xgmac4_ptp_ref_clk.clkr,
2939 + [NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC] =
2940 + &nss_cc_xgmac4_ptp_ref_div_clk_src.clkr,
2941 + [NSS_CC_XGMAC5_PTP_REF_CLK] = &nss_cc_xgmac5_ptp_ref_clk.clkr,
2942 + [NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC] =
2943 + &nss_cc_xgmac5_ptp_ref_div_clk_src.clkr,
2944 + [UBI32_PLL] = &ubi32_pll.clkr,
2945 + [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
2946 +};
2947 +
2948 +static const struct qcom_reset_map nss_cc_ipq9574_resets[] = {
2949 + [NSS_CC_CE_BCR] = { 0x28400, 0 },
2950 + [NSS_CC_CLC_BCR] = { 0x28600, 0 },
2951 + [NSS_CC_EIP197_BCR] = { 0x16004, 0 },
2952 + [NSS_CC_HAQ_BCR] = { 0x28300, 0 },
2953 + [NSS_CC_IMEM_BCR] = { 0xe004, 0 },
2954 + [NSS_CC_MAC_BCR] = { 0x28100, 0 },
2955 + [NSS_CC_PPE_BCR] = { 0x28200, 0 },
2956 + [NSS_CC_UBI_BCR] = { 0x28700, 0 },
2957 + [NSS_CC_UNIPHY_BCR] = { 0x28900, 0 },
2958 + [UBI3_CLKRST_CLAMP_ENABLE] = { 0x28a04, 9 },
2959 + [UBI3_CORE_CLAMP_ENABLE] = { 0x28a04, 8 },
2960 + [UBI2_CLKRST_CLAMP_ENABLE] = { 0x28a04, 7 },
2961 + [UBI2_CORE_CLAMP_ENABLE] = { 0x28a04, 6 },
2962 + [UBI1_CLKRST_CLAMP_ENABLE] = { 0x28a04, 5 },
2963 + [UBI1_CORE_CLAMP_ENABLE] = { 0x28a04, 4 },
2964 + [UBI0_CLKRST_CLAMP_ENABLE] = { 0x28a04, 3 },
2965 + [UBI0_CORE_CLAMP_ENABLE] = { 0x28a04, 2 },
2966 + [NSSNOC_NSS_CSR_ARES] = { 0x28a04, 1 },
2967 + [NSS_CSR_ARES] = { 0x28a04, 0 },
2968 + [PPE_BTQ_ARES] = { 0x28a08, 20 },
2969 + [PPE_IPE_ARES] = { 0x28a08, 19 },
2970 + [PPE_ARES] = { 0x28a08, 18 },
2971 + [PPE_CFG_ARES] = { 0x28a08, 17 },
2972 + [PPE_EDMA_ARES] = { 0x28a08, 16 },
2973 + [PPE_EDMA_CFG_ARES] = { 0x28a08, 15 },
2974 + [CRY_PPE_ARES] = { 0x28a08, 14 },
2975 + [NSSNOC_PPE_ARES] = { 0x28a08, 13 },
2976 + [NSSNOC_PPE_CFG_ARES] = { 0x28a08, 12 },
2977 + [PORT1_MAC_ARES] = { 0x28a08, 11 },
2978 + [PORT2_MAC_ARES] = { 0x28a08, 10 },
2979 + [PORT3_MAC_ARES] = { 0x28a08, 9 },
2980 + [PORT4_MAC_ARES] = { 0x28a08, 8 },
2981 + [PORT5_MAC_ARES] = { 0x28a08, 7 },
2982 + [PORT6_MAC_ARES] = { 0x28a08, 6 },
2983 + [XGMAC0_PTP_REF_ARES] = { 0x28a08, 5 },
2984 + [XGMAC1_PTP_REF_ARES] = { 0x28a08, 4 },
2985 + [XGMAC2_PTP_REF_ARES] = { 0x28a08, 3 },
2986 + [XGMAC3_PTP_REF_ARES] = { 0x28a08, 2 },
2987 + [XGMAC4_PTP_REF_ARES] = { 0x28a08, 1 },
2988 + [XGMAC5_PTP_REF_ARES] = { 0x28a08, 0 },
2989 + [HAQ_AHB_ARES] = { 0x28a0c, 3 },
2990 + [HAQ_AXI_ARES] = { 0x28a0c, 2 },
2991 + [NSSNOC_HAQ_AHB_ARES] = { 0x28a0c, 1 },
2992 + [NSSNOC_HAQ_AXI_ARES] = { 0x28a0c, 0 },
2993 + [CE_APB_ARES] = { 0x28a10, 3 },
2994 + [CE_AXI_ARES] = { 0x28a10, 2 },
2995 + [NSSNOC_CE_APB_ARES] = { 0x28a10, 1 },
2996 + [NSSNOC_CE_AXI_ARES] = { 0x28a10, 0 },
2997 + [CRYPTO_ARES] = { 0x28a14, 1 },
2998 + [NSSNOC_CRYPTO_ARES] = { 0x28a14, 0 },
2999 + [NSSNOC_NC_AXI0_1_ARES] = { 0x28a1c, 28 },
3000 + [UBI0_CORE_ARES] = { 0x28a1c, 27 },
3001 + [UBI1_CORE_ARES] = { 0x28a1c, 26 },
3002 + [UBI2_CORE_ARES] = { 0x28a1c, 25 },
3003 + [UBI3_CORE_ARES] = { 0x28a1c, 24 },
3004 + [NC_AXI0_ARES] = { 0x28a1c, 23 },
3005 + [UTCM0_ARES] = { 0x28a1c, 22 },
3006 + [NC_AXI1_ARES] = { 0x28a1c, 21 },
3007 + [UTCM1_ARES] = { 0x28a1c, 20 },
3008 + [NC_AXI2_ARES] = { 0x28a1c, 19 },
3009 + [UTCM2_ARES] = { 0x28a1c, 18 },
3010 + [NC_AXI3_ARES] = { 0x28a1c, 17 },
3011 + [UTCM3_ARES] = { 0x28a1c, 16 },
3012 + [NSSNOC_NC_AXI0_ARES] = { 0x28a1c, 15 },
3013 + [AHB0_ARES] = { 0x28a1c, 14 },
3014 + [INTR0_AHB_ARES] = { 0x28a1c, 13 },
3015 + [AHB1_ARES] = { 0x28a1c, 12 },
3016 + [INTR1_AHB_ARES] = { 0x28a1c, 11 },
3017 + [AHB2_ARES] = { 0x28a1c, 10 },
3018 + [INTR2_AHB_ARES] = { 0x28a1c, 9 },
3019 + [AHB3_ARES] = { 0x28a1c, 8 },
3020 + [INTR3_AHB_ARES] = { 0x28a1c, 7 },
3021 + [NSSNOC_AHB0_ARES] = { 0x28a1c, 6 },
3022 + [NSSNOC_INT0_AHB_ARES] = { 0x28a1c, 5 },
3023 + [AXI0_ARES] = { 0x28a1c, 4 },
3024 + [AXI1_ARES] = { 0x28a1c, 3 },
3025 + [AXI2_ARES] = { 0x28a1c, 2 },
3026 + [AXI3_ARES] = { 0x28a1c, 1 },
3027 + [NSSNOC_AXI0_ARES] = { 0x28a1c, 0 },
3028 + [IMEM_QSB_ARES] = { 0x28a20, 3 },
3029 + [NSSNOC_IMEM_QSB_ARES] = { 0x28a20, 2 },
3030 + [IMEM_AHB_ARES] = { 0x28a20, 1 },
3031 + [NSSNOC_IMEM_AHB_ARES] = { 0x28a20, 0 },
3032 + [UNIPHY_PORT1_RX_ARES] = { 0x28a24, 23 },
3033 + [UNIPHY_PORT1_TX_ARES] = { 0x28a24, 22 },
3034 + [UNIPHY_PORT2_RX_ARES] = { 0x28a24, 21 },
3035 + [UNIPHY_PORT2_TX_ARES] = { 0x28a24, 20 },
3036 + [UNIPHY_PORT3_RX_ARES] = { 0x28a24, 19 },
3037 + [UNIPHY_PORT3_TX_ARES] = { 0x28a24, 18 },
3038 + [UNIPHY_PORT4_RX_ARES] = { 0x28a24, 17 },
3039 + [UNIPHY_PORT4_TX_ARES] = { 0x28a24, 16 },
3040 + [UNIPHY_PORT5_RX_ARES] = { 0x28a24, 15 },
3041 + [UNIPHY_PORT5_TX_ARES] = { 0x28a24, 14 },
3042 + [UNIPHY_PORT6_RX_ARES] = { 0x28a24, 13 },
3043 + [UNIPHY_PORT6_TX_ARES] = { 0x28a24, 12 },
3044 + [PORT1_RX_ARES] = { 0x28a24, 11 },
3045 + [PORT1_TX_ARES] = { 0x28a24, 10 },
3046 + [PORT2_RX_ARES] = { 0x28a24, 9 },
3047 + [PORT2_TX_ARES] = { 0x28a24, 8 },
3048 + [PORT3_RX_ARES] = { 0x28a24, 7 },
3049 + [PORT3_TX_ARES] = { 0x28a24, 6 },
3050 + [PORT4_RX_ARES] = { 0x28a24, 5 },
3051 + [PORT4_TX_ARES] = { 0x28a24, 4 },
3052 + [PORT5_RX_ARES] = { 0x28a24, 3 },
3053 + [PORT5_TX_ARES] = { 0x28a24, 2 },
3054 + [PORT6_RX_ARES] = { 0x28a24, 1 },
3055 + [PORT6_TX_ARES] = { 0x28a24, 0 },
3056 + [PPE_FULL_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(20, 17) },
3057 + [UNIPHY0_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(23, 14) },
3058 + [UNIPHY1_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3059 + [UNIPHY2_SOFT_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3060 + [UNIPHY_PORT1_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(23, 22) },
3061 + [UNIPHY_PORT2_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(21, 20) },
3062 + [UNIPHY_PORT3_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(19, 18) },
3063 + [UNIPHY_PORT4_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(17, 16) },
3064 + [UNIPHY_PORT5_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(15, 14) },
3065 + [UNIPHY_PORT6_ARES] = { .reg = 0x28a24, .bitmask = GENMASK(13, 12) },
3066 + [NSSPORT1_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(11, 10) },
3067 + [NSSPORT2_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(9, 8) },
3068 + [NSSPORT3_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(7, 6) },
3069 + [NSSPORT4_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(5, 4) },
3070 + [NSSPORT5_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(3, 2) },
3071 + [NSSPORT6_RESET] = { .reg = 0x28a24, .bitmask = GENMASK(1, 0) },
3072 + [EDMA_HW_RESET] = { .reg = 0x28a08, .bitmask = GENMASK(16, 15) },
3073 +};
3074 +
3075 +static const struct regmap_config nss_cc_ipq9574_regmap_config = {
3076 + .reg_bits = 32,
3077 + .reg_stride = 4,
3078 + .val_bits = 32,
3079 + .max_register = 0x28a34,
3080 + .fast_io = true,
3081 +};
3082 +
3083 +static struct qcom_icc_hws_data icc_ipq9574_nss_hws[] = {
3084 + { MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK },
3085 + { MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK },
3086 + { MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK },
3087 + { MASTER_NSSNOC_IMEM_QSB, SLAVE_NSSNOC_IMEM_QSB, NSS_CC_NSSNOC_IMEM_QSB_CLK },
3088 + { MASTER_NSSNOC_IMEM_AHB, SLAVE_NSSNOC_IMEM_AHB, NSS_CC_NSSNOC_IMEM_AHB_CLK },
3089 +};
3090 +
3091 +#define IPQ_NSSCC_ID (9574 * 2) /* some unique value */
3092 +
3093 +static const struct qcom_cc_desc nss_cc_ipq9574_desc = {
3094 + .config = &nss_cc_ipq9574_regmap_config,
3095 + .clks = nss_cc_ipq9574_clocks,
3096 + .num_clks = ARRAY_SIZE(nss_cc_ipq9574_clocks),
3097 + .resets = nss_cc_ipq9574_resets,
3098 + .num_resets = ARRAY_SIZE(nss_cc_ipq9574_resets),
3099 + .icc_hws = icc_ipq9574_nss_hws,
3100 + .num_icc_hws = ARRAY_SIZE(icc_ipq9574_nss_hws),
3101 + .icc_first_node_id = IPQ_NSSCC_ID,
3102 +};
3103 +
3104 +static const struct of_device_id nss_cc_ipq9574_match_table[] = {
3105 + { .compatible = "qcom,ipq9574-nsscc" },
3106 + { }
3107 +};
3108 +MODULE_DEVICE_TABLE(of, nss_cc_ipq9574_match_table);
3109 +
3110 +static int nss_cc_ipq9574_probe(struct platform_device *pdev)
3111 +{
3112 + struct regmap *regmap;
3113 +
3114 + regmap = qcom_cc_map(pdev, &nss_cc_ipq9574_desc);
3115 + if (IS_ERR(regmap))
3116 + return PTR_ERR(regmap);
3117 +
3118 + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
3119 +
3120 + return qcom_cc_really_probe(&pdev->dev, &nss_cc_ipq9574_desc, regmap);
3121 +}
3122 +
3123 +static struct platform_driver nss_cc_ipq9574_driver = {
3124 + .probe = nss_cc_ipq9574_probe,
3125 + .driver = {
3126 + .name = "qcom,nsscc-ipq9574",
3127 + .of_match_table = nss_cc_ipq9574_match_table,
3128 + .sync_state = icc_sync_state, /* TODO seems to cause hang */
3129 + },
3130 +};
3131 +
3132 +module_platform_driver(nss_cc_ipq9574_driver);
3133 +
3134 +MODULE_DESCRIPTION("QTI NSS_CC IPQ9574 Driver");
3135 +MODULE_LICENSE("GPL");
3136 --
3137 2.45.2
3138
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