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1 From 4d9470c29736bf81bdb0d21da24cf350b1e99402 Mon Sep 17 00:00:00 2001
2 From: Jim Quinlan <james.quinlan@broadcom.com>
3 Date: Mon, 16 Dec 2019 12:01:09 +0100
4 Subject: [PATCH] PCI: brcmstb: Add Broadcom STB PCIe host controller
5 driver
6
7 commit c0452137034bda8f686dd9a2e167949bfffd6776 upstream.
8
9 This adds a basic driver for Broadcom's STB PCIe controller, for now
10 aimed at Raspberry Pi 4's SoC, bcm2711.
11
12 Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
13 Co-developed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
14 Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
15 [lorenzo.pieralisi@arm.com: updated brcm_pcie_get_rc_bar2_size_and_offset()according to https://lore.kernel.org/linux-pci/be8ddb33a7360af1815cf686f77f3f0913d02be3.camel@suse.de]
16 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
17 Reviewed-by: Andrew Murray <andrew.murray@arm.com>
18 Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
19 ---
20 drivers/pci/controller/Kconfig | 8 +
21 drivers/pci/controller/Makefile | 1 +
22 drivers/pci/controller/pcie-brcmstb.c | 755 ++++++++++++++++++++++++++
23 3 files changed, 764 insertions(+)
24 create mode 100644 drivers/pci/controller/pcie-brcmstb.c
25
26 --- a/drivers/pci/controller/Kconfig
27 +++ b/drivers/pci/controller/Kconfig
28 @@ -281,6 +281,14 @@ config VMD
29 To compile this driver as a module, choose M here: the
30 module will be called vmd.
31
32 +config PCIE_BRCMSTB
33 + tristate "Broadcom Brcmstb PCIe host controller"
34 + depends on ARCH_BCM2835 || COMPILE_TEST
35 + depends on OF
36 + help
37 + Say Y here to enable PCIe host controller support for
38 + Broadcom STB based SoCs, like the Raspberry Pi 4.
39 +
40 config PCI_HYPERV_INTERFACE
41 tristate "Hyper-V PCI Interface"
42 depends on X86 && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && X86_64
43 --- a/drivers/pci/controller/Makefile
44 +++ b/drivers/pci/controller/Makefile
45 @@ -30,6 +30,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-medi
46 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
47 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
48 obj-$(CONFIG_VMD) += vmd.o
49 +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
50 # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
51 obj-y += dwc/
52
53 --- /dev/null
54 +++ b/drivers/pci/controller/pcie-brcmstb.c
55 @@ -0,0 +1,755 @@
56 +// SPDX-License-Identifier: GPL-2.0+
57 +/* Copyright (C) 2009 - 2019 Broadcom */
58 +
59 +#include <linux/bitfield.h>
60 +#include <linux/clk.h>
61 +#include <linux/compiler.h>
62 +#include <linux/delay.h>
63 +#include <linux/init.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/io.h>
66 +#include <linux/ioport.h>
67 +#include <linux/irqdomain.h>
68 +#include <linux/kernel.h>
69 +#include <linux/list.h>
70 +#include <linux/log2.h>
71 +#include <linux/module.h>
72 +#include <linux/of_address.h>
73 +#include <linux/of_irq.h>
74 +#include <linux/of_pci.h>
75 +#include <linux/of_platform.h>
76 +#include <linux/pci.h>
77 +#include <linux/printk.h>
78 +#include <linux/sizes.h>
79 +#include <linux/slab.h>
80 +#include <linux/string.h>
81 +#include <linux/types.h>
82 +
83 +#include "../pci.h"
84 +
85 +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
86 +#define BRCM_PCIE_CAP_REGS 0x00ac
87 +
88 +/* Broadcom STB PCIe Register Offsets */
89 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
90 +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
91 +#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
92 +
93 +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
94 +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
95 +
96 +#define PCIE_RC_DL_MDIO_ADDR 0x1100
97 +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
98 +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
99 +
100 +#define PCIE_MISC_MISC_CTRL 0x4008
101 +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
102 +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
103 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
104 +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128 0x0
105 +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
106 +
107 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
108 +#define PCIE_MEM_WIN0_LO(win) \
109 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
110 +
111 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
112 +#define PCIE_MEM_WIN0_HI(win) \
113 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
114 +
115 +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
116 +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
117 +
118 +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
119 +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
120 +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
121 +
122 +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
123 +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
124 +
125 +#define PCIE_MISC_PCIE_CTRL 0x4064
126 +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
127 +
128 +#define PCIE_MISC_PCIE_STATUS 0x4068
129 +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
130 +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
131 +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
132 +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
133 +
134 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
135 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
136 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
137 +#define PCIE_MEM_WIN0_BASE_LIMIT(win) \
138 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
139 +
140 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
141 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
142 +#define PCIE_MEM_WIN0_BASE_HI(win) \
143 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
144 +
145 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
146 +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
147 +#define PCIE_MEM_WIN0_LIMIT_HI(win) \
148 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
149 +
150 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
151 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
152 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
153 +
154 +#define PCIE_MSI_INTR2_STATUS 0x4500
155 +#define PCIE_MSI_INTR2_CLR 0x4508
156 +#define PCIE_MSI_INTR2_MASK_SET 0x4510
157 +#define PCIE_MSI_INTR2_MASK_CLR 0x4514
158 +
159 +#define PCIE_EXT_CFG_DATA 0x8000
160 +
161 +#define PCIE_EXT_CFG_INDEX 0x9000
162 +#define PCIE_EXT_BUSNUM_SHIFT 20
163 +#define PCIE_EXT_SLOT_SHIFT 15
164 +#define PCIE_EXT_FUNC_SHIFT 12
165 +
166 +#define PCIE_RGR1_SW_INIT_1 0x9210
167 +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
168 +#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2
169 +
170 +/* PCIe parameters */
171 +#define BRCM_NUM_PCIE_OUT_WINS 0x4
172 +
173 +/* MDIO registers */
174 +#define MDIO_PORT0 0x0
175 +#define MDIO_DATA_MASK 0x7fffffff
176 +#define MDIO_PORT_MASK 0xf0000
177 +#define MDIO_REGAD_MASK 0xffff
178 +#define MDIO_CMD_MASK 0xfff00000
179 +#define MDIO_CMD_READ 0x1
180 +#define MDIO_CMD_WRITE 0x0
181 +#define MDIO_DATA_DONE_MASK 0x80000000
182 +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
183 +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
184 +#define SSC_REGS_ADDR 0x1100
185 +#define SET_ADDR_OFFSET 0x1f
186 +#define SSC_CNTL_OFFSET 0x2
187 +#define SSC_CNTL_OVRD_EN_MASK 0x8000
188 +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
189 +#define SSC_STATUS_OFFSET 0x1
190 +#define SSC_STATUS_SSC_MASK 0x400
191 +#define SSC_STATUS_PLL_LOCK_MASK 0x800
192 +
193 +/* Internal PCIe Host Controller Information.*/
194 +struct brcm_pcie {
195 + struct device *dev;
196 + void __iomem *base;
197 + struct clk *clk;
198 + struct pci_bus *root_bus;
199 + struct device_node *np;
200 + bool ssc;
201 + int gen;
202 +};
203 +
204 +/*
205 + * This is to convert the size of the inbound "BAR" region to the
206 + * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
207 + */
208 +static int brcm_pcie_encode_ibar_size(u64 size)
209 +{
210 + int log2_in = ilog2(size);
211 +
212 + if (log2_in >= 12 && log2_in <= 15)
213 + /* Covers 4KB to 32KB (inclusive) */
214 + return (log2_in - 12) + 0x1c;
215 + else if (log2_in >= 16 && log2_in <= 35)
216 + /* Covers 64KB to 32GB, (inclusive) */
217 + return log2_in - 15;
218 + /* Something is awry so disable */
219 + return 0;
220 +}
221 +
222 +static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
223 +{
224 + u32 pkt = 0;
225 +
226 + pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
227 + pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
228 + pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
229 +
230 + return pkt;
231 +}
232 +
233 +/* negative return value indicates error */
234 +static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
235 +{
236 + int tries;
237 + u32 data;
238 +
239 + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
240 + base + PCIE_RC_DL_MDIO_ADDR);
241 + readl(base + PCIE_RC_DL_MDIO_ADDR);
242 +
243 + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
244 + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
245 + udelay(10);
246 + data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
247 + }
248 +
249 + *val = FIELD_GET(MDIO_DATA_MASK, data);
250 + return MDIO_RD_DONE(data) ? 0 : -EIO;
251 +}
252 +
253 +/* negative return value indicates error */
254 +static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
255 + u8 regad, u16 wrdata)
256 +{
257 + int tries;
258 + u32 data;
259 +
260 + writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
261 + base + PCIE_RC_DL_MDIO_ADDR);
262 + readl(base + PCIE_RC_DL_MDIO_ADDR);
263 + writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
264 +
265 + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
266 + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
267 + udelay(10);
268 + data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
269 + }
270 +
271 + return MDIO_WT_DONE(data) ? 0 : -EIO;
272 +}
273 +
274 +/*
275 + * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
276 + * return value indicates error.
277 + */
278 +static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
279 +{
280 + int pll, ssc;
281 + int ret;
282 + u32 tmp;
283 +
284 + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
285 + SSC_REGS_ADDR);
286 + if (ret < 0)
287 + return ret;
288 +
289 + ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
290 + SSC_CNTL_OFFSET, &tmp);
291 + if (ret < 0)
292 + return ret;
293 +
294 + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
295 + u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
296 + ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
297 + SSC_CNTL_OFFSET, tmp);
298 + if (ret < 0)
299 + return ret;
300 +
301 + usleep_range(1000, 2000);
302 + ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
303 + SSC_STATUS_OFFSET, &tmp);
304 + if (ret < 0)
305 + return ret;
306 +
307 + ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
308 + pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
309 +
310 + return ssc && pll ? 0 : -EIO;
311 +}
312 +
313 +/* Limits operation to a specific generation (1, 2, or 3) */
314 +static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
315 +{
316 + u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
317 + u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
318 +
319 + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
320 + writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
321 +
322 + lnkctl2 = (lnkctl2 & ~0xf) | gen;
323 + writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
324 +}
325 +
326 +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
327 + unsigned int win, u64 cpu_addr,
328 + u64 pcie_addr, u64 size)
329 +{
330 + u32 cpu_addr_mb_high, limit_addr_mb_high;
331 + phys_addr_t cpu_addr_mb, limit_addr_mb;
332 + int high_addr_shift;
333 + u32 tmp;
334 +
335 + /* Set the base of the pcie_addr window */
336 + writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
337 + writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
338 +
339 + /* Write the addr base & limit lower bits (in MBs) */
340 + cpu_addr_mb = cpu_addr / SZ_1M;
341 + limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
342 +
343 + tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
344 + u32p_replace_bits(&tmp, cpu_addr_mb,
345 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
346 + u32p_replace_bits(&tmp, limit_addr_mb,
347 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
348 + writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
349 +
350 + /* Write the cpu & limit addr upper bits */
351 + high_addr_shift =
352 + HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
353 +
354 + cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
355 + tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
356 + u32p_replace_bits(&tmp, cpu_addr_mb_high,
357 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
358 + writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
359 +
360 + limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
361 + tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
362 + u32p_replace_bits(&tmp, limit_addr_mb_high,
363 + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
364 + writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
365 +}
366 +
367 +/* The controller is capable of serving in both RC and EP roles */
368 +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
369 +{
370 + void __iomem *base = pcie->base;
371 + u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
372 +
373 + return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
374 +}
375 +
376 +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
377 +{
378 + u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
379 + u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
380 + u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
381 +
382 + return dla && plu;
383 +}
384 +
385 +/* Configuration space read/write support */
386 +static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg)
387 +{
388 + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT)
389 + | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT)
390 + | (busnr << PCIE_EXT_BUSNUM_SHIFT)
391 + | (reg & ~3);
392 +}
393 +
394 +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
395 + int where)
396 +{
397 + struct brcm_pcie *pcie = bus->sysdata;
398 + void __iomem *base = pcie->base;
399 + int idx;
400 +
401 + /* Accesses to the RC go right to the RC registers if slot==0 */
402 + if (pci_is_root_bus(bus))
403 + return PCI_SLOT(devfn) ? NULL : base + where;
404 +
405 + /* For devices, write to the config space index register */
406 + idx = brcm_pcie_cfg_index(bus->number, devfn, 0);
407 + writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
408 + return base + PCIE_EXT_CFG_DATA + where;
409 +}
410 +
411 +static struct pci_ops brcm_pcie_ops = {
412 + .map_bus = brcm_pcie_map_conf,
413 + .read = pci_generic_config_read,
414 + .write = pci_generic_config_write,
415 +};
416 +
417 +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val)
418 +{
419 + u32 tmp;
420 +
421 + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1);
422 + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_INIT_MASK);
423 + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1);
424 +}
425 +
426 +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val)
427 +{
428 + u32 tmp;
429 +
430 + tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1);
431 + u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
432 + writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1);
433 +}
434 +
435 +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
436 + u64 *rc_bar2_size,
437 + u64 *rc_bar2_offset)
438 +{
439 + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
440 + struct device *dev = pcie->dev;
441 + struct resource_entry *entry;
442 +
443 + entry = resource_list_first_type(&bridge->dma_ranges, IORESOURCE_MEM);
444 + if (!entry)
445 + return -ENODEV;
446 +
447 +
448 + /*
449 + * The controller expects the inbound window offset to be calculated as
450 + * the difference between PCIe's address space and CPU's. The offset
451 + * provided by the firmware is calculated the opposite way, so we
452 + * negate it.
453 + */
454 + *rc_bar2_offset = -entry->offset;
455 + *rc_bar2_size = 1ULL << fls64(entry->res->end - entry->res->start);
456 +
457 + /*
458 + * We validate the inbound memory view even though we should trust
459 + * whatever the device-tree provides. This is because of an HW issue on
460 + * early Raspberry Pi 4's revisions (bcm2711). It turns out its
461 + * firmware has to dynamically edit dma-ranges due to a bug on the
462 + * PCIe controller integration, which prohibits any access above the
463 + * lower 3GB of memory. Given this, we decided to keep the dma-ranges
464 + * in check, avoiding hard to debug device-tree related issues in the
465 + * future:
466 + *
467 + * The PCIe host controller by design must set the inbound viewport to
468 + * be a contiguous arrangement of all of the system's memory. In
469 + * addition, its size mut be a power of two. To further complicate
470 + * matters, the viewport must start on a pcie-address that is aligned
471 + * on a multiple of its size. If a portion of the viewport does not
472 + * represent system memory -- e.g. 3GB of memory requires a 4GB
473 + * viewport -- we can map the outbound memory in or after 3GB and even
474 + * though the viewport will overlap the outbound memory the controller
475 + * will know to send outbound memory downstream and everything else
476 + * upstream.
477 + *
478 + * For example:
479 + *
480 + * - The best-case scenario, memory up to 3GB, is to place the inbound
481 + * region in the first 4GB of pcie-space, as some legacy devices can
482 + * only address 32bits. We would also like to put the MSI under 4GB
483 + * as well, since some devices require a 32bit MSI target address.
484 + *
485 + * - If the system memory is 4GB or larger we cannot start the inbound
486 + * region at location 0 (since we have to allow some space for
487 + * outbound memory @ 3GB). So instead it will start at the 1x
488 + * multiple of its size
489 + */
490 + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size ||
491 + (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
492 + dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
493 + *rc_bar2_size, *rc_bar2_offset);
494 + return -EINVAL;
495 + }
496 +
497 + return 0;
498 +}
499 +
500 +static int brcm_pcie_setup(struct brcm_pcie *pcie)
501 +{
502 + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
503 + u64 rc_bar2_offset, rc_bar2_size;
504 + void __iomem *base = pcie->base;
505 + struct device *dev = pcie->dev;
506 + struct resource_entry *entry;
507 + unsigned int scb_size_val;
508 + bool ssc_good = false;
509 + struct resource *res;
510 + int num_out_wins = 0;
511 + u16 nlw, cls, lnksta;
512 + int i, ret;
513 + u32 tmp;
514 +
515 + /* Reset the bridge */
516 + brcm_pcie_bridge_sw_init_set(pcie, 1);
517 +
518 + usleep_range(100, 200);
519 +
520 + /* Take the bridge out of reset */
521 + brcm_pcie_bridge_sw_init_set(pcie, 0);
522 +
523 + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
524 + tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
525 + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
526 + /* Wait for SerDes to be stable */
527 + usleep_range(100, 200);
528 +
529 + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
530 + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
531 + u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
532 + u32p_replace_bits(&tmp, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_128,
533 + PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
534 + writel(tmp, base + PCIE_MISC_MISC_CTRL);
535 +
536 + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
537 + &rc_bar2_offset);
538 + if (ret)
539 + return ret;
540 +
541 + tmp = lower_32_bits(rc_bar2_offset);
542 + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
543 + PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
544 + writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
545 + writel(upper_32_bits(rc_bar2_offset),
546 + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
547 +
548 + scb_size_val = rc_bar2_size ?
549 + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */
550 + tmp = readl(base + PCIE_MISC_MISC_CTRL);
551 + u32p_replace_bits(&tmp, scb_size_val,
552 + PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK);
553 + writel(tmp, base + PCIE_MISC_MISC_CTRL);
554 +
555 + /* disable the PCIe->GISB memory window (RC_BAR1) */
556 + tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
557 + tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
558 + writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
559 +
560 + /* disable the PCIe->SCB memory window (RC_BAR3) */
561 + tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
562 + tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
563 + writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
564 +
565 + /* Mask all interrupts since we are not handling any yet */
566 + writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_MASK_SET);
567 +
568 + /* clear any interrupts we find on boot */
569 + writel(0xffffffff, pcie->base + PCIE_MSI_INTR2_CLR);
570 +
571 + if (pcie->gen)
572 + brcm_pcie_set_gen(pcie, pcie->gen);
573 +
574 + /* Unassert the fundamental reset */
575 + brcm_pcie_perst_set(pcie, 0);
576 +
577 + /*
578 + * Give the RC/EP time to wake up, before trying to configure RC.
579 + * Intermittently check status for link-up, up to a total of 100ms.
580 + */
581 + for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
582 + msleep(5);
583 +
584 + if (!brcm_pcie_link_up(pcie)) {
585 + dev_err(dev, "link down\n");
586 + return -ENODEV;
587 + }
588 +
589 + if (!brcm_pcie_rc_mode(pcie)) {
590 + dev_err(dev, "PCIe misconfigured; is in EP mode\n");
591 + return -EINVAL;
592 + }
593 +
594 + resource_list_for_each_entry(entry, &bridge->windows) {
595 + res = entry->res;
596 +
597 + if (resource_type(res) != IORESOURCE_MEM)
598 + continue;
599 +
600 + if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
601 + dev_err(pcie->dev, "too many outbound wins\n");
602 + return -EINVAL;
603 + }
604 +
605 + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
606 + res->start - entry->offset,
607 + resource_size(res));
608 + num_out_wins++;
609 + }
610 +
611 + /*
612 + * For config space accesses on the RC, show the right class for
613 + * a PCIe-PCIe bridge (the default setting is to be EP mode).
614 + */
615 + tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
616 + u32p_replace_bits(&tmp, 0x060400,
617 + PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
618 + writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
619 +
620 + if (pcie->ssc) {
621 + ret = brcm_pcie_set_ssc(pcie);
622 + if (ret == 0)
623 + ssc_good = true;
624 + else
625 + dev_err(dev, "failed attempt to enter ssc mode\n");
626 + }
627 +
628 + lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
629 + cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
630 + nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
631 + dev_info(dev, "link up, %s x%u %s\n",
632 + PCIE_SPEED2STR(cls + PCI_SPEED_133MHz_PCIX_533),
633 + nlw, ssc_good ? "(SSC)" : "(!SSC)");
634 +
635 + /* PCIe->SCB endian mode for BAR */
636 + tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
637 + u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
638 + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
639 + writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
640 +
641 + /*
642 + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
643 + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
644 + */
645 + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
646 + tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
647 + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
648 +
649 + return 0;
650 +}
651 +
652 +/* L23 is a low-power PCIe link state */
653 +static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
654 +{
655 + void __iomem *base = pcie->base;
656 + int l23, i;
657 + u32 tmp;
658 +
659 + /* Assert request for L23 */
660 + tmp = readl(base + PCIE_MISC_PCIE_CTRL);
661 + u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
662 + writel(tmp, base + PCIE_MISC_PCIE_CTRL);
663 +
664 + /* Wait up to 36 msec for L23 */
665 + tmp = readl(base + PCIE_MISC_PCIE_STATUS);
666 + l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
667 + for (i = 0; i < 15 && !l23; i++) {
668 + usleep_range(2000, 2400);
669 + tmp = readl(base + PCIE_MISC_PCIE_STATUS);
670 + l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
671 + tmp);
672 + }
673 +
674 + if (!l23)
675 + dev_err(pcie->dev, "failed to enter low-power link state\n");
676 +}
677 +
678 +static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
679 +{
680 + void __iomem *base = pcie->base;
681 + int tmp;
682 +
683 + if (brcm_pcie_link_up(pcie))
684 + brcm_pcie_enter_l23(pcie);
685 + /* Assert fundamental reset */
686 + brcm_pcie_perst_set(pcie, 1);
687 +
688 + /* Deassert request for L23 in case it was asserted */
689 + tmp = readl(base + PCIE_MISC_PCIE_CTRL);
690 + u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
691 + writel(tmp, base + PCIE_MISC_PCIE_CTRL);
692 +
693 + /* Turn off SerDes */
694 + tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
695 + u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
696 + writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
697 +
698 + /* Shutdown PCIe bridge */
699 + brcm_pcie_bridge_sw_init_set(pcie, 1);
700 +}
701 +
702 +static void __brcm_pcie_remove(struct brcm_pcie *pcie)
703 +{
704 + brcm_pcie_turn_off(pcie);
705 + clk_disable_unprepare(pcie->clk);
706 + clk_put(pcie->clk);
707 +}
708 +
709 +static int brcm_pcie_remove(struct platform_device *pdev)
710 +{
711 + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
712 +
713 + pci_stop_root_bus(pcie->root_bus);
714 + pci_remove_root_bus(pcie->root_bus);
715 + __brcm_pcie_remove(pcie);
716 +
717 + return 0;
718 +}
719 +
720 +static int brcm_pcie_probe(struct platform_device *pdev)
721 +{
722 + struct device_node *np = pdev->dev.of_node;
723 + struct pci_host_bridge *bridge;
724 + struct brcm_pcie *pcie;
725 + struct pci_bus *child;
726 + struct resource *res;
727 + int ret;
728 +
729 + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
730 + if (!bridge)
731 + return -ENOMEM;
732 +
733 + pcie = pci_host_bridge_priv(bridge);
734 + pcie->dev = &pdev->dev;
735 + pcie->np = np;
736 +
737 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
738 + pcie->base = devm_ioremap_resource(&pdev->dev, res);
739 + if (IS_ERR(pcie->base))
740 + return PTR_ERR(pcie->base);
741 +
742 + pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
743 + if (IS_ERR(pcie->clk))
744 + return PTR_ERR(pcie->clk);
745 +
746 + ret = of_pci_get_max_link_speed(np);
747 + pcie->gen = (ret < 0) ? 0 : ret;
748 +
749 + pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
750 +
751 + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows,
752 + &bridge->dma_ranges, NULL);
753 + if (ret)
754 + return ret;
755 +
756 + ret = clk_prepare_enable(pcie->clk);
757 + if (ret) {
758 + dev_err(&pdev->dev, "could not enable clock\n");
759 + return ret;
760 + }
761 +
762 + ret = brcm_pcie_setup(pcie);
763 + if (ret)
764 + goto fail;
765 +
766 + bridge->dev.parent = &pdev->dev;
767 + bridge->busnr = 0;
768 + bridge->ops = &brcm_pcie_ops;
769 + bridge->sysdata = pcie;
770 + bridge->map_irq = of_irq_parse_and_map_pci;
771 + bridge->swizzle_irq = pci_common_swizzle;
772 +
773 + ret = pci_scan_root_bus_bridge(bridge);
774 + if (ret < 0) {
775 + dev_err(pcie->dev, "Scanning root bridge failed\n");
776 + goto fail;
777 + }
778 +
779 + pci_assign_unassigned_bus_resources(bridge->bus);
780 + list_for_each_entry(child, &bridge->bus->children, node)
781 + pcie_bus_configure_settings(child);
782 + pci_bus_add_devices(bridge->bus);
783 + platform_set_drvdata(pdev, pcie);
784 + pcie->root_bus = bridge->bus;
785 +
786 + return 0;
787 +fail:
788 + __brcm_pcie_remove(pcie);
789 + return ret;
790 +}
791 +
792 +static const struct of_device_id brcm_pcie_match[] = {
793 + { .compatible = "brcm,bcm2711-pcie" },
794 + {},
795 +};
796 +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
797 +
798 +static struct platform_driver brcm_pcie_driver = {
799 + .probe = brcm_pcie_probe,
800 + .remove = brcm_pcie_remove,
801 + .driver = {
802 + .name = "brcm-pcie",
803 + .of_match_table = brcm_pcie_match,
804 + },
805 +};
806 +module_platform_driver(brcm_pcie_driver);
807 +
808 +MODULE_LICENSE("GPL");
809 +MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
810 +MODULE_AUTHOR("Broadcom");
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