1 From 120c8f221cb18f6630d5cb954484bac88288cced Mon Sep 17 00:00:00 2001
2 From: Haiying Wang <Haiying.Wang@freescale.com>
3 Date: Wed, 22 Apr 2015 13:07:25 -0400
4 Subject: [PATCH] arm64: add ioremap for normal cacheable non-shareable memory
6 Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
7 Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
8 Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
10 arch/arm64/include/asm/io.h | 1 +
11 arch/arm64/include/asm/pgtable-prot.h | 1 +
12 2 files changed, 2 insertions(+)
14 --- a/arch/arm64/include/asm/io.h
15 +++ b/arch/arm64/include/asm/io.h
16 @@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_
17 #define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
18 #define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
19 #define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
20 +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS))
23 * PCI configuration space mapping function.
24 --- a/arch/arm64/include/asm/pgtable-prot.h
25 +++ b/arch/arm64/include/asm/pgtable-prot.h
27 #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
28 #define PROT_NORMAL_WT (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
29 #define PROT_NORMAL (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
30 +#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
32 #define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
33 #define PROT_SECT_NORMAL (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))