git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From d9bf944beaaad1890ad3fcb755c61e1c7e4c5630 Mon Sep 17 00:00:00 2001
   2 From: Sam Shih <sam.shih@mediatek.com>
   3 Date: Sun, 17 Dec 2023 21:50:07 +0000
   4 Subject: [PATCH 3/4] clk: mediatek: add pcw_chg_bit control for PLLs of MT7988
   5
   6 Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
   7 of the previously hardcoded PCW_CHG_MASK macro if set.
   8 This will needed for clocks on the MT7988 SoC.
   9
  10 Signed-off-by: Sam Shih <sam.shih@mediatek.com>
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  13 Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  drivers/clk/mediatek/clk-pll.c | 5 +++--
  17  drivers/clk/mediatek/clk-pll.h | 1 +
  18  2 files changed, 4 insertions(+), 2 deletions(-)
  19
  20 --- a/drivers/clk/mediatek/clk-pll.c
  21 +++ b/drivers/clk/mediatek/clk-pll.c
  22 @@ -23,7 +23,7 @@
  23  #define CON0_BASE_EN           BIT(0)
  24  #define CON0_PWR_ON            BIT(0)
  25  #define CON0_ISO_EN            BIT(1)
  26 -#define PCW_CHG_MASK           BIT(31)
  27 +#define PCW_CHG_BIT            31
  28
  29  #define AUDPLL_TUNER_EN                BIT(31)
  30
  31 @@ -141,7 +141,8 @@ static void mtk_pll_set_rate_regs(struct
  32                         pll->data->pcw_shift);
  33         val |= pcw << pll->data->pcw_shift;
  34         writel(val, pll->pcw_addr);
  35 -       chg = readl(pll->pcw_chg_addr) | PCW_CHG_MASK;
  36 +       chg = readl(pll->pcw_chg_addr) |
  37 +             BIT(pll->data->pcw_chg_bit ? : PCW_CHG_BIT);
  38         writel(chg, pll->pcw_chg_addr);
  39         if (pll->tuner_addr)
  40                 writel(val + 1, pll->tuner_addr);
  41 --- a/drivers/clk/mediatek/clk-pll.h
  42 +++ b/drivers/clk/mediatek/clk-pll.h
  43 @@ -46,6 +46,7 @@ struct mtk_pll_data {
  44         const char *parent_name;
  45         u32 en_reg;
  46         u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
  47 +       u8 pcw_chg_bit;
  48  };
  49
  50  int mtk_clk_register_plls(struct device_node *node,