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1 From 1dbc1bdc2869e6d2929235c70d64e393aa5a5fa2 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
3 Date: Mon, 22 Apr 2024 10:15:12 +0300
4 Subject: [PATCH 05/15] net: dsa: mt7530: refactor MT7530_MFC and MT7531_CFC,
5 add MT7531_QRY_FFP
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 The MT7530_MFC register is on MT7530, MT7531, and the switch on the MT7988
11 SoC. Rename it to MT753X_MFC. Bit 7 to 0 differs between MT7530 and
12 MT7531/MT7988. Add MT7530 prefix to these definitions, and define the
13 IGMP/MLD Query Frame Flooding Ports mask for MT7531.
14
15 Rename the cases of MIRROR_MASK to MIRROR_PORT_MASK.
16
17 Move mt753x_mirror_port_get() and mt753x_port_mirror_set() to mt7530.h as
18 macros.
19
20 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
21 ---
22 drivers/net/dsa/mt7530.c | 38 ++++++++--------------
23 drivers/net/dsa/mt7530.h | 69 +++++++++++++++++++++++++---------------
24 2 files changed, 57 insertions(+), 50 deletions(-)
25
26 --- a/drivers/net/dsa/mt7530.c
27 +++ b/drivers/net/dsa/mt7530.c
28 @@ -1154,7 +1154,7 @@ mt753x_cpu_port_enable(struct dsa_switch
29 PORT_SPEC_TAG);
30
31 /* Enable flooding on the CPU port */
32 - mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
33 + mt7530_set(priv, MT753X_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) |
34 UNU_FFP(BIT(port)));
35
36 /* Add the CPU port to the CPU port bitmap for MT7531. Trapped frames
37 @@ -1318,15 +1318,15 @@ mt7530_port_bridge_flags(struct dsa_swit
38 flags.val & BR_LEARNING ? 0 : SA_DIS);
39
40 if (flags.mask & BR_FLOOD)
41 - mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)),
42 + mt7530_rmw(priv, MT753X_MFC, UNU_FFP(BIT(port)),
43 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
44
45 if (flags.mask & BR_MCAST_FLOOD)
46 - mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)),
47 + mt7530_rmw(priv, MT753X_MFC, UNM_FFP(BIT(port)),
48 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
49
50 if (flags.mask & BR_BCAST_FLOOD)
51 - mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)),
52 + mt7530_rmw(priv, MT753X_MFC, BC_FFP(BIT(port)),
53 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
54
55 return 0;
56 @@ -1862,20 +1862,6 @@ mt7530_port_vlan_del(struct dsa_switch *
57 return 0;
58 }
59
60 -static int mt753x_mirror_port_get(unsigned int id, u32 val)
61 -{
62 - return (id == ID_MT7531 || id == ID_MT7988) ?
63 - MT7531_MIRROR_PORT_GET(val) :
64 - MIRROR_PORT(val);
65 -}
66 -
67 -static int mt753x_mirror_port_set(unsigned int id, u32 val)
68 -{
69 - return (id == ID_MT7531 || id == ID_MT7988) ?
70 - MT7531_MIRROR_PORT_SET(val) :
71 - MIRROR_PORT(val);
72 -}
73 -
74 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
75 struct dsa_mall_mirror_tc_entry *mirror,
76 bool ingress, struct netlink_ext_ack *extack)
77 @@ -1891,14 +1877,14 @@ static int mt753x_port_mirror_add(struct
78 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
79
80 /* MT7530 only supports one monitor port */
81 - monitor_port = mt753x_mirror_port_get(priv->id, val);
82 + monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
83 if (val & MT753X_MIRROR_EN(priv->id) &&
84 monitor_port != mirror->to_local_port)
85 return -EEXIST;
86
87 val |= MT753X_MIRROR_EN(priv->id);
88 - val &= ~MT753X_MIRROR_MASK(priv->id);
89 - val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
90 + val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
91 + val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
92 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
93
94 val = mt7530_read(priv, MT7530_PCR_P(port));
95 @@ -2538,7 +2524,7 @@ mt7531_setup_common(struct dsa_switch *d
96 mt7530_mib_reset(ds);
97
98 /* Disable flooding on all ports */
99 - mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK |
100 + mt7530_clear(priv, MT753X_MFC, BC_FFP_MASK | UNM_FFP_MASK |
101 UNU_FFP_MASK);
102
103 for (i = 0; i < MT7530_NUM_PORTS; i++) {
104 @@ -3100,10 +3086,12 @@ mt753x_conduit_state_change(struct dsa_s
105 else
106 priv->active_cpu_ports &= ~mask;
107
108 - if (priv->active_cpu_ports)
109 - val = CPU_EN | CPU_PORT(__ffs(priv->active_cpu_ports));
110 + if (priv->active_cpu_ports) {
111 + val = MT7530_CPU_EN |
112 + MT7530_CPU_PORT(__ffs(priv->active_cpu_ports));
113 + }
114
115 - mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, val);
116 + mt7530_rmw(priv, MT753X_MFC, MT7530_CPU_EN | MT7530_CPU_PORT_MASK, val);
117 }
118
119 static int mt7988_setup(struct dsa_switch *ds)
120 --- a/drivers/net/dsa/mt7530.h
121 +++ b/drivers/net/dsa/mt7530.h
122 @@ -36,36 +36,55 @@ enum mt753x_id {
123 #define MT753X_AGC 0xc
124 #define LOCAL_EN BIT(7)
125
126 -/* Registers to mac forward control for unknown frames */
127 -#define MT7530_MFC 0x10
128 -#define BC_FFP(x) (((x) & 0xff) << 24)
129 -#define BC_FFP_MASK BC_FFP(~0)
130 -#define UNM_FFP(x) (((x) & 0xff) << 16)
131 -#define UNM_FFP_MASK UNM_FFP(~0)
132 -#define UNU_FFP(x) (((x) & 0xff) << 8)
133 -#define UNU_FFP_MASK UNU_FFP(~0)
134 -#define CPU_EN BIT(7)
135 -#define CPU_PORT_MASK GENMASK(6, 4)
136 -#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x)
137 -#define MIRROR_EN BIT(3)
138 -#define MIRROR_PORT(x) ((x) & 0x7)
139 -#define MIRROR_MASK 0x7
140 +/* Register for MAC forward control */
141 +#define MT753X_MFC 0x10
142 +#define BC_FFP_MASK GENMASK(31, 24)
143 +#define BC_FFP(x) FIELD_PREP(BC_FFP_MASK, x)
144 +#define UNM_FFP_MASK GENMASK(23, 16)
145 +#define UNM_FFP(x) FIELD_PREP(UNM_FFP_MASK, x)
146 +#define UNU_FFP_MASK GENMASK(15, 8)
147 +#define UNU_FFP(x) FIELD_PREP(UNU_FFP_MASK, x)
148 +#define MT7530_CPU_EN BIT(7)
149 +#define MT7530_CPU_PORT_MASK GENMASK(6, 4)
150 +#define MT7530_CPU_PORT(x) FIELD_PREP(MT7530_CPU_PORT_MASK, x)
151 +#define MT7530_MIRROR_EN BIT(3)
152 +#define MT7530_MIRROR_PORT_MASK GENMASK(2, 0)
153 +#define MT7530_MIRROR_PORT_GET(x) FIELD_GET(MT7530_MIRROR_PORT_MASK, x)
154 +#define MT7530_MIRROR_PORT_SET(x) FIELD_PREP(MT7530_MIRROR_PORT_MASK, x)
155 +#define MT7531_QRY_FFP_MASK GENMASK(7, 0)
156 +#define MT7531_QRY_FFP(x) FIELD_PREP(MT7531_QRY_FFP_MASK, x)
157
158 -/* Registers for CPU forward control */
159 +/* Register for CPU forward control */
160 #define MT7531_CFC 0x4
161 #define MT7531_MIRROR_EN BIT(19)
162 -#define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
163 -#define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
164 -#define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
165 +#define MT7531_MIRROR_PORT_MASK GENMASK(18, 16)
166 +#define MT7531_MIRROR_PORT_GET(x) FIELD_GET(MT7531_MIRROR_PORT_MASK, x)
167 +#define MT7531_MIRROR_PORT_SET(x) FIELD_PREP(MT7531_MIRROR_PORT_MASK, x)
168 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
169 #define MT7531_CPU_PMAP(x) FIELD_PREP(MT7531_CPU_PMAP_MASK, x)
170
171 -#define MT753X_MIRROR_REG(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
172 - MT7531_CFC : MT7530_MFC)
173 -#define MT753X_MIRROR_EN(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
174 - MT7531_MIRROR_EN : MIRROR_EN)
175 -#define MT753X_MIRROR_MASK(id) ((((id) == ID_MT7531) || ((id) == ID_MT7988)) ? \
176 - MT7531_MIRROR_MASK : MIRROR_MASK)
177 +#define MT753X_MIRROR_REG(id) ((id == ID_MT7531 || \
178 + id == ID_MT7988) ? \
179 + MT7531_CFC : MT753X_MFC)
180 +
181 +#define MT753X_MIRROR_EN(id) ((id == ID_MT7531 || \
182 + id == ID_MT7988) ? \
183 + MT7531_MIRROR_EN : MT7530_MIRROR_EN)
184 +
185 +#define MT753X_MIRROR_PORT_MASK(id) ((id == ID_MT7531 || \
186 + id == ID_MT7988) ? \
187 + MT7531_MIRROR_PORT_MASK : \
188 + MT7530_MIRROR_PORT_MASK)
189 +
190 +#define MT753X_MIRROR_PORT_GET(id, val) ((id == ID_MT7531 || \
191 + id == ID_MT7988) ? \
192 + MT7531_MIRROR_PORT_GET(val) : \
193 + MT7530_MIRROR_PORT_GET(val))
194 +
195 +#define MT753X_MIRROR_PORT_SET(id, val) ((id == ID_MT7531 || \
196 + id == ID_MT7988) ? \
197 + MT7531_MIRROR_PORT_SET(val) : \
198 + MT7530_MIRROR_PORT_SET(val))
199
200 /* Register for BPDU and PAE frame control */
201 #define MT753X_BPC 0x24
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