git.openwrt.org Git - openwrt/staging/blogic.git/blob

   1 From 7f54cc9772ced2d76ac11832f0ada43798443ac9 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Mon, 3 Apr 2023 02:19:02 +0100
   4 Subject: [PATCH 13/16] net: dsa: mt7530: split-off common parts from
   5  mt7531_setup
   6
   7 MT7988 shares a significant part of the setup function with MT7531.
   8 Split-off those parts into a shared function which is going to be used
   9 also by mt7988_setup.
  10
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  13 Signed-off-by: David S. Miller <davem@davemloft.net>
  14 ---
  15  drivers/net/dsa/mt7530.c | 99 ++++++++++++++++++++++------------------
  16  1 file changed, 55 insertions(+), 44 deletions(-)
  17
  18 --- a/drivers/net/dsa/mt7530.c
  19 +++ b/drivers/net/dsa/mt7530.c
  20 @@ -2348,11 +2348,64 @@ mt7530_setup(struct dsa_switch *ds)
  21  }
  22
  23  static int
  24 +mt7531_setup_common(struct dsa_switch *ds)
  25 +{
  26 +       struct mt7530_priv *priv = ds->priv;
  27 +       struct dsa_port *cpu_dp;
  28 +       int ret, i;
  29 +
  30 +       /* BPDU to CPU port */
  31 +       dsa_switch_for_each_cpu_port(cpu_dp, ds) {
  32 +               mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
  33 +                          BIT(cpu_dp->index));
  34 +               break;
  35 +       }
  36 +       mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
  37 +                  MT753X_BPDU_CPU_ONLY);
  38 +
  39 +       /* Enable and reset MIB counters */
  40 +       mt7530_mib_reset(ds);
  41 +
  42 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
  43 +               /* Disable forwarding by default on all ports */
  44 +               mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
  45 +                          PCR_MATRIX_CLR);
  46 +
  47 +               /* Disable learning by default on all ports */
  48 +               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
  49 +
  50 +               mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
  51 +
  52 +               if (dsa_is_cpu_port(ds, i)) {
  53 +                       ret = mt753x_cpu_port_enable(ds, i);
  54 +                       if (ret)
  55 +                               return ret;
  56 +               } else {
  57 +                       mt7530_port_disable(ds, i);
  58 +
  59 +                       /* Set default PVID to 0 on all user ports */
  60 +                       mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
  61 +                                  G0_PORT_VID_DEF);
  62 +               }
  63 +
  64 +               /* Enable consistent egress tag */
  65 +               mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
  66 +                          PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
  67 +       }
  68 +
  69 +       /* Flush the FDB table */
  70 +       ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
  71 +       if (ret < 0)
  72 +               return ret;
  73 +
  74 +       return 0;
  75 +}
  76 +
  77 +static int
  78  mt7531_setup(struct dsa_switch *ds)
  79  {
  80         struct mt7530_priv *priv = ds->priv;
  81         struct mt7530_dummy_poll p;
  82 -       struct dsa_port *cpu_dp;
  83         u32 val, id;
  84         int ret, i;
  85
  86 @@ -2426,44 +2479,7 @@ mt7531_setup(struct dsa_switch *ds)
  87         mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
  88                                  CORE_PLL_GROUP4, val);
  89
  90 -       /* BPDU to CPU port */
  91 -       dsa_switch_for_each_cpu_port(cpu_dp, ds) {
  92 -               mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
  93 -                          BIT(cpu_dp->index));
  94 -               break;
  95 -       }
  96 -       mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
  97 -                  MT753X_BPDU_CPU_ONLY);
  98 -
  99 -       /* Enable and reset MIB counters */
 100 -       mt7530_mib_reset(ds);
 101 -
 102 -       for (i = 0; i < MT7530_NUM_PORTS; i++) {
 103 -               /* Disable forwarding by default on all ports */
 104 -               mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
 105 -                          PCR_MATRIX_CLR);
 106 -
 107 -               /* Disable learning by default on all ports */
 108 -               mt7530_set(priv, MT7530_PSC_P(i), SA_DIS);
 109 -
 110 -               mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
 111 -
 112 -               if (dsa_is_cpu_port(ds, i)) {
 113 -                       ret = mt753x_cpu_port_enable(ds, i);
 114 -                       if (ret)
 115 -                               return ret;
 116 -               } else {
 117 -                       mt7530_port_disable(ds, i);
 118 -
 119 -                       /* Set default PVID to 0 on all user ports */
 120 -                       mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
 121 -                                  G0_PORT_VID_DEF);
 122 -               }
 123 -
 124 -               /* Enable consistent egress tag */
 125 -               mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
 126 -                          PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
 127 -       }
 128 +       mt7531_setup_common(ds);
 129
 130         /* Setup VLAN ID 0 for VLAN-unaware bridges */
 131         ret = mt7530_setup_vlan0(priv);
 132 @@ -2473,11 +2489,6 @@ mt7531_setup(struct dsa_switch *ds)
 133         ds->assisted_learning_on_cpu_port = true;
 134         ds->mtu_enforcement_ingress = true;
 135
 136 -       /* Flush the FDB table */
 137 -       ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
 138 -       if (ret < 0)
 139 -               return ret;
 140 -
 141         return 0;
 142  }
 143