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1 From 06e912bd821b21d9360a75cde2d78b03f17a5872 Mon Sep 17 00:00:00 2001
2 From: Wen He <wen.he_1@nxp.com>
3 Date: Tue, 17 Sep 2019 15:35:52 +0800
4 Subject: [PATCH] drm: ls1028a: Add DP driver support for LS1028A
5
6 Add Display Port driver support for NXP Layerscape LS1028A platform.
7
8 Signed-off-by: Wen He <wen.he_1@nxp.com>
9 ---
10 drivers/gpu/drm/bridge/cadence/cdns-dp-core.c | 1 +
11 drivers/gpu/drm/imx/Makefile | 2 +-
12 drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c | 13 +++
13 drivers/gpu/drm/imx/cdn-mhdp-ls1028a.c | 110 ++++++++++++++++++++++++++
14 drivers/gpu/drm/imx/cdns-mhdp-imx.h | 2 +
15 5 files changed, 127 insertions(+), 1 deletion(-)
16 create mode 100644 drivers/gpu/drm/imx/cdn-mhdp-ls1028a.c
17
18 --- a/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
19 +++ b/drivers/gpu/drm/bridge/cadence/cdns-dp-core.c
20 @@ -275,6 +275,7 @@ static int cdns_dp_bridge_attach(struct
21 struct drm_connector *connector = &mhdp->connector.base;
22
23 connector->interlace_allowed = 1;
24 +
25 connector->polled = DRM_CONNECTOR_POLL_HPD;
26
27 drm_connector_helper_add(connector, &cdns_dp_connector_helper_funcs);
28 --- a/drivers/gpu/drm/imx/Makefile
29 +++ b/drivers/gpu/drm/imx/Makefile
30 @@ -9,4 +9,4 @@ obj-$(CONFIG_DRM_IMX_TVE) += imx-tve.o
31 obj-$(CONFIG_DRM_IMX_LDB) += imx-ldb.o
32
33 obj-$(CONFIG_DRM_IMX_HDMI) += dw_hdmi-imx.o
34 -obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imxdrv.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o cdn-mhdp-imx8qm.o
35 +obj-$(CONFIG_DRM_IMX_CDNS_MHDP) += cdn-mhdp-imxdrv.o cdn-mhdp-dp-phy.o cdn-mhdp-hdmi-phy.o cdn-mhdp-imx8qm.o cdn-mhdp-ls1028a.o
36 --- a/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
37 +++ b/drivers/gpu/drm/imx/cdn-mhdp-imxdrv.c
38 @@ -94,6 +94,16 @@ static struct cdns_plat_data imx8qm_dp_d
39 .is_dp = true,
40 };
41
42 +static struct cdns_plat_data ls1028a_dp_drv_data = {
43 + .bind = cdns_dp_bind,
44 + .unbind = cdns_dp_unbind,
45 + .phy_set = cdns_dp_phy_set_imx8mq,
46 + .power_on = cdns_mhdp_power_on_ls1028a,
47 + .firmware_init = cdns_mhdp_firmware_init_imx8qm,
48 + .pclk_rate = cdns_mhdp_pclk_rate_ls1028a,
49 + .bus_type = BUS_TYPE_NORMAL_APB,
50 +};
51 +
52 static const struct of_device_id cdns_mhdp_imx_dt_ids[] = {
53 { .compatible = "cdn,imx8mq-hdmi",
54 .data = &imx8mq_hdmi_drv_data
55 @@ -107,6 +117,9 @@ static const struct of_device_id cdns_mh
56 { .compatible = "cdn,imx8qm-dp",
57 .data = &imx8qm_dp_drv_data
58 },
59 + { .compatible = "cdn,ls1028a-dp",
60 + .data = &ls1028a_dp_drv_data
61 + },
62 {},
63 };
64 MODULE_DEVICE_TABLE(of, cdns_mhdp_imx_dt_ids);
65 --- /dev/null
66 +++ b/drivers/gpu/drm/imx/cdn-mhdp-ls1028a.c
67 @@ -0,0 +1,110 @@
68 +// SPDX-License-Identifier: GPL-2.0
69 +/*
70 + * Copyright 2019 NXP
71 + *
72 + */
73 +#include <linux/clk.h>
74 +#include <drm/drmP.h>
75 +#include <linux/of.h>
76 +#include <linux/of_address.h>
77 +#include <linux/of_device.h>
78 +
79 +#include "cdns-mhdp-imx.h"
80 +
81 +static const struct of_device_id scfg_device_ids[] = {
82 + { .compatible = "fsl,ls1028a-scfg", },
83 + {}
84 +};
85 +
86 +static void ls1028a_phy_reset(u8 reset)
87 +{
88 + struct device_node *scfg_node;
89 + void __iomem *scfg_base = NULL;
90 +
91 + scfg_node = of_find_matching_node(NULL, scfg_device_ids);
92 + if (scfg_node)
93 + scfg_base = of_iomap(scfg_node, 0);
94 +
95 + iowrite32(reset, scfg_base + 0x230);
96 +}
97 +
98 +int ls1028a_clocks_init(struct imx_mhdp_device *imx_mhdp)
99 +{
100 + struct device *dev = imx_mhdp->mhdp.dev;
101 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
102 +
103 + clks->clk_core = devm_clk_get(dev, "clk_core");
104 + if (IS_ERR(clks->clk_core)) {
105 + dev_warn(dev, "failed to get hdp core clk\n");
106 + return PTR_ERR(clks->clk_core);
107 + }
108 +
109 + clks->clk_pxl = devm_clk_get(dev, "clk_pxl");
110 + if (IS_ERR(clks->clk_pxl)) {
111 + dev_warn(dev, "failed to get pxl clk\n");
112 + return PTR_ERR(clks->clk_pxl);
113 + }
114 +
115 + return true;
116 +}
117 +
118 +static int ls1028a_pixel_clk_enable(struct imx_mhdp_device *imx_mhdp)
119 +{
120 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
121 + struct device *dev = imx_mhdp->mhdp.dev;
122 + int ret;
123 +
124 + ret = clk_prepare_enable(clks->clk_pxl);
125 + if (ret < 0) {
126 + dev_err(dev, "%s, pre clk pxl error\n", __func__);
127 + return ret;
128 + }
129 +
130 + return ret;
131 +}
132 +
133 +static void ls1028a_pixel_clk_disable(struct imx_mhdp_device *imx_mhdp)
134 +{
135 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
136 +
137 + clk_disable_unprepare(clks->clk_pxl);
138 +}
139 +
140 +static void ls1028a_pixel_clk_set_rate(struct imx_mhdp_device *imx_mhdp,
141 + u32 pclock)
142 +{
143 + struct imx_hdp_clks *clks = &imx_mhdp->clks;
144 +
145 + clk_set_rate(clks->clk_pxl, pclock);
146 +}
147 +
148 +int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp)
149 +{
150 + struct imx_mhdp_device *imx_mhdp = container_of
151 + (mhdp, struct imx_mhdp_device, mhdp);
152 +
153 + /* clock init and rate set */
154 + ls1028a_clocks_init(imx_mhdp);
155 +
156 + ls1028a_pixel_clk_enable(imx_mhdp);
157 +
158 + /* Init pixel clock with 148.5MHz before FW init */
159 + ls1028a_pixel_clk_set_rate(imx_mhdp, 148500000);
160 +
161 + ls1028a_phy_reset(1);
162 +
163 + return 0;
164 +}
165 +
166 +void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp)
167 +{
168 + struct imx_mhdp_device *imx_mhdp = container_of
169 + (mhdp, struct imx_mhdp_device, mhdp);
170 +
171 + /* set pixel clock before video mode setup */
172 + ls1028a_pixel_clk_disable(imx_mhdp);
173 +
174 + ls1028a_pixel_clk_set_rate(imx_mhdp, imx_mhdp->mhdp.mode.clock * 1000);
175 +
176 + ls1028a_pixel_clk_enable(imx_mhdp);
177 +}
178 --- a/drivers/gpu/drm/imx/cdns-mhdp-imx.h
179 +++ b/drivers/gpu/drm/imx/cdns-mhdp-imx.h
180 @@ -78,4 +78,6 @@ void cdns_mhdp_plat_deinit_imx8qm(struct
181 void cdns_mhdp_pclk_rate_imx8qm(struct cdns_mhdp_device *mhdp);
182 int cdns_mhdp_firmware_init_imx8qm(struct cdns_mhdp_device *mhdp);
183 int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp);
184 +int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp);
185 +void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp);
186 #endif /* CDNS_MHDP_IMX_H_ */
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