git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From a9108b0712bf018dc69020864b21485b71b17dfc Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Sun, 30 Jul 2023 09:41:12 +0200
   4 Subject: [PATCH 3/4] net: dsa: qca8k: move qca8xxx hol fixup to separate
   5  function
   6
   7 Move qca8xxx hol fixup to separate function to tidy things up and to
   8 permit using a more efficent loop in future patch.
   9
  10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  11 Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
  12 Link: https://lore.kernel.org/r/20230730074113.21889-4-ansuelsmth@gmail.com
  13 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  14 ---
  15  drivers/net/dsa/qca/qca8k-8xxx.c | 78 +++++++++++++++++---------------
  16  1 file changed, 42 insertions(+), 36 deletions(-)
  17
  18 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
  19 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
  20 @@ -1784,6 +1784,46 @@ static int qca8k_connect_tag_protocol(st
  21         return 0;
  22  }
  23
  24 +static void qca8k_setup_hol_fixup(struct qca8k_priv *priv, int port)
  25 +{
  26 +       u32 mask;
  27 +
  28 +       switch (port) {
  29 +       /* The 2 CPU port and port 5 requires some different
  30 +        * priority than any other ports.
  31 +        */
  32 +       case 0:
  33 +       case 5:
  34 +       case 6:
  35 +               mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
  36 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
  37 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
  38 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
  39 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
  40 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
  41 +                       QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
  42 +               break;
  43 +       default:
  44 +               mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
  45 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
  46 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
  47 +                       QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
  48 +                       QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
  49 +       }
  50 +       regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask);
  51 +
  52 +       mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
  53 +              QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
  54 +              QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
  55 +              QCA8K_PORT_HOL_CTRL1_WRED_EN;
  56 +       regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port),
  57 +                          QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
  58 +                          QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
  59 +                          QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
  60 +                          QCA8K_PORT_HOL_CTRL1_WRED_EN,
  61 +                          mask);
  62 +}
  63 +
  64  static int
  65  qca8k_setup(struct dsa_switch *ds)
  66  {
  67 @@ -1919,42 +1959,8 @@ qca8k_setup(struct dsa_switch *ds)
  68                  * missing settings to improve switch stability under load condition.
  69                  * This problem is limited to qca8337 and other qca8k switch are not affected.
  70                  */
  71 -               if (priv->switch_id == QCA8K_ID_QCA8337) {
  72 -                       switch (i) {
  73 -                       /* The 2 CPU port and port 5 requires some different
  74 -                        * priority than any other ports.
  75 -                        */
  76 -                       case 0:
  77 -                       case 5:
  78 -                       case 6:
  79 -                               mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
  80 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
  81 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
  82 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
  83 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
  84 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
  85 -                                       QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
  86 -                               break;
  87 -                       default:
  88 -                               mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
  89 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
  90 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
  91 -                                       QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
  92 -                                       QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
  93 -                       }
  94 -                       qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
  95 -
  96 -                       mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
  97 -                       QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
  98 -                       QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
  99 -                       QCA8K_PORT_HOL_CTRL1_WRED_EN;
 100 -                       qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
 101 -                                 QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
 102 -                                 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
 103 -                                 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
 104 -                                 QCA8K_PORT_HOL_CTRL1_WRED_EN,
 105 -                                 mask);
 106 -               }
 107 +               if (priv->switch_id == QCA8K_ID_QCA8337)
 108 +                       qca8k_setup_hol_fixup(priv, i);
 109         }
 110
 111         /* Special GLOBAL_FC_THRESH value are needed for ar8327 switch */