git.openwrt.org Git - openwrt/staging/981213.git/blob

   1 From 38a8553b0a22ed54f014d8402fedd268b529175c Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Thu, 10 Feb 2022 10:48:59 +0100
   4 Subject: [PATCH 2/2] clk: ralink: make system controller node a reset provider
   5
   6 MT7621 system controller node is already providing the clocks for the whole
   7 system but must also serve as a reset provider. Hence, add reset controller
   8 related code to the clock driver itself. To get resets properly ready for
   9 the rest of the world we need to move platform driver initialization process
  10 to 'arch_initcall'.
  11
  12 CC: Philipp Zabel <p.zabel@pengutronix.de>
  13 Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
  14 Acked-by: Stephen Boyd <sboyd@kernel.org>
  15 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  16 Link: https://lore.kernel.org/r/20220210094859.927868-3-sergio.paracuellos@gmail.com
  17 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  18 ---
  19  drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++++++++++-
  20  1 file changed, 91 insertions(+), 1 deletion(-)
  21
  22 --- a/drivers/clk/ralink/clk-mt7621.c
  23 +++ b/drivers/clk/ralink/clk-mt7621.c
  24 @@ -11,14 +11,17 @@
  25  #include <linux/mfd/syscon.h>
  26  #include <linux/platform_device.h>
  27  #include <linux/regmap.h>
  28 +#include <linux/reset-controller.h>
  29  #include <linux/slab.h>
  30  #include <dt-bindings/clock/mt7621-clk.h>
  31 +#include <dt-bindings/reset/mt7621-reset.h>
  32
  33  /* Configuration registers */
  34  #define SYSC_REG_SYSTEM_CONFIG0         0x10
  35  #define SYSC_REG_SYSTEM_CONFIG1         0x14
  36  #define SYSC_REG_CLKCFG0               0x2c
  37  #define SYSC_REG_CLKCFG1               0x30
  38 +#define SYSC_REG_RESET_CTRL            0x34
  39  #define SYSC_REG_CUR_CLK_STS           0x44
  40  #define MEMC_REG_CPU_PLL               0x648
  41
  42 @@ -398,6 +401,82 @@ free_clk_priv:
  43  }
  44  CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
  45
  46 +struct mt7621_rst {
  47 +       struct reset_controller_dev rcdev;
  48 +       struct regmap *sysc;
  49 +};
  50 +
  51 +static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
  52 +{
  53 +       return container_of(dev, struct mt7621_rst, rcdev);
  54 +}
  55 +
  56 +static int mt7621_assert_device(struct reset_controller_dev *rcdev,
  57 +                               unsigned long id)
  58 +{
  59 +       struct mt7621_rst *data = to_mt7621_rst(rcdev);
  60 +       struct regmap *sysc = data->sysc;
  61 +
  62 +       return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
  63 +}
  64 +
  65 +static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
  66 +                                 unsigned long id)
  67 +{
  68 +       struct mt7621_rst *data = to_mt7621_rst(rcdev);
  69 +       struct regmap *sysc = data->sysc;
  70 +
  71 +       return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
  72 +}
  73 +
  74 +static int mt7621_reset_device(struct reset_controller_dev *rcdev,
  75 +                              unsigned long id)
  76 +{
  77 +       int ret;
  78 +
  79 +       ret = mt7621_assert_device(rcdev, id);
  80 +       if (ret < 0)
  81 +               return ret;
  82 +
  83 +       return mt7621_deassert_device(rcdev, id);
  84 +}
  85 +
  86 +static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
  87 +                           const struct of_phandle_args *reset_spec)
  88 +{
  89 +       unsigned long id = reset_spec->args[0];
  90 +
  91 +       if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
  92 +               return -EINVAL;
  93 +
  94 +       return id;
  95 +}
  96 +
  97 +static const struct reset_control_ops reset_ops = {
  98 +       .reset = mt7621_reset_device,
  99 +       .assert = mt7621_assert_device,
 100 +       .deassert = mt7621_deassert_device
 101 +};
 102 +
 103 +static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
 104 +{
 105 +       struct mt7621_rst *rst_data;
 106 +
 107 +       rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
 108 +       if (!rst_data)
 109 +               return -ENOMEM;
 110 +
 111 +       rst_data->sysc = sysc;
 112 +       rst_data->rcdev.ops = &reset_ops;
 113 +       rst_data->rcdev.owner = THIS_MODULE;
 114 +       rst_data->rcdev.nr_resets = 32;
 115 +       rst_data->rcdev.of_reset_n_cells = 1;
 116 +       rst_data->rcdev.of_xlate = mt7621_rst_xlate;
 117 +       rst_data->rcdev.of_node = dev_of_node(dev);
 118 +
 119 +       return devm_reset_controller_register(dev, &rst_data->rcdev);
 120 +}
 121 +
 122  static int mt7621_clk_probe(struct platform_device *pdev)
 123  {
 124         struct device_node *np = pdev->dev.of_node;
 125 @@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platf
 126                 return ret;
 127         }
 128
 129 +       ret = mt7621_reset_init(dev, priv->sysc);
 130 +       if (ret) {
 131 +               dev_err(dev, "Could not init reset controller\n");
 132 +               return ret;
 133 +       }
 134 +
 135         count = ARRAY_SIZE(mt7621_clks_base) +
 136                 ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
 137         clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
 138 @@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk
 139                 .of_match_table = mt7621_clk_of_match,
 140         },
 141  };
 142 -builtin_platform_driver(mt7621_clk_driver);
 143 +
 144 +static int __init mt7621_clk_reset_init(void)
 145 +{
 146 +       return platform_driver_register(&mt7621_clk_driver);
 147 +}
 148 +arch_initcall(mt7621_clk_reset_init);