git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 From feeef118fda562cf9081edef8ad464d89db070f4 Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Tue, 27 Sep 2022 22:12:18 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq6018: move ARMv8 timer out of SoC node
   5
   6 The ARM timer is usually considered not part of SoC node, just like
   7 other ARM designed blocks (PMU, PSCI).  This fixes dtbs_check warning:
   8
   9 arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dtb: soc: timer: {'compatible': ['arm,armv8-timer'], 'interrupts': [[1, 2, 3848], [1, 3, 3848], [1, 4, 3848], [1, 1, 3848]]} should not be valid under {'type': 'object'}
  10         From schema: dtschema/schemas/simple-bus.yaml
  11
  12 Signed-off-by: Robert Marko <robimarko@gmail.com>
  13 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  14 Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
  15 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  16 Link: https://lore.kernel.org/r/20220927201218.1264506-2-robimarko@gmail.com
  17 ---
  18  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 ++++++++--------
  19  1 file changed, 8 insertions(+), 8 deletions(-)
  20
  21 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  22 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  23 @@ -510,14 +510,6 @@
  24                         clock-names = "xo";
  25                 };
  26
  27 -               timer {
  28 -                       compatible = "arm,armv8-timer";
  29 -                       interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  30 -                                    <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  31 -                                    <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  32 -                                    <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  33 -               };
  34 -
  35                 timer@b120000 {
  36                         #address-cells = <1>;
  37                         #size-cells = <1>;
  38 @@ -769,6 +761,14 @@
  39                 };
  40         };
  41
  42 +       timer {
  43 +               compatible = "arm,armv8-timer";
  44 +               interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  45 +                            <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  46 +                            <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  47 +                            <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  48 +       };
  49 +
  50         wcss: wcss-smp2p {
  51                 compatible = "qcom,smp2p";
  52                 qcom,smem = <435>, <428>;