git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From dae2475df84cd77c6f7245984869897c0eb0f84e Mon Sep 17 00:00:00 2001
   2 From: Wen He <wen.he_1@nxp.com>
   3 Date: Tue, 10 Sep 2019 15:01:00 +0800
   4 Subject: [PATCH] drm/arm/mali-dp: Add display QoS interface configuration for
   5  Mali DP500
   6
   7 Configure the display Quality of service (QoS) levels priority if the
   8 optional property node "arm,malidp-aqros-value" is defined in DTS file.
   9
  10 QoS signaling using AQROS and AWQOS AXI interface signals, the AQROS is
  11 driven from the "RQOS" register, so needed to program the RQOS register
  12 to avoid the high resolutions flicker issue on the LS1028A platform.
  13
  14 Signed-off-by: Wen He <wen.he_1@nxp.com>
  15 ---
  16  drivers/gpu/drm/arm/malidp_drv.c  |  6 ++++++
  17  drivers/gpu/drm/arm/malidp_hw.c   |  9 +++++++++
  18  drivers/gpu/drm/arm/malidp_hw.h   |  3 +++
  19  drivers/gpu/drm/arm/malidp_regs.h | 10 ++++++++++
  20  4 files changed, 28 insertions(+)
  21
  22 --- a/drivers/gpu/drm/arm/malidp_drv.c
  23 +++ b/drivers/gpu/drm/arm/malidp_drv.c
  24 @@ -817,6 +817,12 @@ static int malidp_bind(struct device *de
  25
  26         malidp->core_id = version;
  27
  28 +       ret = of_property_read_u32(dev->of_node,
  29 +                                       "arm,malidp-arqos-value",
  30 +                                       &hwdev->arqos_value);
  31 +       if (ret)
  32 +               hwdev->arqos_value = 0x0;
  33 +
  34         /* set the number of lines used for output of RGB data */
  35         ret = of_property_read_u8_array(dev->of_node,
  36                                         "arm,malidp-output-port-lines",
  37 --- a/drivers/gpu/drm/arm/malidp_hw.c
  38 +++ b/drivers/gpu/drm/arm/malidp_hw.c
  39 @@ -379,6 +379,15 @@ static void malidp500_modeset(struct mal
  40                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  41         else
  42                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
  43 +
  44 +       /*
  45 +        * Program the RQoS register to avoid high resolutions flicker
  46 +        * issue on the LS1028A.
  47 +        */
  48 +       if (hwdev->arqos_value) {
  49 +               val = hwdev->arqos_value;
  50 +               malidp_hw_setbits(hwdev, val, MALIDP500_RQOS_QUALITY);
  51 +       }
  52  }
  53
  54  int malidp_format_get_bpp(u32 fmt)
  55 --- a/drivers/gpu/drm/arm/malidp_hw.h
  56 +++ b/drivers/gpu/drm/arm/malidp_hw.h
  57 @@ -251,6 +251,9 @@ struct malidp_hw_device {
  58
  59         /* size of memory used for rotating layers, up to two banks available */
  60         u32 rotation_memory[2];
  61 +
  62 +       /* priority level of RQOS register used for driven the ARQOS signal */
  63 +       u32 arqos_value;
  64  };
  65
  66  static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
  67 --- a/drivers/gpu/drm/arm/malidp_regs.h
  68 +++ b/drivers/gpu/drm/arm/malidp_regs.h
  69 @@ -210,6 +210,16 @@
  70  #define MALIDP500_CONFIG_VALID         0x00f00
  71  #define MALIDP500_CONFIG_ID            0x00fd4
  72
  73 +/*
  74 + * The quality of service (QoS) register on the DP500. RQOS register values
  75 + * are driven by the ARQOS signal, using AXI transacations, dependent on the
  76 + * FIFO input level.
  77 + * The RQOS register can also set QoS levels for:
  78 + *    - RED_ARQOS   @ A 4-bit signal value for close to underflow conditions
  79 + *    - GREEN_ARQOS @ A 4-bit signal value for normal conditions
  80 + */
  81 +#define MALIDP500_RQOS_QUALITY          0x00500
  82 +
  83  /* register offsets and bits specific to DP550/DP650 */
  84  #define MALIDP550_ADDR_SPACE_SIZE      0x10000
  85  #define MALIDP550_DE_CONTROL           0x00010