git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 7f6c8bdfe020c45c398c01b417460e3319476606 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 29 Jul 2022 10:43:39 +0800
   4 Subject: [PATCH 22/31] clk: mediatek: add CLK_BYPASS_XTAL flag to allow
   5  bypassing searching clock parent of xtal clock
   6
   7 The mtk clock framework in u-boot uses array index for searching clock
   8 parent (kernel uses strings for search), so we need to specify a special
   9 clock with ID=0 for CLK_XTAL in u-boot.
  10
  11 In the mt7622/mt7629 clock tree, the clocks with ID=0 never call
  12 mtk_topckgen_get_mux_rate, adn return xtal clock directly. This what we
  13 expected.
  14
  15 However for newer chips, they may have some clocks with ID=0 not
  16 representing the xtal clock and still needs mtk_topckgen_get_mux_rate be
  17 called. Current logic will make entire clock driver not working.
  18
  19 This patch adds a flag to indicate that whether a clock driver needs clocks
  20 with ID=0 to call mtk_topckgen_get_mux_rate.
  21
  22 Reviewed-by: Simon Glass <sjg@chromium.org>
  23 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  24 ---
  25  drivers/clk/mediatek/clk-mtk.c | 5 ++++-
  26  drivers/clk/mediatek/clk-mtk.h | 6 ++++++
  27  2 files changed, 10 insertions(+), 1 deletion(-)
  28
  29 --- a/drivers/clk/mediatek/clk-mtk.c
  30 +++ b/drivers/clk/mediatek/clk-mtk.c
  31 @@ -314,12 +314,15 @@ static ulong mtk_topckgen_get_mux_rate(s
  32         struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
  33         const struct mtk_composite *mux = &priv->tree->muxes[off];
  34         u32 index;
  35 +       u32 flag = 0;
  36
  37         index = readl(priv->base + mux->mux_reg);
  38         index &= mux->mux_mask << mux->mux_shift;
  39         index = index >> mux->mux_shift;
  40
  41 -       if (mux->parent[index])
  42 +       if (mux->parent[index] == CLK_XTAL && priv->tree->flags & CLK_BYPASS_XTAL)
  43 +               flag = 1;
  44 +       if (mux->parent[index] > 0 || flag == 1)
  45                 return mtk_clk_find_parent_rate(clk, mux->parent[index],
  46                                                 NULL);
  47
  48 --- a/drivers/clk/mediatek/clk-mtk.h
  49 +++ b/drivers/clk/mediatek/clk-mtk.h
  50 @@ -11,6 +11,11 @@
  51  #define CLK_XTAL                       0
  52  #define MHZ                            (1000 * 1000)
  53
  54 +/* flags in struct mtk_clk_tree */
  55 +
  56 +/* clk id == 0 doesn't mean it's xtal clk */
  57 +#define CLK_BYPASS_XTAL                        BIT(0)
  58 +
  59  #define HAVE_RST_BAR                   BIT(0)
  60  #define CLK_DOMAIN_SCPSYS              BIT(0)
  61  #define CLK_MUX_SETCLR_UPD             BIT(1)
  62 @@ -197,6 +202,7 @@ struct mtk_clk_tree {
  63         const struct mtk_fixed_clk *fclks;
  64         const struct mtk_fixed_factor *fdivs;
  65         const struct mtk_composite *muxes;
  66 +       u32 flags;
  67  };
  68
  69  struct mtk_clk_priv {