git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 3b162fdf85d89829d58bbee2d7d79987aceaa595 Mon Sep 17 00:00:00 2001
   2 From: Boris Brezillon <boris.brezillon@free-electrons.com>
   3 Date: Fri, 2 Dec 2016 14:48:07 +0100
   4 Subject: [PATCH] drm/vc4: Fix ->clock_select setting for the VEC encoder
   5
   6 PV_CONTROL_CLK_SELECT_VEC is actually 2 and not 0. Fix the definition and
   7 rework the vc4_set_crtc_possible_masks() to cover the full range of the
   8 PV_CONTROL_CLK_SELECT field.
   9
  10 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 (cherry picked from commit ab8df60e3a3b68420d0d4477c5f07c00fbfb078b)
  13 ---
  14  drivers/gpu/drm/vc4/vc4_crtc.c | 38 +++++++++++++++++++++++---------------
  15  drivers/gpu/drm/vc4/vc4_drv.h  |  1 +
  16  drivers/gpu/drm/vc4/vc4_regs.h |  3 ++-
  17  3 files changed, 26 insertions(+), 16 deletions(-)
  18
  19 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  20 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  21 @@ -83,8 +83,7 @@ struct vc4_crtc_data {
  22         /* Which channel of the HVS this pixelvalve sources from. */
  23         int hvs_channel;
  24
  25 -       enum vc4_encoder_type encoder0_type;
  26 -       enum vc4_encoder_type encoder1_type;
  27 +       enum vc4_encoder_type encoder_types[4];
  28  };
  29
  30  #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
  31 @@ -880,20 +879,26 @@ static const struct drm_crtc_helper_func
  32
  33  static const struct vc4_crtc_data pv0_data = {
  34         .hvs_channel = 0,
  35 -       .encoder0_type = VC4_ENCODER_TYPE_DSI0,
  36 -       .encoder1_type = VC4_ENCODER_TYPE_DPI,
  37 +       .encoder_types = {
  38 +               [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
  39 +               [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
  40 +       },
  41  };
  42
  43  static const struct vc4_crtc_data pv1_data = {
  44         .hvs_channel = 2,
  45 -       .encoder0_type = VC4_ENCODER_TYPE_DSI1,
  46 -       .encoder1_type = VC4_ENCODER_TYPE_SMI,
  47 +       .encoder_types = {
  48 +               [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
  49 +               [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
  50 +       },
  51  };
  52
  53  static const struct vc4_crtc_data pv2_data = {
  54         .hvs_channel = 1,
  55 -       .encoder0_type = VC4_ENCODER_TYPE_VEC,
  56 -       .encoder1_type = VC4_ENCODER_TYPE_HDMI,
  57 +       .encoder_types = {
  58 +               [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
  59 +               [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
  60 +       },
  61  };
  62
  63  static const struct of_device_id vc4_crtc_dt_match[] = {
  64 @@ -907,17 +912,20 @@ static void vc4_set_crtc_possible_masks(
  65                                         struct drm_crtc *crtc)
  66  {
  67         struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
  68 +       const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
  69 +       const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
  70         struct drm_encoder *encoder;
  71
  72         drm_for_each_encoder(encoder, drm) {
  73                 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
  74 +               int i;
  75
  76 -               if (vc4_encoder->type == vc4_crtc->data->encoder0_type) {
  77 -                       vc4_encoder->clock_select = 0;
  78 -                       encoder->possible_crtcs |= drm_crtc_mask(crtc);
  79 -               } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) {
  80 -                       vc4_encoder->clock_select = 1;
  81 -                       encoder->possible_crtcs |= drm_crtc_mask(crtc);
  82 +               for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
  83 +                       if (vc4_encoder->type == encoder_types[i]) {
  84 +                               vc4_encoder->clock_select = i;
  85 +                               encoder->possible_crtcs |= drm_crtc_mask(crtc);
  86 +                               break;
  87 +                       }
  88                 }
  89         }
  90  }
  91 --- a/drivers/gpu/drm/vc4/vc4_drv.h
  92 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
  93 @@ -197,6 +197,7 @@ to_vc4_plane(struct drm_plane *plane)
  94  }
  95
  96  enum vc4_encoder_type {
  97 +       VC4_ENCODER_TYPE_NONE,
  98         VC4_ENCODER_TYPE_HDMI,
  99         VC4_ENCODER_TYPE_VEC,
 100         VC4_ENCODER_TYPE_DSI0,
 101 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 102 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 103 @@ -177,8 +177,9 @@
 104  # define PV_CONTROL_WAIT_HSTART                        BIT(12)
 105  # define PV_CONTROL_PIXEL_REP_MASK             VC4_MASK(5, 4)
 106  # define PV_CONTROL_PIXEL_REP_SHIFT            4
 107 -# define PV_CONTROL_CLK_SELECT_DSI_VEC         0
 108 +# define PV_CONTROL_CLK_SELECT_DSI             0
 109  # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI    1
 110 +# define PV_CONTROL_CLK_SELECT_VEC             2
 111  # define PV_CONTROL_CLK_SELECT_MASK            VC4_MASK(3, 2)
 112  # define PV_CONTROL_CLK_SELECT_SHIFT           2
 113  # define PV_CONTROL_FIFO_CLR                   BIT(1)