git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 961c38974fa5b34d6232d7485120e4392d279ab4 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Wed, 13 Jan 2021 12:14:06 +0100
   4 Subject: [PATCH] arm64: dts: broadcom: bcm4908: describe internal switch
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 BCM4908 has internal switch with 5 GPHYs. Ports 0 - 3 are always
  10 connected to the internal PHYs. Remaining ports depend on device setup.
  11
  12 Asus GT-AC5300 has an extra switch with its PHYs accessible using the
  13 internal MDIO.
  14
  15 CPU port and Ethernet interface remain to be documented.
  16
  17 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  18 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  19 ---
  20  .../bcm4908/bcm4908-asus-gt-ac5300.dts        | 51 +++++++++++
  21  .../boot/dts/broadcom/bcm4908/bcm4908.dtsi    | 85 ++++++++++++++++++-
  22  2 files changed, 135 insertions(+), 1 deletion(-)
  23
  24 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
  25 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908-asus-gt-ac5300.dts
  26 @@ -44,6 +44,57 @@
  27         };
  28  };
  29
  30 +&ports {
  31 +       port@0 {
  32 +               label = "lan2";
  33 +       };
  34 +
  35 +       port@1 {
  36 +               label = "lan1";
  37 +       };
  38 +
  39 +       port@2 {
  40 +               label = "lan6";
  41 +       };
  42 +
  43 +       port@3 {
  44 +               label = "lan5";
  45 +       };
  46 +
  47 +       /* External BCM53134S switch */
  48 +       port@7 {
  49 +               label = "sw";
  50 +               reg = <7>;
  51 +
  52 +               fixed-link {
  53 +                       speed = <1000>;
  54 +                       full-duplex;
  55 +               };
  56 +       };
  57 +};
  58 +
  59 +&mdio {
  60 +       /* lan8 */
  61 +       phy@0 {
  62 +               reg = <0>;
  63 +       };
  64 +
  65 +       /* lan7 */
  66 +       phy@1 {
  67 +               reg = <1>;
  68 +       };
  69 +
  70 +       /* lan4 */
  71 +       phy@2 {
  72 +               reg = <2>;
  73 +       };
  74 +
  75 +       /* lan3 */
  76 +       phy@3 {
  77 +               reg = <3>;
  78 +       };
  79 +};
  80 +
  81  &nandcs {
  82         nand-ecc-strength = <4>;
  83         nand-ecc-step-size = <512>;
  84 --- a/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
  85 +++ b/arch/arm64/boot/dts/broadcom/bcm4908/bcm4908.dtsi
  86 @@ -108,7 +108,7 @@
  87                 compatible = "simple-bus";
  88                 #address-cells = <1>;
  89                 #size-cells = <1>;
  90 -               ranges = <0x00 0x00 0x80000000 0x10000>;
  91 +               ranges = <0x00 0x00 0x80000000 0xd0000>;
  92
  93                 usb@c300 {
  94                         compatible = "generic-ehci";
  95 @@ -130,6 +130,89 @@
  96                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  97                         status = "disabled";
  98                 };
  99 +
 100 +               switch@80000 {
 101 +                       compatible = "simple-bus";
 102 +                       #size-cells = <1>;
 103 +                       #address-cells = <1>;
 104 +                       ranges = <0 0x80000 0x50000>;
 105 +
 106 +                       switch@0 {
 107 +                               compatible = "brcm,bcm4908-switch";
 108 +                               reg = <0x0 0x40000>,
 109 +                                     <0x40000 0x110>,
 110 +                                     <0x40340 0x30>,
 111 +                                     <0x40380 0x30>,
 112 +                                     <0x40600 0x34>,
 113 +                                     <0x40800 0x208>;
 114 +                               reg-names = "core", "reg", "intrl2_0",
 115 +                                           "intrl2_1", "fcb", "acb";
 116 +                               interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 117 +                                            <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 118 +                               brcm,num-gphy = <5>;
 119 +                               brcm,num-rgmii-ports = <2>;
 120 +
 121 +                               #address-cells = <1>;
 122 +                               #size-cells = <0>;
 123 +
 124 +                               ports: ports {
 125 +                                       #address-cells = <1>;
 126 +                                       #size-cells = <0>;
 127 +
 128 +                                       port@0 {
 129 +                                               reg = <0>;
 130 +                                               phy-mode = "internal";
 131 +                                               phy-handle = <&phy8>;
 132 +                                       };
 133 +
 134 +                                       port@1 {
 135 +                                               reg = <1>;
 136 +                                               phy-mode = "internal";
 137 +                                               phy-handle = <&phy9>;
 138 +                                       };
 139 +
 140 +                                       port@2 {
 141 +                                               reg = <2>;
 142 +                                               phy-mode = "internal";
 143 +                                               phy-handle = <&phy10>;
 144 +                                       };
 145 +
 146 +                                       port@3 {
 147 +                                               reg = <3>;
 148 +                                               phy-mode = "internal";
 149 +                                               phy-handle = <&phy11>;
 150 +                                       };
 151 +                               };
 152 +                       };
 153 +
 154 +                       mdio: mdio@405c0 {
 155 +                               compatible = "brcm,unimac-mdio";
 156 +                               reg = <0x405c0 0x8>;
 157 +                               reg-names = "mdio";
 158 +                               #size-cells = <1>;
 159 +                               #address-cells = <0>;
 160 +
 161 +                               phy8: phy@8 {
 162 +                                       reg = <8>;
 163 +                               };
 164 +
 165 +                               phy9: phy@9 {
 166 +                                       reg = <9>;
 167 +                               };
 168 +
 169 +                               phy10: phy@a {
 170 +                                       reg = <10>;
 171 +                               };
 172 +
 173 +                               phy11: phy@b {
 174 +                                       reg = <11>;
 175 +                               };
 176 +
 177 +                               phy12: phy@c {
 178 +                                       reg = <12>;
 179 +                               };
 180 +                       };
 181 +               };
 182         };
 183
 184         bus@ff800000 {