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1 From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
2 From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
3 Date: Fri, 20 Jan 2023 10:20:52 +0100
4 Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
5 clocks enabled
6
7 Instead of calling clk_prepare_enable() on a bunch of clocks at probe
8 time, set the CLK_IS_CRITICAL flag to the same as these are required
9 to be always on, and this is the right way of achieving that.
10
11 Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
12 Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
13 Reviewed-by: Miles Chen <miles.chen@mediatek.com>
14 Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
15 Tested-by: Mingming Su <mingming.su@mediatek.com>
16 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
17 ---
18 drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
19 1 file changed, 24 insertions(+), 22 deletions(-)
20
21 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
22 +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
23 @@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
24 MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
25 f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
26 0x1C0, 10),
27 - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
28 - 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
29 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
30 + f_26m_adc_parents, 0x020, 0x024, 0x028,
31 + 24, 1, 31, 0x1C0, 11,
32 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
33 /* CLK_CFG_3 */
34 - MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
35 - dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
36 - 0x1C0, 12),
37 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
38 - 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
39 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
40 - 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
41 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
42 + dramc_md32_parents, 0x030, 0x034, 0x038,
43 + 0, 1, 7, 0x1C0, 12,
44 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
45 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
46 + sysaxi_parents, 0x030, 0x034, 0x038,
47 + 8, 2, 15, 0x1C0, 13,
48 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
49 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
50 + sysapb_parents, 0x030, 0x034, 0x038,
51 + 16, 2, 23, 0x1C0, 14,
52 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
53 MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
54 arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
55 31, 0x1C0, 15),
56 @@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
57 MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
58 sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
59 0x1C0, 21),
60 - MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
61 - sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
62 - 0x1C0, 22),
63 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
64 + sgm_reg_parents, 0x050, 0x054, 0x058,
65 + 16, 1, 23, 0x1C0, 22,
66 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
67 MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
68 0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
69 /* CLK_CFG_6 */
70 @@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
71 f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
72 0x1C0, 27),
73 /* CLK_CFG_7 */
74 - MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
75 - f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
76 - 0x1C0, 28),
77 + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
78 + f_26m_adc_parents, 0x070, 0x074, 0x078,
79 + 0, 1, 7, 0x1C0, 28,
80 + CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
81 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
82 0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
83 MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
84 @@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
85 ARRAY_SIZE(top_muxes), node,
86 &mt7986_clk_lock, clk_data);
87
88 - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
89 - clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
90 - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
91 - clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
92 - clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
93 - clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
94 -
95 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
96
97 if (r) {
Staging tree of David Bauer