git.openwrt.org Git - openwrt/staging/nbd.git/blob

   1 From f61d5d294f12df46380ef1af5f55abe8e8f45500 Mon Sep 17 00:00:00 2001
   2 From: Dom Cobley <popcornmix@gmail.com>
   3 Date: Tue, 24 Oct 2023 16:20:42 +0100
   4 Subject: [PATCH 0713/1085] drm/vc4: crtc: Support odd horizontal timings on
   5  BCM2712
   6
   7 BCM2711 runs pixelvalve at two pixels per clock cycle which results
   8 in an unfortunate limitation that odd horizontal timings are not
   9 possible. This is apparent on the standard DMT mode of 1366x768@60
  10 which cannot be driven with correct timing.
  11
  12 BCM2712 defaults to the same behaviour, but has a mode to support
  13 odd timings. While internally it still runs at two pixels per clock,
  14 setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally
  15 to behave as it is one pixel per clock.
  16
  17 Switching to this mode fixes 1366x768@60 mode, and other custom
  18 resultions with odd horizontal timings.
  19
  20 Signed-off-by: Dom Cobley <popcornmix@gmail.com>
  21 ---
  22  drivers/gpu/drm/vc4/vc4_crtc.c | 12 ++++--------
  23  drivers/gpu/drm/vc4/vc4_hdmi.c |  4 ++--
  24  drivers/gpu/drm/vc4/vc4_regs.h |  1 +
  25  3 files changed, 7 insertions(+), 10 deletions(-)
  26
  27 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  28 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  29 @@ -399,12 +399,6 @@ static void vc4_crtc_config_pv(struct dr
  30
  31         vc4_crtc_pixelvalve_reset(crtc);
  32
  33 -       /*
  34 -        * NOTE: The BCM2712 has a H_OTE (Horizontal Odd Timing Enable)
  35 -        * bit that, when set, will allow to specify the timings in
  36 -        * pixels instead of cycles, thus allowing to specify odd
  37 -        * timings.
  38 -        */
  39         CRTC_WRITE(PV_HORZA,
  40                    VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
  41                                  PV_HORZA_HBP) |
  42 @@ -449,6 +443,7 @@ static void vc4_crtc_config_pv(struct dr
  43                  */
  44                 CRTC_WRITE(PV_V_CONTROL,
  45                            PV_VCONTROL_CONTINUOUS |
  46 +                          (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
  47                            (is_dsi ? PV_VCONTROL_DSI : 0) |
  48                            PV_VCONTROL_INTERLACE |
  49                            (odd_field_first
  50 @@ -460,6 +455,7 @@ static void vc4_crtc_config_pv(struct dr
  51         } else {
  52                 CRTC_WRITE(PV_V_CONTROL,
  53                            PV_VCONTROL_CONTINUOUS |
  54 +                          (vc4->gen >= VC4_GEN_6 ? PV_VCONTROL_ODD_TIMING : 0) |
  55                            (is_dsi ? PV_VCONTROL_DSI : 0));
  56                 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
  57         }
  58 @@ -1332,7 +1328,7 @@ const struct vc4_pv_data bcm2712_pv0_dat
  59                 .hvs_output = 0,
  60         },
  61         .fifo_depth = 64,
  62 -       .pixels_per_clock = 2,
  63 +       .pixels_per_clock = 1,
  64         .encoder_types = {
  65                 [0] = VC4_ENCODER_TYPE_HDMI0,
  66         },
  67 @@ -1345,7 +1341,7 @@ const struct vc4_pv_data bcm2712_pv1_dat
  68                 .hvs_output = 1,
  69         },
  70         .fifo_depth = 64,
  71 -       .pixels_per_clock = 2,
  72 +       .pixels_per_clock = 1,
  73         .encoder_types = {
  74                 [0] = VC4_ENCODER_TYPE_HDMI1,
  75         },
  76 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  77 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  78 @@ -3912,7 +3912,7 @@ static const struct vc4_hdmi_variant bcm
  79                 PHY_LANE_2,
  80                 PHY_LANE_CK,
  81         },
  82 -       .unsupported_odd_h_timings      = true,
  83 +       .unsupported_odd_h_timings      = false,
  84         .external_irq_controller        = true,
  85
  86         .init_resources         = vc5_hdmi_init_resources,
  87 @@ -3939,7 +3939,7 @@ static const struct vc4_hdmi_variant bcm
  88                 PHY_LANE_2,
  89                 PHY_LANE_CK,
  90         },
  91 -       .unsupported_odd_h_timings      = true,
  92 +       .unsupported_odd_h_timings      = false,
  93         .external_irq_controller        = true,
  94
  95         .init_resources         = vc5_hdmi_init_resources,
  96 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  97 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  98 @@ -155,6 +155,7 @@
  99  # define PV_CONTROL_EN                         BIT(0)
 100
 101  #define PV_V_CONTROL                           0x04
 102 +# define PV_VCONTROL_ODD_TIMING                        BIT(29)
 103  # define PV_VCONTROL_ODD_DELAY_MASK            VC4_MASK(22, 6)
 104  # define PV_VCONTROL_ODD_DELAY_SHIFT           6
 105  # define PV_VCONTROL_ODD_FIRST                 BIT(5)