bdc3f9989712363195b87e2f6607ed6162382ddc
[openwrt/staging/stintel.git] /
1 From 10073a205df269abcbd9c3fbc690a813827107ef Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Tue, 28 Jun 2016 11:35:21 -0700
4 Subject: watchdog: qcom: configure BARK time in addition to BITE time
5
6 For certain parts and some versions of TZ, TZ will reset the chip
7 when a BARK is triggered even though it was not configured here. So
8 by default let's configure this BARK time as well.
9
10 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
11 Reviewed-by: Guenter Roeck <linux@roeck-us.net>
12 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
13 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
14 Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
15 ---
16 drivers/watchdog/qcom-wdt.c | 5 +++++
17 1 file changed, 5 insertions(+)
18
19 --- a/drivers/watchdog/qcom-wdt.c
20 +++ b/drivers/watchdog/qcom-wdt.c
21 @@ -24,6 +24,7 @@ enum wdt_reg {
22 WDT_RST,
23 WDT_EN,
24 WDT_STS,
25 + WDT_BARK_TIME,
26 WDT_BITE_TIME,
27 };
28
29 @@ -31,6 +32,7 @@ static const u32 reg_offset_data_apcs_tm
30 [WDT_RST] = 0x38,
31 [WDT_EN] = 0x40,
32 [WDT_STS] = 0x44,
33 + [WDT_BARK_TIME] = 0x4C,
34 [WDT_BITE_TIME] = 0x5C,
35 };
36
37 @@ -38,6 +40,7 @@ static const u32 reg_offset_data_kpss[]
38 [WDT_RST] = 0x4,
39 [WDT_EN] = 0x8,
40 [WDT_STS] = 0xC,
41 + [WDT_BARK_TIME] = 0x10,
42 [WDT_BITE_TIME] = 0x14,
43 };
44
45 @@ -66,6 +69,7 @@ static int qcom_wdt_start(struct watchdo
46
47 writel(0, wdt_addr(wdt, WDT_EN));
48 writel(1, wdt_addr(wdt, WDT_RST));
49 + writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BARK_TIME));
50 writel(wdd->timeout * wdt->rate, wdt_addr(wdt, WDT_BITE_TIME));
51 writel(1, wdt_addr(wdt, WDT_EN));
52 return 0;
53 @@ -108,6 +112,7 @@ static int qcom_wdt_restart(struct watch
54
55 writel(0, wdt_addr(wdt, WDT_EN));
56 writel(1, wdt_addr(wdt, WDT_RST));
57 + writel(timeout, wdt_addr(wdt, WDT_BARK_TIME));
58 writel(timeout, wdt_addr(wdt, WDT_BITE_TIME));
59 writel(1, wdt_addr(wdt, WDT_EN));
60