git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 8e28947dacb52352807fed71d70355a18bf416c5 Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@nxp.com>
   3 Date: Thu, 8 Feb 2018 14:38:35 +0800
   4 Subject: [PATCH] MLK-17566: ASoC: fsl_sai: fix register definition
   5
   6 The register definition is not completed for SAI support
   7 8 transmit data register and 8 receive data register.
   8
   9 Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
  10 Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
  11 ---
  12  sound/soc/fsl/fsl_sai.c | 24 ++++++++++++++++++++++++
  13  sound/soc/fsl/fsl_sai.h | 12 ++++++++++++
  14  2 files changed, 36 insertions(+)
  15
  16 --- a/sound/soc/fsl/fsl_sai.c
  17 +++ b/sound/soc/fsl/fsl_sai.c
  18 @@ -964,6 +964,12 @@ static struct reg_default fsl_sai_v3_reg
  19         {FSL_SAI_TCR5(8), 0},
  20         {FSL_SAI_TDR0, 0},
  21         {FSL_SAI_TDR1, 0},
  22 +       {FSL_SAI_TDR2, 0},
  23 +       {FSL_SAI_TDR3, 0},
  24 +       {FSL_SAI_TDR4, 0},
  25 +       {FSL_SAI_TDR5, 0},
  26 +       {FSL_SAI_TDR6, 0},
  27 +       {FSL_SAI_TDR7, 0},
  28         {FSL_SAI_TMR,  0},
  29         {FSL_SAI_RCR1(8), 0},
  30         {FSL_SAI_RCR2(8), 0},
  31 @@ -996,6 +1002,12 @@ static bool fsl_sai_readable_reg(struct
  32         case FSL_SAI_TMR:
  33         case FSL_SAI_RDR0:
  34         case FSL_SAI_RDR1:
  35 +       case FSL_SAI_RDR2:
  36 +       case FSL_SAI_RDR3:
  37 +       case FSL_SAI_RDR4:
  38 +       case FSL_SAI_RDR5:
  39 +       case FSL_SAI_RDR6:
  40 +       case FSL_SAI_RDR7:
  41         case FSL_SAI_RFR0:
  42         case FSL_SAI_RFR1:
  43         case FSL_SAI_RFR2:
  44 @@ -1038,6 +1050,12 @@ static bool fsl_sai_volatile_reg(struct
  45         case FSL_SAI_RFR7:
  46         case FSL_SAI_RDR0:
  47         case FSL_SAI_RDR1:
  48 +       case FSL_SAI_RDR2:
  49 +       case FSL_SAI_RDR3:
  50 +       case FSL_SAI_RDR4:
  51 +       case FSL_SAI_RDR5:
  52 +       case FSL_SAI_RDR6:
  53 +       case FSL_SAI_RDR7:
  54                 return true;
  55         default:
  56                 return false;
  57 @@ -1058,6 +1076,12 @@ static bool fsl_sai_writeable_reg(struct
  58         switch (reg) {
  59         case FSL_SAI_TDR0:
  60         case FSL_SAI_TDR1:
  61 +       case FSL_SAI_TDR2:
  62 +       case FSL_SAI_TDR3:
  63 +       case FSL_SAI_TDR4:
  64 +       case FSL_SAI_TDR5:
  65 +       case FSL_SAI_TDR6:
  66 +       case FSL_SAI_TDR7:
  67         case FSL_SAI_TMR:
  68         case FSL_SAI_RMR:
  69                 return true;
  70 --- a/sound/soc/fsl/fsl_sai.h
  71 +++ b/sound/soc/fsl/fsl_sai.h
  72 @@ -25,6 +25,12 @@
  73  #define FSL_SAI_TCR5(offset) (0x14 + offset) /* SAI Transmit Configuration 5 */
  74  #define FSL_SAI_TDR0    0x20 /* SAI Transmit Data */
  75  #define FSL_SAI_TDR1    0x24 /* SAI Transmit Data */
  76 +#define FSL_SAI_TDR2    0x28 /* SAI Transmit Data */
  77 +#define FSL_SAI_TDR3    0x2C /* SAI Transmit Data */
  78 +#define FSL_SAI_TDR4    0x30 /* SAI Transmit Data */
  79 +#define FSL_SAI_TDR5    0x34 /* SAI Transmit Data */
  80 +#define FSL_SAI_TDR6    0x38 /* SAI Transmit Data */
  81 +#define FSL_SAI_TDR7    0x3C /* SAI Transmit Data */
  82  #define FSL_SAI_TFR0    0x40 /* SAI Transmit FIFO */
  83  #define FSL_SAI_TFR1    0x44 /* SAI Transmit FIFO */
  84  #define FSL_SAI_TFR2    0x48 /* SAI Transmit FIFO */
  85 @@ -43,6 +49,12 @@
  86  #define FSL_SAI_RCR5(offset) (0x94 + offset) /* SAI Receive Configuration 5 */
  87  #define FSL_SAI_RDR0    0xa0 /* SAI Receive Data */
  88  #define FSL_SAI_RDR1    0xa4 /* SAI Receive Data */
  89 +#define FSL_SAI_RDR2    0xa8 /* SAI Receive Data */
  90 +#define FSL_SAI_RDR3    0xac /* SAI Receive Data */
  91 +#define FSL_SAI_RDR4    0xb0 /* SAI Receive Data */
  92 +#define FSL_SAI_RDR5    0xb4 /* SAI Receive Data */
  93 +#define FSL_SAI_RDR6    0xb8 /* SAI Receive Data */
  94 +#define FSL_SAI_RDR7    0xbc /* SAI Receive Data */
  95  #define FSL_SAI_RFR0    0xc0 /* SAI Receive FIFO */
  96  #define FSL_SAI_RFR1    0xc4 /* SAI Receive FIFO */
  97  #define FSL_SAI_RFR2    0xc8 /* SAI Receive FIFO */