projects / openwrt / staging / xback.git / blob
? search:


bc34aa33a9f2a0d88d738548a217d86ff684dfdf
[openwrt/staging/xback.git] /
1 From: Lorenzo Bianconi <lorenzo@kernel.org>
2 Date: Mon, 18 Sep 2023 12:29:06 +0200
3 Subject: [PATCH] net: ethernet: mtk_wed: do not configure rx offload if not
4 supported
5
6 Check if rx offload is supported running mtk_wed_get_rx_capa routine
7 before configuring it. This is a preliminary patch to introduce Wireless
8 Ethernet Dispatcher (WED) support for MT7988 SoC.
9
10 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
11 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
13 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
14 ---
15
16 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
17 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
18 @@ -605,7 +605,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
19 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
20 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
21
22 - if (mtk_wed_is_v1(dev->hw))
23 + if (!mtk_wed_get_rx_capa(dev))
24 return;
25
26 wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
27 @@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
28 {
29 if (mtk_wed_is_v1(dev->hw)) {
30 wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
31 - } else {
32 - mtk_wed_bus_init(dev);
33 -
34 - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
35 - wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
36 - wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
37 - wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
38 - wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
39 - wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
40 + return;
41 }
42 +
43 + mtk_wed_bus_init(dev);
44 +
45 + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
46 + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
47 + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
48 + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
49 +
50 + if (!mtk_wed_get_rx_capa(dev))
51 + return;
52 +
53 + wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
54 + wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
55 }
56
57 static void
58 @@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
59 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
60 } else {
61 wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
62 - /* rx hw init */
63 - wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
64 - MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
65 - MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
66 - wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
67 -
68 - mtk_wed_rx_buffer_hw_init(dev);
69 - mtk_wed_rro_hw_init(dev);
70 - mtk_wed_route_qm_hw_init(dev);
71 + if (mtk_wed_get_rx_capa(dev)) {
72 + /* rx hw init */
73 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
74 + MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
75 + MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
76 + wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
77 +
78 + mtk_wed_rx_buffer_hw_init(dev);
79 + mtk_wed_rro_hw_init(dev);
80 + mtk_wed_route_qm_hw_init(dev);
81 + }
82 }
83
84 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
85 @@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
86
87 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
88 } else {
89 - wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
90 - GENMASK(1, 0));
91 /* initail tx interrupt trigger */
92 wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
93 MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
94 @@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
95 FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
96 dev->wlan.txfree_tbit));
97
98 - wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
99 - MTK_WED_WPDMA_INT_CTRL_RX0_EN |
100 - MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
101 - MTK_WED_WPDMA_INT_CTRL_RX1_EN |
102 - MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
103 - FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
104 - dev->wlan.rx_tbit[0]) |
105 - FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
106 - dev->wlan.rx_tbit[1]));
107 + if (mtk_wed_get_rx_capa(dev)) {
108 + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
109 + MTK_WED_WPDMA_INT_CTRL_RX0_EN |
110 + MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
111 + MTK_WED_WPDMA_INT_CTRL_RX1_EN |
112 + MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
113 + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
114 + dev->wlan.rx_tbit[0]) |
115 + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
116 + dev->wlan.rx_tbit[1]));
117 +
118 + wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
119 + GENMASK(1, 0));
120 + }
121
122 wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
123 wed_set(dev, MTK_WED_WDMA_INT_CTRL,
124 @@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
125 static void
126 mtk_wed_dma_enable(struct mtk_wed_device *dev)
127 {
128 + int i;
129 +
130 wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
131
132 wed_set(dev, MTK_WED_GLO_CFG,
133 @@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
134 if (mtk_wed_is_v1(dev->hw)) {
135 wdma_set(dev, MTK_WDMA_GLO_CFG,
136 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
137 - } else {
138 - int i;
139 + return;
140 + }
141
142 - wed_set(dev, MTK_WED_WPDMA_CTRL,
143 - MTK_WED_WPDMA_CTRL_SDL1_FIXED);
144 + wed_set(dev, MTK_WED_WPDMA_CTRL,
145 + MTK_WED_WPDMA_CTRL_SDL1_FIXED);
146 + wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
147 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
148 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
149 + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
150 + MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
151 + MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
152
153 - wed_set(dev, MTK_WED_WDMA_GLO_CFG,
154 - MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
155 - MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
156 + if (!mtk_wed_get_rx_capa(dev))
157 + return;
158
159 - wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
160 - MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
161 - MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
162 -
163 - wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
164 - MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
165 - MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
166 + wed_set(dev, MTK_WED_WDMA_GLO_CFG,
167 + MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
168 + MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
169
170 - wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
171 - MTK_WED_WPDMA_RX_D_RX_DRV_EN |
172 - FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
173 - FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
174 - 0x2));
175 + wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
176 + MTK_WED_WPDMA_RX_D_RX_DRV_EN |
177 + FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
178 + FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
179 + 0x2));
180
181 - for (i = 0; i < MTK_WED_RX_QUEUES; i++)
182 - mtk_wed_check_wfdma_rx_fill(dev, i);
183 - }
184 + for (i = 0; i < MTK_WED_RX_QUEUES; i++)
185 + mtk_wed_check_wfdma_rx_fill(dev, i);
186 }
187
188 static void
189 @@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
190
191 val |= BIT(0) | (BIT(1) * !!dev->hw->index);
192 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
193 - } else {
194 + } else if (mtk_wed_get_rx_capa(dev)) {
195 /* driver set mid ready and only once */
196 wed_w32(dev, MTK_WED_EXT_INT_MASK1,
197 MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
198 @@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
199
200 if (mtk_wed_rro_cfg(dev))
201 return;
202 -
203 }
204
205 mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
206 @@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
207 }
208
209 mtk_wed_hw_init_early(dev);
210 - if (mtk_wed_is_v1(hw)) {
211 + if (mtk_wed_is_v1(hw))
212 regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
213 BIT(hw->index), 0);
214 - } else {
215 + else
216 dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
217 +
218 + if (mtk_wed_get_rx_capa(dev))
219 ret = mtk_wed_wo_init(hw);
220 - }
221 out:
222 if (ret) {
223 dev_err(dev->hw->dev, "failed to attach wed device\n");
224 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
225 +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
226 @@ -207,7 +207,7 @@ int mtk_wed_mcu_msg_update(struct mtk_we
227 {
228 struct mtk_wed_wo *wo = dev->hw->wed_wo;
229
230 - if (mtk_wed_is_v1(dev->hw))
231 + if (!mtk_wed_get_rx_capa(dev))
232 return 0;
233
234 if (WARN_ON(!wo))
Staging tree of Koen Vandeputte