git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 23711cabe122ef55bcb2e5c3e3835b5a2a688fc0 Mon Sep 17 00:00:00 2001
   2 From: Varadarajan Narayanan <quic_varada@quicinc.com>
   3 Date: Tue, 30 Apr 2024 12:12:13 +0530
   4 Subject: [PATCH] clk: qcom: ipq9574: Use icc-clk for enabling NoC related
   5  clocks
   6
   7 Use the icc-clk framework to enable few clocks to be able to
   8 create paths and use the peripherals connected on those NoCs.
   9
  10 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
  11 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  12 Link: https://lore.kernel.org/r/20240430064214.2030013-6-quic_varada@quicinc.com
  13 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  14 ---
  15  drivers/clk/qcom/Kconfig       |  2 ++
  16  drivers/clk/qcom/gcc-ipq9574.c | 33 +++++++++++++++++++++++++++++++++
  17  2 files changed, 35 insertions(+)
  18
  19 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
  20 index 1231eae51556..11ae28430dad 100644
  21 --- a/drivers/clk/qcom/Kconfig
  22 +++ b/drivers/clk/qcom/Kconfig
  23 @@ -14,6 +14,8 @@ menuconfig COMMON_CLK_QCOM
  24         select RATIONAL
  25         select REGMAP_MMIO
  26         select RESET_CONTROLLER
  27 +       select INTERCONNECT
  28 +       select INTERCONNECT_CLK
  29
  30  if COMMON_CLK_QCOM
  31
  32 diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
  33 index bc3e17f34295..f08a447370bd 100644
  34 --- a/drivers/clk/qcom/gcc-ipq9574.c
  35 +++ b/drivers/clk/qcom/gcc-ipq9574.c
  36 @@ -4,6 +4,8 @@
  37   */
  38
  39  #include <linux/clk-provider.h>
  40 +#include <linux/interconnect-clk.h>
  41 +#include <linux/interconnect-provider.h>
  42  #include <linux/kernel.h>
  43  #include <linux/module.h>
  44  #include <linux/of.h>
  45 @@ -12,6 +14,7 @@
  46
  47  #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  48  #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
  49 +#include <dt-bindings/interconnect/qcom,ipq9574.h>
  50
  51  #include "clk-alpha-pll.h"
  52  #include "clk-branch.h"
  53 @@ -4377,6 +4380,32 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = {
  54         [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
  55  };
  56
  57 +#define IPQ_APPS_ID                    9574    /* some unique value */
  58 +
  59 +static struct qcom_icc_hws_data icc_ipq9574_hws[] = {
  60 +       { MASTER_ANOC_PCIE0, SLAVE_ANOC_PCIE0, GCC_ANOC_PCIE0_1LANE_M_CLK },
  61 +       { MASTER_SNOC_PCIE0, SLAVE_SNOC_PCIE0, GCC_SNOC_PCIE0_1LANE_S_CLK },
  62 +       { MASTER_ANOC_PCIE1, SLAVE_ANOC_PCIE1, GCC_ANOC_PCIE1_1LANE_M_CLK },
  63 +       { MASTER_SNOC_PCIE1, SLAVE_SNOC_PCIE1, GCC_SNOC_PCIE1_1LANE_S_CLK },
  64 +       { MASTER_ANOC_PCIE2, SLAVE_ANOC_PCIE2, GCC_ANOC_PCIE2_2LANE_M_CLK },
  65 +       { MASTER_SNOC_PCIE2, SLAVE_SNOC_PCIE2, GCC_SNOC_PCIE2_2LANE_S_CLK },
  66 +       { MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
  67 +       { MASTER_SNOC_PCIE3, SLAVE_SNOC_PCIE3, GCC_SNOC_PCIE3_2LANE_S_CLK },
  68 +       { MASTER_USB, SLAVE_USB, GCC_SNOC_USB_CLK },
  69 +       { MASTER_USB_AXI, SLAVE_USB_AXI, GCC_ANOC_USB_AXI_CLK },
  70 +       { MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
  71 +       { MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
  72 +       { MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
  73 +       { MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
  74 +       { MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
  75 +       { MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
  76 +       { MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
  77 +       { MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
  78 +       { MASTER_MEM_NOC_NSSNOC, SLAVE_MEM_NOC_NSSNOC, GCC_MEM_NOC_NSSNOC_CLK },
  79 +       { MASTER_NSSNOC_MEMNOC, SLAVE_NSSNOC_MEMNOC, GCC_NSSNOC_MEMNOC_CLK },
  80 +       { MASTER_NSSNOC_MEM_NOC_1, SLAVE_NSSNOC_MEM_NOC_1, GCC_NSSNOC_MEM_NOC_1_CLK },
  81 +};
  82 +
  83  static const struct of_device_id gcc_ipq9574_match_table[] = {
  84         { .compatible = "qcom,ipq9574-gcc" },
  85         { }
  86 @@ -4399,6 +4428,9 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = {
  87         .num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
  88         .clk_hws = gcc_ipq9574_hws,
  89         .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
  90 +       .icc_hws = icc_ipq9574_hws,
  91 +       .num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws),
  92 +       .icc_first_node_id = IPQ_APPS_ID,
  93  };
  94
  95  static int gcc_ipq9574_probe(struct platform_device *pdev)
  96 @@ -4411,6 +4443,7 @@ static struct platform_driver gcc_ipq9574_driver = {
  97         .driver = {
  98                 .name   = "qcom,gcc-ipq9574",
  99                 .of_match_table = gcc_ipq9574_match_table,
 100 +               .sync_state = icc_sync_state,
 101         },
 102  };
 103
 104 --
 105 2.45.2
 106