git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 5209e1b8f78fd1184f25cf19cf0daa58f4ad6599 Mon Sep 17 00:00:00 2001
   2 From: Boris Brezillon <boris.brezillon@free-electrons.com>
   3 Date: Thu, 1 Dec 2016 22:00:20 +0100
   4 Subject: [PATCH] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC
   5  clock
   6
   7 The VEC clock requires needs to be set at exactly 108MHz. Allow rate
   8 change propagation on PLLH_AUX to match this requirement wihtout
   9 impacting other IPs (PLLH is currently only used by the HDMI encoder,
  10 which cannot be enabled when the VEC encoder is enabled).
  11
  12 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  13 Reviewed-by: Eric Anholt <eric@anholt.net>
  14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  15 (cherry picked from commit d86d46af84855403c00018be1c3e7bc190f2a6cd)
  16 ---
  17  drivers/clk/bcm/clk-bcm2835.c | 7 ++++++-
  18  1 file changed, 6 insertions(+), 1 deletion(-)
  19
  20 --- a/drivers/clk/bcm/clk-bcm2835.c
  21 +++ b/drivers/clk/bcm/clk-bcm2835.c
  22 @@ -1876,7 +1876,12 @@ static const struct bcm2835_clk_desc clk
  23                 .ctl_reg = CM_VECCTL,
  24                 .div_reg = CM_VECDIV,
  25                 .int_bits = 4,
  26 -               .frac_bits = 0),
  27 +               .frac_bits = 0,
  28 +               /*
  29 +                * Allow rate change propagation only on PLLH_AUX which is
  30 +                * assigned index 7 in the parent array.
  31 +                */
  32 +               .set_rate_parent = BIT(7)),
  33
  34         /* dsi clocks */
  35         [BCM2835_CLOCK_DSI0E]   = REGISTER_PER_CLK(