projects / openwrt / staging / ansuel.git / blob
? search:


ba72a796ee3f74d9f7e0b87adf51b7b7d80cf3bc
[openwrt/staging/ansuel.git] /
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sat, 5 Feb 2022 17:56:08 +0100
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for Wireless
4 Ethernet Dispatch (WED)
5
6 The Wireless Ethernet Dispatch subsystem on the MT7622 SoC can be
7 configured to intercept and handle access to the DMA queues and
8 PCIe interrupts for a MT7615/MT7915 wireless card.
9 It can manage the internal WDMA (Wireless DMA) controller, which allows
10 ethernet packets to be passed from the packet switch engine (PSE) to the
11 wireless card, bypassing the CPU entirely.
12 This can be used to implement hardware flow offloading from ethernet to
13 WLAN.
14
15 Signed-off-by: Felix Fietkau <nbd@nbd.name>
16 ---
17 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.c
18 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed.h
19 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
20 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_ops.c
21 create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_regs.h
22 create mode 100644 include/linux/soc/mediatek/mtk_wed.h
23
24 --- a/drivers/net/ethernet/mediatek/Kconfig
25 +++ b/drivers/net/ethernet/mediatek/Kconfig
26 @@ -7,6 +7,10 @@ config NET_VENDOR_MEDIATEK
27
28 if NET_VENDOR_MEDIATEK
29
30 +config NET_MEDIATEK_SOC_WED
31 + depends on ARCH_MEDIATEK || COMPILE_TEST
32 + def_bool NET_MEDIATEK_SOC != n
33 +
34 config NET_MEDIATEK_SOC
35 tristate "MediaTek SoC Gigabit Ethernet support"
36 depends on NET_DSA || !NET_DSA
37 --- a/drivers/net/ethernet/mediatek/Makefile
38 +++ b/drivers/net/ethernet/mediatek/Makefile
39 @@ -5,4 +5,9 @@
40
41 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
42 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
43 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o
44 +ifdef CONFIG_DEBUG_FS
45 +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
46 +endif
47 +obj-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_ops.o
48 obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
49 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
50 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
51 @@ -24,6 +24,7 @@
52 #include <net/dsa.h>
53
54 #include "mtk_eth_soc.h"
55 +#include "mtk_wed.h"
56
57 static int mtk_msg_level = -1;
58 module_param_named(msg_level, mtk_msg_level, int, 0);
59 @@ -3205,6 +3206,22 @@ static int mtk_probe(struct platform_dev
60 }
61 }
62
63 + for (i = 0;; i++) {
64 + struct device_node *np = of_parse_phandle(pdev->dev.of_node,
65 + "mediatek,wed", i);
66 + static const u32 wdma_regs[] = {
67 + MTK_WDMA0_BASE,
68 + MTK_WDMA1_BASE
69 + };
70 + void __iomem *wdma;
71 +
72 + if (!np || i >= ARRAY_SIZE(wdma_regs))
73 + break;
74 +
75 + wdma = eth->base + wdma_regs[i];
76 + mtk_wed_add_hw(np, eth, wdma, i);
77 + }
78 +
79 for (i = 0; i < 3; i++) {
80 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT) && i > 0)
81 eth->irq[i] = eth->irq[0];
82 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
83 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
84 @@ -295,6 +295,9 @@
85 #define MTK_GDM1_TX_GPCNT 0x2438
86 #define MTK_STAT_OFFSET 0x40
87
88 +#define MTK_WDMA0_BASE 0x2800
89 +#define MTK_WDMA1_BASE 0x2c00
90 +
91 /* QDMA descriptor txd4 */
92 #define TX_DMA_CHKSUM (0x7 << 29)
93 #define TX_DMA_TSO BIT(28)
94 --- /dev/null
95 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
96 @@ -0,0 +1,875 @@
97 +// SPDX-License-Identifier: GPL-2.0-only
98 +/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
99 +
100 +#include <linux/kernel.h>
101 +#include <linux/slab.h>
102 +#include <linux/module.h>
103 +#include <linux/bitfield.h>
104 +#include <linux/dma-mapping.h>
105 +#include <linux/skbuff.h>
106 +#include <linux/of_platform.h>
107 +#include <linux/of_address.h>
108 +#include <linux/mfd/syscon.h>
109 +#include <linux/debugfs.h>
110 +#include <linux/soc/mediatek/mtk_wed.h>
111 +#include "mtk_eth_soc.h"
112 +#include "mtk_wed_regs.h"
113 +#include "mtk_wed.h"
114 +#include "mtk_ppe.h"
115 +
116 +#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
117 +
118 +#define MTK_WED_PKT_SIZE 1900
119 +#define MTK_WED_BUF_SIZE 2048
120 +#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
121 +
122 +#define MTK_WED_TX_RING_SIZE 2048
123 +#define MTK_WED_WDMA_RING_SIZE 1024
124 +
125 +static struct mtk_wed_hw *hw_list[2];
126 +static DEFINE_MUTEX(hw_lock);
127 +
128 +static void
129 +wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
130 +{
131 + regmap_update_bits(dev->hw->regs, reg, mask | val, val);
132 +}
133 +
134 +static void
135 +wed_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
136 +{
137 + return wed_m32(dev, reg, 0, mask);
138 +}
139 +
140 +static void
141 +wed_clr(struct mtk_wed_device *dev, u32 reg, u32 mask)
142 +{
143 + return wed_m32(dev, reg, mask, 0);
144 +}
145 +
146 +static void
147 +wdma_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
148 +{
149 + wdma_w32(dev, reg, (wdma_r32(dev, reg) & ~mask) | val);
150 +}
151 +
152 +static void
153 +wdma_set(struct mtk_wed_device *dev, u32 reg, u32 mask)
154 +{
155 + wdma_m32(dev, reg, 0, mask);
156 +}
157 +
158 +static u32
159 +mtk_wed_read_reset(struct mtk_wed_device *dev)
160 +{
161 + return wed_r32(dev, MTK_WED_RESET);
162 +}
163 +
164 +static void
165 +mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
166 +{
167 + u32 status;
168 +
169 + wed_w32(dev, MTK_WED_RESET, mask);
170 + if (readx_poll_timeout(mtk_wed_read_reset, dev, status,
171 + !(status & mask), 0, 1000))
172 + WARN_ON_ONCE(1);
173 +}
174 +
175 +static struct mtk_wed_hw *
176 +mtk_wed_assign(struct mtk_wed_device *dev)
177 +{
178 + struct mtk_wed_hw *hw;
179 +
180 + hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
181 + if (!hw || hw->wed_dev)
182 + return NULL;
183 +
184 + hw->wed_dev = dev;
185 + return hw;
186 +}
187 +
188 +static int
189 +mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
190 +{
191 + struct mtk_wdma_desc *desc;
192 + dma_addr_t desc_phys;
193 + void **page_list;
194 + int token = dev->wlan.token_start;
195 + int ring_size;
196 + int n_pages;
197 + int i, page_idx;
198 +
199 + ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
200 + n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
201 +
202 + page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
203 + if (!page_list)
204 + return -ENOMEM;
205 +
206 + dev->buf_ring.size = ring_size;
207 + dev->buf_ring.pages = page_list;
208 +
209 + desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
210 + &desc_phys, GFP_KERNEL);
211 + if (!desc)
212 + return -ENOMEM;
213 +
214 + dev->buf_ring.desc = desc;
215 + dev->buf_ring.desc_phys = desc_phys;
216 +
217 + for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
218 + dma_addr_t page_phys, buf_phys;
219 + struct page *page;
220 + void *buf;
221 + int s;
222 +
223 + page = __dev_alloc_pages(GFP_KERNEL, 0);
224 + if (!page)
225 + return -ENOMEM;
226 +
227 + page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
228 + DMA_BIDIRECTIONAL);
229 + if (dma_mapping_error(dev->hw->dev, page_phys)) {
230 + __free_page(page);
231 + return -ENOMEM;
232 + }
233 +
234 + page_list[page_idx++] = page;
235 + dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
236 + DMA_BIDIRECTIONAL);
237 +
238 + buf = page_to_virt(page);
239 + buf_phys = page_phys;
240 +
241 + for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
242 + u32 txd_size;
243 +
244 + txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
245 +
246 + desc->buf0 = buf_phys;
247 + desc->buf1 = buf_phys + txd_size;
248 + desc->ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0,
249 + txd_size) |
250 + FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
251 + MTK_WED_BUF_SIZE - txd_size) |
252 + MTK_WDMA_DESC_CTRL_LAST_SEG1;
253 + desc->info = 0;
254 + desc++;
255 +
256 + buf += MTK_WED_BUF_SIZE;
257 + buf_phys += MTK_WED_BUF_SIZE;
258 + }
259 +
260 + dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
261 + DMA_BIDIRECTIONAL);
262 + }
263 +
264 + return 0;
265 +}
266 +
267 +static void
268 +mtk_wed_free_buffer(struct mtk_wed_device *dev)
269 +{
270 + struct mtk_wdma_desc *desc = dev->buf_ring.desc;
271 + void **page_list = dev->buf_ring.pages;
272 + int page_idx;
273 + int i;
274 +
275 + if (!page_list)
276 + return;
277 +
278 + if (!desc)
279 + goto free_pagelist;
280 +
281 + for (i = 0, page_idx = 0; i < dev->buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
282 + void *page = page_list[page_idx++];
283 +
284 + if (!page)
285 + break;
286 +
287 + dma_unmap_page(dev->hw->dev, desc[i].buf0,
288 + PAGE_SIZE, DMA_BIDIRECTIONAL);
289 + __free_page(page);
290 + }
291 +
292 + dma_free_coherent(dev->hw->dev, dev->buf_ring.size * sizeof(*desc),
293 + desc, dev->buf_ring.desc_phys);
294 +
295 +free_pagelist:
296 + kfree(page_list);
297 +}
298 +
299 +static void
300 +mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
301 +{
302 + if (!ring->desc)
303 + return;
304 +
305 + dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc),
306 + ring->desc, ring->desc_phys);
307 +}
308 +
309 +static void
310 +mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
311 +{
312 + int i;
313 +
314 + for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
315 + mtk_wed_free_ring(dev, &dev->tx_ring[i]);
316 + for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
317 + mtk_wed_free_ring(dev, &dev->tx_wdma[i]);
318 +}
319 +
320 +static void
321 +mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
322 +{
323 + u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
324 +
325 + if (!dev->hw->num_flows)
326 + mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
327 +
328 + wed_w32(dev, MTK_WED_EXT_INT_MASK, en ? mask : 0);
329 + wed_r32(dev, MTK_WED_EXT_INT_MASK);
330 +}
331 +
332 +static void
333 +mtk_wed_stop(struct mtk_wed_device *dev)
334 +{
335 + regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
336 + mtk_wed_set_ext_int(dev, false);
337 +
338 + wed_clr(dev, MTK_WED_CTRL,
339 + MTK_WED_CTRL_WDMA_INT_AGENT_EN |
340 + MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
341 + MTK_WED_CTRL_WED_TX_BM_EN |
342 + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
343 + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
344 + wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
345 + wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
346 + wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
347 + wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
348 +
349 + wed_clr(dev, MTK_WED_GLO_CFG,
350 + MTK_WED_GLO_CFG_TX_DMA_EN |
351 + MTK_WED_GLO_CFG_RX_DMA_EN);
352 + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
353 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
354 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
355 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
356 + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
357 +}
358 +
359 +static void
360 +mtk_wed_detach(struct mtk_wed_device *dev)
361 +{
362 + struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node;
363 + struct mtk_wed_hw *hw = dev->hw;
364 +
365 + mutex_lock(&hw_lock);
366 +
367 + mtk_wed_stop(dev);
368 +
369 + wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
370 + wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
371 +
372 + mtk_wed_reset(dev, MTK_WED_RESET_WED);
373 +
374 + mtk_wed_free_buffer(dev);
375 + mtk_wed_free_tx_rings(dev);
376 +
377 + if (of_dma_is_coherent(wlan_node))
378 + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
379 + BIT(hw->index), BIT(hw->index));
380 +
381 + if (!hw_list[!hw->index]->wed_dev &&
382 + hw->eth->dma_dev != hw->eth->dev)
383 + mtk_eth_set_dma_device(hw->eth, hw->eth->dev);
384 +
385 + memset(dev, 0, sizeof(*dev));
386 + module_put(THIS_MODULE);
387 +
388 + hw->wed_dev = NULL;
389 + mutex_unlock(&hw_lock);
390 +}
391 +
392 +static void
393 +mtk_wed_hw_init_early(struct mtk_wed_device *dev)
394 +{
395 + u32 mask, set;
396 + u32 offset;
397 +
398 + mtk_wed_stop(dev);
399 + mtk_wed_reset(dev, MTK_WED_RESET_WED);
400 +
401 + mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
402 + MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
403 + MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
404 + set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
405 + MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
406 + MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
407 + wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
408 +
409 + wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);
410 +
411 + offset = dev->hw->index ? 0x04000400 : 0;
412 + wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
413 + wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
414 +
415 + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));
416 + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
417 +}
418 +
419 +static void
420 +mtk_wed_hw_init(struct mtk_wed_device *dev)
421 +{
422 + if (dev->init_done)
423 + return;
424 +
425 + dev->init_done = true;
426 + mtk_wed_set_ext_int(dev, false);
427 + wed_w32(dev, MTK_WED_TX_BM_CTRL,
428 + MTK_WED_TX_BM_CTRL_PAUSE |
429 + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
430 + dev->buf_ring.size / 128) |
431 + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
432 + MTK_WED_TX_RING_SIZE / 256));
433 +
434 + wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
435 +
436 + wed_w32(dev, MTK_WED_TX_BM_TKID,
437 + FIELD_PREP(MTK_WED_TX_BM_TKID_START,
438 + dev->wlan.token_start) |
439 + FIELD_PREP(MTK_WED_TX_BM_TKID_END,
440 + dev->wlan.token_start + dev->wlan.nbuf - 1));
441 +
442 + wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
443 +
444 + wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
445 + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
446 + MTK_WED_TX_BM_DYN_THR_HI);
447 +
448 + mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
449 +
450 + wed_set(dev, MTK_WED_CTRL,
451 + MTK_WED_CTRL_WED_TX_BM_EN |
452 + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
453 +
454 + wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
455 +}
456 +
457 +static void
458 +mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size)
459 +{
460 + int i;
461 +
462 + for (i = 0; i < size; i++) {
463 + desc[i].buf0 = 0;
464 + desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
465 + desc[i].buf1 = 0;
466 + desc[i].info = 0;
467 + }
468 +}
469 +
470 +static u32
471 +mtk_wed_check_busy(struct mtk_wed_device *dev)
472 +{
473 + if (wed_r32(dev, MTK_WED_GLO_CFG) & MTK_WED_GLO_CFG_TX_DMA_BUSY)
474 + return true;
475 +
476 + if (wed_r32(dev, MTK_WED_WPDMA_GLO_CFG) &
477 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY)
478 + return true;
479 +
480 + if (wed_r32(dev, MTK_WED_CTRL) & MTK_WED_CTRL_WDMA_INT_AGENT_BUSY)
481 + return true;
482 +
483 + if (wed_r32(dev, MTK_WED_WDMA_GLO_CFG) &
484 + MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
485 + return true;
486 +
487 + if (wdma_r32(dev, MTK_WDMA_GLO_CFG) &
488 + MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY)
489 + return true;
490 +
491 + if (wed_r32(dev, MTK_WED_CTRL) &
492 + (MTK_WED_CTRL_WED_TX_BM_BUSY | MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY))
493 + return true;
494 +
495 + return false;
496 +}
497 +
498 +static int
499 +mtk_wed_poll_busy(struct mtk_wed_device *dev)
500 +{
501 + int sleep = 15000;
502 + int timeout = 100 * sleep;
503 + u32 val;
504 +
505 + return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
506 + timeout, false, dev);
507 +}
508 +
509 +static void
510 +mtk_wed_reset_dma(struct mtk_wed_device *dev)
511 +{
512 + bool busy = false;
513 + u32 val;
514 + int i;
515 +
516 + for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) {
517 + struct mtk_wdma_desc *desc = dev->tx_ring[i].desc;
518 +
519 + if (!desc)
520 + continue;
521 +
522 + mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE);
523 + }
524 +
525 + if (mtk_wed_poll_busy(dev))
526 + busy = mtk_wed_check_busy(dev);
527 +
528 + if (busy) {
529 + mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
530 + } else {
531 + wed_w32(dev, MTK_WED_RESET_IDX,
532 + MTK_WED_RESET_IDX_TX |
533 + MTK_WED_RESET_IDX_RX);
534 + wed_w32(dev, MTK_WED_RESET_IDX, 0);
535 + }
536 +
537 + wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
538 + wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
539 +
540 + if (busy) {
541 + mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
542 + mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
543 + } else {
544 + wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
545 + MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
546 + wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
547 +
548 + wed_set(dev, MTK_WED_WDMA_GLO_CFG,
549 + MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
550 +
551 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
552 + MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
553 + }
554 +
555 + for (i = 0; i < 100; i++) {
556 + val = wed_r32(dev, MTK_WED_TX_BM_INTF);
557 + if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
558 + break;
559 + }
560 +
561 + mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
562 + mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
563 +
564 + if (busy) {
565 + mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
566 + mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
567 + mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
568 + } else {
569 + wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
570 + MTK_WED_WPDMA_RESET_IDX_TX |
571 + MTK_WED_WPDMA_RESET_IDX_RX);
572 + wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
573 + }
574 +
575 +}
576 +
577 +static int
578 +mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
579 + int size)
580 +{
581 + ring->desc = dma_alloc_coherent(dev->hw->dev,
582 + size * sizeof(*ring->desc),
583 + &ring->desc_phys, GFP_KERNEL);
584 + if (!ring->desc)
585 + return -ENOMEM;
586 +
587 + ring->size = size;
588 + mtk_wed_ring_reset(ring->desc, size);
589 +
590 + return 0;
591 +}
592 +
593 +static int
594 +mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)
595 +{
596 + struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
597 +
598 + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE))
599 + return -ENOMEM;
600 +
601 + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
602 + wdma->desc_phys);
603 + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
604 + size);
605 + wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
606 +
607 + wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
608 + wdma->desc_phys);
609 + wed_w32(dev, MTK_WED_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_COUNT,
610 + size);
611 +
612 + return 0;
613 +}
614 +
615 +static void
616 +mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
617 +{
618 + u32 wdma_mask;
619 + u32 val;
620 + int i;
621 +
622 + for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
623 + if (!dev->tx_wdma[i].desc)
624 + mtk_wed_wdma_ring_setup(dev, i, 16);
625 +
626 + wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
627 +
628 + mtk_wed_hw_init(dev);
629 +
630 + wed_set(dev, MTK_WED_CTRL,
631 + MTK_WED_CTRL_WDMA_INT_AGENT_EN |
632 + MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
633 + MTK_WED_CTRL_WED_TX_BM_EN |
634 + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
635 +
636 + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);
637 +
638 + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
639 + MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
640 + MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
641 +
642 + wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
643 + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
644 +
645 + wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
646 + wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
647 +
648 + wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
649 + wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
650 +
651 + wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
652 + wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
653 +
654 + wed_set(dev, MTK_WED_GLO_CFG,
655 + MTK_WED_GLO_CFG_TX_DMA_EN |
656 + MTK_WED_GLO_CFG_RX_DMA_EN);
657 + wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
658 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
659 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
660 + wed_set(dev, MTK_WED_WDMA_GLO_CFG,
661 + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
662 +
663 + mtk_wed_set_ext_int(dev, true);
664 + val = dev->wlan.wpdma_phys |
665 + MTK_PCIE_MIRROR_MAP_EN |
666 + FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);
667 +
668 + if (dev->hw->index)
669 + val |= BIT(1);
670 + val |= BIT(0);
671 + regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
672 +
673 + dev->running = true;
674 +}
675 +
676 +static int
677 +mtk_wed_attach(struct mtk_wed_device *dev)
678 + __releases(RCU)
679 +{
680 + struct mtk_wed_hw *hw;
681 + int ret = 0;
682 +
683 + RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
684 + "mtk_wed_attach without holding the RCU read lock");
685 +
686 + if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 ||
687 + !try_module_get(THIS_MODULE))
688 + ret = -ENODEV;
689 +
690 + rcu_read_unlock();
691 +
692 + if (ret)
693 + return ret;
694 +
695 + mutex_lock(&hw_lock);
696 +
697 + hw = mtk_wed_assign(dev);
698 + if (!hw) {
699 + module_put(THIS_MODULE);
700 + ret = -ENODEV;
701 + goto out;
702 + }
703 +
704 + dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index);
705 +
706 + dev->hw = hw;
707 + dev->dev = hw->dev;
708 + dev->irq = hw->irq;
709 + dev->wdma_idx = hw->index;
710 +
711 + if (hw->eth->dma_dev == hw->eth->dev &&
712 + of_dma_is_coherent(hw->eth->dev->of_node))
713 + mtk_eth_set_dma_device(hw->eth, hw->dev);
714 +
715 + ret = mtk_wed_buffer_alloc(dev);
716 + if (ret) {
717 + mtk_wed_detach(dev);
718 + goto out;
719 + }
720 +
721 + mtk_wed_hw_init_early(dev);
722 + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0);
723 +
724 +out:
725 + mutex_unlock(&hw_lock);
726 +
727 + return ret;
728 +}
729 +
730 +static int
731 +mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
732 +{
733 + struct mtk_wed_ring *ring = &dev->tx_ring[idx];
734 +
735 + /*
736 + * Tx ring redirection:
737 + * Instead of configuring the WLAN PDMA TX ring directly, the WLAN
738 + * driver allocated DMA ring gets configured into WED MTK_WED_RING_TX(n)
739 + * registers.
740 + *
741 + * WED driver posts its own DMA ring as WLAN PDMA TX and configures it
742 + * into MTK_WED_WPDMA_RING_TX(n) registers.
743 + * It gets filled with packets picked up from WED TX ring and from
744 + * WDMA RX.
745 + */
746 +
747 + BUG_ON(idx > ARRAY_SIZE(dev->tx_ring));
748 +
749 + if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE))
750 + return -ENOMEM;
751 +
752 + if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
753 + return -ENOMEM;
754 +
755 + ring->reg_base = MTK_WED_RING_TX(idx);
756 + ring->wpdma = regs;
757 +
758 + /* WED -> WPDMA */
759 + wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
760 + wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
761 + wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_CPU_IDX, 0);
762 +
763 + wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
764 + ring->desc_phys);
765 + wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
766 + MTK_WED_TX_RING_SIZE);
767 + wed_w32(dev, MTK_WED_WPDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
768 +
769 + return 0;
770 +}
771 +
772 +static int
773 +mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
774 +{
775 + struct mtk_wed_ring *ring = &dev->txfree_ring;
776 + int i;
777 +
778 + /*
779 + * For txfree event handling, the same DMA ring is shared between WED
780 + * and WLAN. The WLAN driver accesses the ring index registers through
781 + * WED
782 + */
783 + ring->reg_base = MTK_WED_RING_RX(1);
784 + ring->wpdma = regs;
785 +
786 + for (i = 0; i < 12; i += 4) {
787 + u32 val = readl(regs + i);
788 +
789 + wed_w32(dev, MTK_WED_RING_RX(1) + i, val);
790 + wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val);
791 + }
792 +
793 + return 0;
794 +}
795 +
796 +static u32
797 +mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
798 +{
799 + u32 val;
800 +
801 + val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
802 + wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
803 + val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
804 + if (!dev->hw->num_flows)
805 + val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
806 + if (val && net_ratelimit())
807 + pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
808 +
809 + val = wed_r32(dev, MTK_WED_INT_STATUS);
810 + val &= mask;
811 + wed_w32(dev, MTK_WED_INT_STATUS, val); /* ACK */
812 +
813 + return val;
814 +}
815 +
816 +static void
817 +mtk_wed_irq_set_mask(struct mtk_wed_device *dev, u32 mask)
818 +{
819 + if (!dev->running)
820 + return;
821 +
822 + mtk_wed_set_ext_int(dev, !!mask);
823 + wed_w32(dev, MTK_WED_INT_MASK, mask);
824 +}
825 +
826 +int mtk_wed_flow_add(int index)
827 +{
828 + struct mtk_wed_hw *hw = hw_list[index];
829 + int ret;
830 +
831 + if (!hw || !hw->wed_dev)
832 + return -ENODEV;
833 +
834 + if (hw->num_flows) {
835 + hw->num_flows++;
836 + return 0;
837 + }
838 +
839 + mutex_lock(&hw_lock);
840 + if (!hw->wed_dev) {
841 + ret = -ENODEV;
842 + goto out;
843 + }
844 +
845 + ret = hw->wed_dev->wlan.offload_enable(hw->wed_dev);
846 + if (!ret)
847 + hw->num_flows++;
848 + mtk_wed_set_ext_int(hw->wed_dev, true);
849 +
850 +out:
851 + mutex_unlock(&hw_lock);
852 +
853 + return ret;
854 +}
855 +
856 +void mtk_wed_flow_remove(int index)
857 +{
858 + struct mtk_wed_hw *hw = hw_list[index];
859 +
860 + if (!hw)
861 + return;
862 +
863 + if (--hw->num_flows)
864 + return;
865 +
866 + mutex_lock(&hw_lock);
867 + if (!hw->wed_dev)
868 + goto out;
869 +
870 + hw->wed_dev->wlan.offload_disable(hw->wed_dev);
871 + mtk_wed_set_ext_int(hw->wed_dev, true);
872 +
873 +out:
874 + mutex_unlock(&hw_lock);
875 +}
876 +
877 +void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
878 + void __iomem *wdma, int index)
879 +{
880 + static const struct mtk_wed_ops wed_ops = {
881 + .attach = mtk_wed_attach,
882 + .tx_ring_setup = mtk_wed_tx_ring_setup,
883 + .txfree_ring_setup = mtk_wed_txfree_ring_setup,
884 + .start = mtk_wed_start,
885 + .stop = mtk_wed_stop,
886 + .reset_dma = mtk_wed_reset_dma,
887 + .reg_read = wed_r32,
888 + .reg_write = wed_w32,
889 + .irq_get = mtk_wed_irq_get,
890 + .irq_set_mask = mtk_wed_irq_set_mask,
891 + .detach = mtk_wed_detach,
892 + };
893 + struct device_node *eth_np = eth->dev->of_node;
894 + struct platform_device *pdev;
895 + struct mtk_wed_hw *hw;
896 + struct regmap *regs;
897 + int irq;
898 +
899 + if (!np)
900 + return;
901 +
902 + pdev = of_find_device_by_node(np);
903 + if (!pdev)
904 + return;
905 +
906 + get_device(&pdev->dev);
907 + irq = platform_get_irq(pdev, 0);
908 + if (irq < 0)
909 + return;
910 +
911 + regs = syscon_regmap_lookup_by_phandle(np, NULL);
912 + if (!regs)
913 + return;
914 +
915 + rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);
916 +
917 + mutex_lock(&hw_lock);
918 +
919 + if (WARN_ON(hw_list[index]))
920 + goto unlock;
921 +
922 + hw = kzalloc(sizeof(*hw), GFP_KERNEL);
923 + hw->node = np;
924 + hw->regs = regs;
925 + hw->eth = eth;
926 + hw->dev = &pdev->dev;
927 + hw->wdma = wdma;
928 + hw->index = index;
929 + hw->irq = irq;
930 + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
931 + "mediatek,pcie-mirror");
932 + hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
933 + "mediatek,hifsys");
934 + if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
935 + kfree(hw);
936 + goto unlock;
937 + }
938 +
939 + if (!index) {
940 + regmap_write(hw->mirror, 0, 0);
941 + regmap_write(hw->mirror, 4, 0);
942 + }
943 + mtk_wed_hw_add_debugfs(hw);
944 +
945 + hw_list[index] = hw;
946 +
947 +unlock:
948 + mutex_unlock(&hw_lock);
949 +}
950 +
951 +void mtk_wed_exit(void)
952 +{
953 + int i;
954 +
955 + rcu_assign_pointer(mtk_soc_wed_ops, NULL);
956 +
957 + synchronize_rcu();
958 +
959 + for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
960 + struct mtk_wed_hw *hw;
961 +
962 + hw = hw_list[i];
963 + if (!hw)
964 + continue;
965 +
966 + hw_list[i] = NULL;
967 + debugfs_remove(hw->debugfs_dir);
968 + put_device(hw->dev);
969 + kfree(hw);
970 + }
971 +}
972 --- /dev/null
973 +++ b/drivers/net/ethernet/mediatek/mtk_wed.h
974 @@ -0,0 +1,128 @@
975 +// SPDX-License-Identifier: GPL-2.0-only
976 +/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
977 +
978 +#ifndef __MTK_WED_PRIV_H
979 +#define __MTK_WED_PRIV_H
980 +
981 +#include <linux/soc/mediatek/mtk_wed.h>
982 +#include <linux/debugfs.h>
983 +#include <linux/regmap.h>
984 +
985 +struct mtk_eth;
986 +
987 +struct mtk_wed_hw {
988 + struct device_node *node;
989 + struct mtk_eth *eth;
990 + struct regmap *regs;
991 + struct regmap *hifsys;
992 + struct device *dev;
993 + void __iomem *wdma;
994 + struct regmap *mirror;
995 + struct dentry *debugfs_dir;
996 + struct mtk_wed_device *wed_dev;
997 + u32 debugfs_reg;
998 + u32 num_flows;
999 + char dirname[5];
1000 + int irq;
1001 + int index;
1002 +};
1003 +
1004 +
1005 +#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1006 +static inline void
1007 +wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
1008 +{
1009 + regmap_write(dev->hw->regs, reg, val);
1010 +}
1011 +
1012 +static inline u32
1013 +wed_r32(struct mtk_wed_device *dev, u32 reg)
1014 +{
1015 + unsigned int val;
1016 +
1017 + regmap_read(dev->hw->regs, reg, &val);
1018 +
1019 + return val;
1020 +}
1021 +
1022 +static inline void
1023 +wdma_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
1024 +{
1025 + writel(val, dev->hw->wdma + reg);
1026 +}
1027 +
1028 +static inline u32
1029 +wdma_r32(struct mtk_wed_device *dev, u32 reg)
1030 +{
1031 + return readl(dev->hw->wdma + reg);
1032 +}
1033 +
1034 +static inline u32
1035 +wpdma_tx_r32(struct mtk_wed_device *dev, int ring, u32 reg)
1036 +{
1037 + if (!dev->tx_ring[ring].wpdma)
1038 + return 0;
1039 +
1040 + return readl(dev->tx_ring[ring].wpdma + reg);
1041 +}
1042 +
1043 +static inline void
1044 +wpdma_tx_w32(struct mtk_wed_device *dev, int ring, u32 reg, u32 val)
1045 +{
1046 + if (!dev->tx_ring[ring].wpdma)
1047 + return;
1048 +
1049 + writel(val, dev->tx_ring[ring].wpdma + reg);
1050 +}
1051 +
1052 +static inline u32
1053 +wpdma_txfree_r32(struct mtk_wed_device *dev, u32 reg)
1054 +{
1055 + if (!dev->txfree_ring.wpdma)
1056 + return 0;
1057 +
1058 + return readl(dev->txfree_ring.wpdma + reg);
1059 +}
1060 +
1061 +static inline void
1062 +wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
1063 +{
1064 + if (!dev->txfree_ring.wpdma)
1065 + return;
1066 +
1067 + writel(val, dev->txfree_ring.wpdma + reg);
1068 +}
1069 +
1070 +void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
1071 + void __iomem *wdma, int index);
1072 +void mtk_wed_exit(void);
1073 +int mtk_wed_flow_add(int index);
1074 +void mtk_wed_flow_remove(int index);
1075 +#else
1076 +static inline void
1077 +mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
1078 + void __iomem *wdma, int index)
1079 +{
1080 +}
1081 +static inline void
1082 +mtk_wed_exit(void)
1083 +{
1084 +}
1085 +static inline int mtk_wed_flow_add(int index)
1086 +{
1087 + return -EINVAL;
1088 +}
1089 +static inline void mtk_wed_flow_remove(int index)
1090 +{
1091 +}
1092 +#endif
1093 +
1094 +#ifdef CONFIG_DEBUG_FS
1095 +void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw);
1096 +#else
1097 +static inline void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
1098 +{
1099 +}
1100 +#endif
1101 +
1102 +#endif
1103 --- /dev/null
1104 +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
1105 @@ -0,0 +1,175 @@
1106 +// SPDX-License-Identifier: GPL-2.0-only
1107 +/* Copyright (C) 2021 Felix Fietkau <nbd@nbd.name> */
1108 +
1109 +#include <linux/seq_file.h>
1110 +#include "mtk_wed.h"
1111 +#include "mtk_wed_regs.h"
1112 +
1113 +struct reg_dump {
1114 + const char *name;
1115 + u16 offset;
1116 + u8 type;
1117 + u8 base;
1118 +};
1119 +
1120 +enum {
1121 + DUMP_TYPE_STRING,
1122 + DUMP_TYPE_WED,
1123 + DUMP_TYPE_WDMA,
1124 + DUMP_TYPE_WPDMA_TX,
1125 + DUMP_TYPE_WPDMA_TXFREE,
1126 +};
1127 +
1128 +#define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
1129 +#define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
1130 +#define DUMP_RING(_prefix, _base, ...) \
1131 + { _prefix " BASE", _base, __VA_ARGS__ }, \
1132 + { _prefix " CNT", _base + 0x4, __VA_ARGS__ }, \
1133 + { _prefix " CIDX", _base + 0x8, __VA_ARGS__ }, \
1134 + { _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
1135 +
1136 +#define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
1137 +#define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
1138 +
1139 +#define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
1140 +#define DUMP_WDMA_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WDMA)
1141 +
1142 +#define DUMP_WPDMA_TX_RING(_n) DUMP_RING("WPDMA_TX" #_n, 0, DUMP_TYPE_WPDMA_TX, _n)
1143 +#define DUMP_WPDMA_TXFREE_RING DUMP_RING("WPDMA_RX1", 0, DUMP_TYPE_WPDMA_TXFREE)
1144 +
1145 +static void
1146 +print_reg_val(struct seq_file *s, const char *name, u32 val)
1147 +{
1148 + seq_printf(s, "%-32s %08x\n", name, val);
1149 +}
1150 +
1151 +static void
1152 +dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev,
1153 + const struct reg_dump *regs, int n_regs)
1154 +{
1155 + const struct reg_dump *cur;
1156 + u32 val;
1157 +
1158 + for (cur = regs; cur < &regs[n_regs]; cur++) {
1159 + switch (cur->type) {
1160 + case DUMP_TYPE_STRING:
1161 + seq_printf(s, "%s======== %s:\n",
1162 + cur > regs ? "\n" : "",
1163 + cur->name);
1164 + continue;
1165 + case DUMP_TYPE_WED:
1166 + val = wed_r32(dev, cur->offset);
1167 + break;
1168 + case DUMP_TYPE_WDMA:
1169 + val = wdma_r32(dev, cur->offset);
1170 + break;
1171 + case DUMP_TYPE_WPDMA_TX:
1172 + val = wpdma_tx_r32(dev, cur->base, cur->offset);
1173 + break;
1174 + case DUMP_TYPE_WPDMA_TXFREE:
1175 + val = wpdma_txfree_r32(dev, cur->offset);
1176 + break;
1177 + }
1178 + print_reg_val(s, cur->name, val);
1179 + }
1180 +}
1181 +
1182 +
1183 +static int
1184 +wed_txinfo_show(struct seq_file *s, void *data)
1185 +{
1186 + static const struct reg_dump regs[] = {
1187 + DUMP_STR("WED TX"),
1188 + DUMP_WED(WED_TX_MIB(0)),
1189 + DUMP_WED_RING(WED_RING_TX(0)),
1190 +
1191 + DUMP_WED(WED_TX_MIB(1)),
1192 + DUMP_WED_RING(WED_RING_TX(1)),
1193 +
1194 + DUMP_STR("WPDMA TX"),
1195 + DUMP_WED(WED_WPDMA_TX_MIB(0)),
1196 + DUMP_WED_RING(WED_WPDMA_RING_TX(0)),
1197 + DUMP_WED(WED_WPDMA_TX_COHERENT_MIB(0)),
1198 +
1199 + DUMP_WED(WED_WPDMA_TX_MIB(1)),
1200 + DUMP_WED_RING(WED_WPDMA_RING_TX(1)),
1201 + DUMP_WED(WED_WPDMA_TX_COHERENT_MIB(1)),
1202 +
1203 + DUMP_STR("WPDMA TX"),
1204 + DUMP_WPDMA_TX_RING(0),
1205 + DUMP_WPDMA_TX_RING(1),
1206 +
1207 + DUMP_STR("WED WDMA RX"),
1208 + DUMP_WED(WED_WDMA_RX_MIB(0)),
1209 + DUMP_WED_RING(WED_WDMA_RING_RX(0)),
1210 + DUMP_WED(WED_WDMA_RX_THRES(0)),
1211 + DUMP_WED(WED_WDMA_RX_RECYCLE_MIB(0)),
1212 + DUMP_WED(WED_WDMA_RX_PROCESSED_MIB(0)),
1213 +
1214 + DUMP_WED(WED_WDMA_RX_MIB(1)),
1215 + DUMP_WED_RING(WED_WDMA_RING_RX(1)),
1216 + DUMP_WED(WED_WDMA_RX_THRES(1)),
1217 + DUMP_WED(WED_WDMA_RX_RECYCLE_MIB(1)),
1218 + DUMP_WED(WED_WDMA_RX_PROCESSED_MIB(1)),
1219 +
1220 + DUMP_STR("WDMA RX"),
1221 + DUMP_WDMA(WDMA_GLO_CFG),
1222 + DUMP_WDMA_RING(WDMA_RING_RX(0)),
1223 + DUMP_WDMA_RING(WDMA_RING_RX(1)),
1224 + };
1225 + struct mtk_wed_hw *hw = s->private;
1226 + struct mtk_wed_device *dev = hw->wed_dev;
1227 +
1228 + if (!dev)
1229 + return 0;
1230 +
1231 + dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
1232 +
1233 + return 0;
1234 +}
1235 +DEFINE_SHOW_ATTRIBUTE(wed_txinfo);
1236 +
1237 +
1238 +static int
1239 +mtk_wed_reg_set(void *data, u64 val)
1240 +{
1241 + struct mtk_wed_hw *hw = data;
1242 +
1243 + regmap_write(hw->regs, hw->debugfs_reg, val);
1244 +
1245 + return 0;
1246 +}
1247 +
1248 +static int
1249 +mtk_wed_reg_get(void *data, u64 *val)
1250 +{
1251 + struct mtk_wed_hw *hw = data;
1252 + unsigned int regval;
1253 + int ret;
1254 +
1255 + ret = regmap_read(hw->regs, hw->debugfs_reg, &regval);
1256 + if (ret)
1257 + return ret;
1258 +
1259 + *val = regval;
1260 +
1261 + return 0;
1262 +}
1263 +
1264 +DEFINE_DEBUGFS_ATTRIBUTE(fops_regval, mtk_wed_reg_get, mtk_wed_reg_set,
1265 + "0x%08llx\n");
1266 +
1267 +void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw)
1268 +{
1269 + struct dentry *dir;
1270 +
1271 + snprintf(hw->dirname, sizeof(hw->dirname), "wed%d", hw->index);
1272 + dir = debugfs_create_dir(hw->dirname, NULL);
1273 + if (!dir)
1274 + return;
1275 +
1276 + hw->debugfs_dir = dir;
1277 + debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
1278 + debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
1279 + debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
1280 +}
1281 --- /dev/null
1282 +++ b/drivers/net/ethernet/mediatek/mtk_wed_ops.c
1283 @@ -0,0 +1,8 @@
1284 +// SPDX-License-Identifier: GPL-2.0-only
1285 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
1286 +
1287 +#include <linux/kernel.h>
1288 +#include <linux/soc/mediatek/mtk_wed.h>
1289 +
1290 +const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
1291 +EXPORT_SYMBOL_GPL(mtk_soc_wed_ops);
1292 --- /dev/null
1293 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
1294 @@ -0,0 +1,251 @@
1295 +// SPDX-License-Identifier: GPL-2.0-only
1296 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
1297 +
1298 +#ifndef __MTK_WED_REGS_H
1299 +#define __MTK_WED_REGS_H
1300 +
1301 +#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
1302 +#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
1303 +#define MTK_WDMA_DESC_CTRL_BURST BIT(16)
1304 +#define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
1305 +#define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
1306 +#define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
1307 +
1308 +struct mtk_wdma_desc {
1309 + __le32 buf0;
1310 + __le32 ctrl;
1311 + __le32 buf1;
1312 + __le32 info;
1313 +} __packed __aligned(4);
1314 +
1315 +#define MTK_WED_RESET 0x008
1316 +#define MTK_WED_RESET_TX_BM BIT(0)
1317 +#define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
1318 +#define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
1319 +#define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
1320 +#define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
1321 +#define MTK_WED_RESET_WED_TX_DMA BIT(12)
1322 +#define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
1323 +#define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
1324 +#define MTK_WED_RESET_WED BIT(31)
1325 +
1326 +#define MTK_WED_CTRL 0x00c
1327 +#define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
1328 +#define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
1329 +#define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
1330 +#define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
1331 +#define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
1332 +#define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
1333 +#define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
1334 +#define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
1335 +#define MTK_WED_CTRL_RESERVE_EN BIT(12)
1336 +#define MTK_WED_CTRL_RESERVE_BUSY BIT(13)
1337 +#define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
1338 +#define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
1339 +
1340 +#define MTK_WED_EXT_INT_STATUS 0x020
1341 +#define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
1342 +#define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1)
1343 +#define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
1344 +#define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
1345 +#define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
1346 +#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
1347 +#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
1348 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
1349 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
1350 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
1351 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
1352 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
1353 +#define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
1354 +#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22)
1355 +#define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
1356 +#define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
1357 + MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
1358 + MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
1359 + MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \
1360 + MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \
1361 + MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \
1362 + MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \
1363 + MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR)
1364 +
1365 +#define MTK_WED_EXT_INT_MASK 0x028
1366 +
1367 +#define MTK_WED_STATUS 0x060
1368 +#define MTK_WED_STATUS_TX GENMASK(15, 8)
1369 +
1370 +#define MTK_WED_TX_BM_CTRL 0x080
1371 +#define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM GENMASK(6, 0)
1372 +#define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
1373 +#define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
1374 +
1375 +#define MTK_WED_TX_BM_BASE 0x084
1376 +
1377 +#define MTK_WED_TX_BM_TKID 0x088
1378 +#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
1379 +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
1380 +
1381 +#define MTK_WED_TX_BM_BUF_LEN 0x08c
1382 +
1383 +#define MTK_WED_TX_BM_INTF 0x09c
1384 +#define MTK_WED_TX_BM_INTF_TKID GENMASK(15, 0)
1385 +#define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16)
1386 +#define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28)
1387 +#define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
1388 +
1389 +#define MTK_WED_TX_BM_DYN_THR 0x0a0
1390 +#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
1391 +#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
1392 +
1393 +#define MTK_WED_INT_STATUS 0x200
1394 +#define MTK_WED_INT_MASK 0x204
1395 +
1396 +#define MTK_WED_GLO_CFG 0x208
1397 +#define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)
1398 +#define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1)
1399 +#define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2)
1400 +#define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3)
1401 +#define MTK_WED_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
1402 +#define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6)
1403 +#define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7)
1404 +#define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
1405 +#define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9)
1406 +#define MTK_WED_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
1407 +#define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
1408 +#define MTK_WED_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)
1409 +#define MTK_WED_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)
1410 +#define MTK_WED_GLO_CFG_SW_RESET BIT(24)
1411 +#define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
1412 +#define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
1413 +#define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28)
1414 +#define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29)
1415 +#define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31)
1416 +
1417 +#define MTK_WED_RESET_IDX 0x20c
1418 +#define MTK_WED_RESET_IDX_TX GENMASK(3, 0)
1419 +#define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
1420 +
1421 +#define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
1422 +
1423 +#define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
1424 +
1425 +#define MTK_WED_RING_RX(_n) (0x400 + (_n) * 0x10)
1426 +
1427 +#define MTK_WED_WPDMA_INT_TRIGGER 0x504
1428 +#define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
1429 +#define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE GENMASK(5, 4)
1430 +
1431 +#define MTK_WED_WPDMA_GLO_CFG 0x508
1432 +#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)
1433 +#define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
1434 +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
1435 +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
1436 +#define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
1437 +#define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
1438 +#define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
1439 +#define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
1440 +#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9)
1441 +#define MTK_WED_WPDMA_GLO_CFG_MULTI_DMA_EN GENMASK(11, 10)
1442 +#define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
1443 +#define MTK_WED_WPDMA_GLO_CFG_MI_DEPTH_RD GENMASK(21, 13)
1444 +#define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_HI GENMASK(23, 22)
1445 +#define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24)
1446 +#define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
1447 +#define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
1448 +#define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
1449 +#define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)
1450 +#define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
1451 +
1452 +#define MTK_WED_WPDMA_RESET_IDX 0x50c
1453 +#define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)
1454 +#define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)
1455 +
1456 +#define MTK_WED_WPDMA_INT_CTRL 0x520
1457 +#define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)
1458 +
1459 +#define MTK_WED_WPDMA_INT_MASK 0x524
1460 +
1461 +#define MTK_WED_PCIE_CFG_BASE 0x560
1462 +
1463 +#define MTK_WED_PCIE_INT_TRIGGER 0x570
1464 +#define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
1465 +
1466 +#define MTK_WED_WPDMA_CFG_BASE 0x580
1467 +
1468 +#define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4)
1469 +#define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4)
1470 +
1471 +#define MTK_WED_WPDMA_RING_TX(_n) (0x600 + (_n) * 0x10)
1472 +#define MTK_WED_WPDMA_RING_RX(_n) (0x700 + (_n) * 0x10)
1473 +#define MTK_WED_WDMA_RING_RX(_n) (0x900 + (_n) * 0x10)
1474 +#define MTK_WED_WDMA_RX_THRES(_n) (0x940 + (_n) * 0x4)
1475 +
1476 +#define MTK_WED_WDMA_GLO_CFG 0xa04
1477 +#define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
1478 +#define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
1479 +#define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
1480 +#define MTK_WED_WDMA_GLO_CFG_BT_SIZE GENMASK(5, 4)
1481 +#define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6)
1482 +#define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13)
1483 +#define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16)
1484 +#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17)
1485 +#define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18)
1486 +#define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19)
1487 +#define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20)
1488 +#define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21)
1489 +#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22)
1490 +#define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23)
1491 +#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24)
1492 +#define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25)
1493 +#define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26)
1494 +#define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30)
1495 +
1496 +#define MTK_WED_WDMA_RESET_IDX 0xa08
1497 +#define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
1498 +#define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)
1499 +
1500 +#define MTK_WED_WDMA_INT_TRIGGER 0xa28
1501 +#define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
1502 +
1503 +#define MTK_WED_WDMA_INT_CTRL 0xa2c
1504 +#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)
1505 +
1506 +#define MTK_WED_WDMA_OFFSET0 0xaa4
1507 +#define MTK_WED_WDMA_OFFSET1 0xaa8
1508 +
1509 +#define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4)
1510 +#define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
1511 +#define MTK_WED_WDMA_RX_PROCESSED_MIB(_n) (0xaf0 + (_n) * 4)
1512 +
1513 +#define MTK_WED_RING_OFS_BASE 0x00
1514 +#define MTK_WED_RING_OFS_COUNT 0x04
1515 +#define MTK_WED_RING_OFS_CPU_IDX 0x08
1516 +#define MTK_WED_RING_OFS_DMA_IDX 0x0c
1517 +
1518 +#define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)
1519 +
1520 +#define MTK_WDMA_GLO_CFG 0x204
1521 +#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26)
1522 +
1523 +#define MTK_WDMA_RESET_IDX 0x208
1524 +#define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)
1525 +#define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)
1526 +
1527 +#define MTK_WDMA_INT_MASK 0x228
1528 +#define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0)
1529 +#define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16)
1530 +#define MTK_WDMA_INT_MASK_TX_DELAY BIT(28)
1531 +#define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29)
1532 +#define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)
1533 +#define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)
1534 +
1535 +#define MTK_WDMA_INT_GRP1 0x250
1536 +#define MTK_WDMA_INT_GRP2 0x254
1537 +
1538 +#define MTK_PCIE_MIRROR_MAP(n) ((n) ? 0x4 : 0x0)
1539 +#define MTK_PCIE_MIRROR_MAP_EN BIT(0)
1540 +#define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
1541 +
1542 +/* DMA channel mapping */
1543 +#define HIFSYS_DMA_AG_MAP 0x008
1544 +
1545 +#endif
1546 --- /dev/null
1547 +++ b/include/linux/soc/mediatek/mtk_wed.h
1548 @@ -0,0 +1,131 @@
1549 +#ifndef __MTK_WED_H
1550 +#define __MTK_WED_H
1551 +
1552 +#include <linux/kernel.h>
1553 +#include <linux/rcupdate.h>
1554 +#include <linux/regmap.h>
1555 +#include <linux/pci.h>
1556 +
1557 +#define MTK_WED_TX_QUEUES 2
1558 +
1559 +struct mtk_wed_hw;
1560 +struct mtk_wdma_desc;
1561 +
1562 +struct mtk_wed_ring {
1563 + struct mtk_wdma_desc *desc;
1564 + dma_addr_t desc_phys;
1565 + int size;
1566 +
1567 + u32 reg_base;
1568 + void __iomem *wpdma;
1569 +};
1570 +
1571 +struct mtk_wed_device {
1572 +#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1573 + const struct mtk_wed_ops *ops;
1574 + struct device *dev;
1575 + struct mtk_wed_hw *hw;
1576 + bool init_done, running;
1577 + int wdma_idx;
1578 + int irq;
1579 +
1580 + struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
1581 + struct mtk_wed_ring txfree_ring;
1582 + struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
1583 +
1584 + struct {
1585 + int size;
1586 + void **pages;
1587 + struct mtk_wdma_desc *desc;
1588 + dma_addr_t desc_phys;
1589 + } buf_ring;
1590 +
1591 + /* filled by driver: */
1592 + struct {
1593 + struct pci_dev *pci_dev;
1594 +
1595 + u32 wpdma_phys;
1596 +
1597 + u16 token_start;
1598 + unsigned int nbuf;
1599 +
1600 + u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
1601 + int (*offload_enable)(struct mtk_wed_device *wed);
1602 + void (*offload_disable)(struct mtk_wed_device *wed);
1603 + } wlan;
1604 +#endif
1605 +};
1606 +
1607 +struct mtk_wed_ops {
1608 + int (*attach)(struct mtk_wed_device *dev);
1609 + int (*tx_ring_setup)(struct mtk_wed_device *dev, int ring,
1610 + void __iomem *regs);
1611 + int (*txfree_ring_setup)(struct mtk_wed_device *dev,
1612 + void __iomem *regs);
1613 + void (*detach)(struct mtk_wed_device *dev);
1614 +
1615 + void (*stop)(struct mtk_wed_device *dev);
1616 + void (*start)(struct mtk_wed_device *dev, u32 irq_mask);
1617 + void (*reset_dma)(struct mtk_wed_device *dev);
1618 +
1619 + u32 (*reg_read)(struct mtk_wed_device *dev, u32 reg);
1620 + void (*reg_write)(struct mtk_wed_device *dev, u32 reg, u32 val);
1621 +
1622 + u32 (*irq_get)(struct mtk_wed_device *dev, u32 mask);
1623 + void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);
1624 +};
1625 +
1626 +extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
1627 +
1628 +static inline int
1629 +mtk_wed_device_attach(struct mtk_wed_device *dev)
1630 +{
1631 + int ret = -ENODEV;
1632 +
1633 +#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1634 + rcu_read_lock();
1635 + dev->ops = rcu_dereference(mtk_soc_wed_ops);
1636 + if (dev->ops)
1637 + ret = dev->ops->attach(dev);
1638 + else
1639 + rcu_read_unlock();
1640 +
1641 + if (ret)
1642 + dev->ops = NULL;
1643 +#endif
1644 +
1645 + return ret;
1646 +}
1647 +
1648 +#ifdef CONFIG_NET_MEDIATEK_SOC_WED
1649 +#define mtk_wed_device_active(_dev) !!(_dev)->ops
1650 +#define mtk_wed_device_detach(_dev) (_dev)->ops->detach(_dev)
1651 +#define mtk_wed_device_start(_dev, _mask) (_dev)->ops->start(_dev, _mask)
1652 +#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) \
1653 + (_dev)->ops->tx_ring_setup(_dev, _ring, _regs)
1654 +#define mtk_wed_device_txfree_ring_setup(_dev, _regs) \
1655 + (_dev)->ops->txfree_ring_setup(_dev, _regs)
1656 +#define mtk_wed_device_reg_read(_dev, _reg) \
1657 + (_dev)->ops->reg_read(_dev, _reg)
1658 +#define mtk_wed_device_reg_write(_dev, _reg, _val) \
1659 + (_dev)->ops->reg_write(_dev, _reg, _val)
1660 +#define mtk_wed_device_irq_get(_dev, _mask) \
1661 + (_dev)->ops->irq_get(_dev, _mask)
1662 +#define mtk_wed_device_irq_set_mask(_dev, _mask) \
1663 + (_dev)->ops->irq_set_mask(_dev, _mask)
1664 +#else
1665 +static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
1666 +{
1667 + return false;
1668 +}
1669 +#define mtk_wed_device_detach(_dev) do {} while (0)
1670 +#define mtk_wed_device_start(_dev, _mask) do {} while (0)
1671 +#define mtk_wed_device_tx_ring_setup(_dev, _ring, _regs) -ENODEV
1672 +#define mtk_wed_device_txfree_ring_setup(_dev, _ring, _regs) -ENODEV
1673 +#define mtk_wed_device_reg_read(_dev, _reg) 0
1674 +#define mtk_wed_device_reg_write(_dev, _reg, _val) do {} while (0)
1675 +#define mtk_wed_device_irq_get(_dev, _mask) 0
1676 +#define mtk_wed_device_irq_set_mask(_dev, _mask) do {} while (0)
1677 +#endif
1678 +
1679 +#endif
Staging tree of Christian Marangi