b9b1636b1624dfd36a561e92b8c7480c0dfded10
[openwrt/staging/ldir.git] /
1 From e63d40712a11de18ea217c2211dfd3ae937bab7f Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Mon, 13 Dec 2021 15:33:11 +0100
4 Subject: [PATCH] drm/vc4: hdmi: Take the sink maximum TMDS clock into
5 account
6
7 In the function that validates that the clock isn't too high, we've only
8 taken our controller limitations into account so far.
9
10 However, the sink can have a limit on the maximum TMDS clock it can deal
11 with too which is exposed through the EDID and the drm_display_info.
12
13 Make sure we check it.
14
15 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
16 ---
17 drivers/gpu/drm/vc4/vc4_hdmi.c | 6 ++++++
18 1 file changed, 6 insertions(+)
19
20 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
21 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
22 @@ -1254,12 +1254,18 @@ static enum drm_mode_status
23 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
24 unsigned long long clock)
25 {
26 + const struct drm_connector *connector = &vc4_hdmi->connector;
27 + const struct drm_display_info *info = &connector->display_info;
28 +
29 if (clock > vc4_hdmi->variant->max_pixel_clock)
30 return MODE_CLOCK_HIGH;
31
32 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
33 return MODE_CLOCK_HIGH;
34
35 + if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
36 + return MODE_CLOCK_HIGH;
37 +
38 return MODE_OK;
39 }
40