git.openwrt.org Git - openwrt/staging/jogo.git/blob

   1 From fd0bb28c547f7c8affb1691128cece38f5b626a1 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Thu, 14 Oct 2021 00:39:19 +0200
   4 Subject: net: dsa: qca8k: move port config to dedicated struct
   5
   6 Move ports related config to dedicated struct to keep things organized.
   7
   8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
   9 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
  10 Signed-off-by: David S. Miller <davem@davemloft.net>
  11 ---
  12  drivers/net/dsa/qca8k.c | 26 +++++++++++++-------------
  13  drivers/net/dsa/qca8k.h | 10 +++++++---
  14  2 files changed, 20 insertions(+), 16 deletions(-)
  15
  16 --- a/drivers/net/dsa/qca8k.c
  17 +++ b/drivers/net/dsa/qca8k.c
  18 @@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_pri
  19                                 delay = 3;
  20                         }
  21
  22 -                       priv->rgmii_tx_delay[cpu_port_index] = delay;
  23 +                       priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
  24
  25                         delay = 0;
  26
  27 @@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_pri
  28                                 delay = 3;
  29                         }
  30
  31 -                       priv->rgmii_rx_delay[cpu_port_index] = delay;
  32 +                       priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
  33
  34                         /* Skip sgmii parsing for rgmii* mode */
  35                         if (mode == PHY_INTERFACE_MODE_RGMII ||
  36 @@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_pri
  37                                 break;
  38
  39                         if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
  40 -                               priv->sgmii_tx_clk_falling_edge = true;
  41 +                               priv->ports_config.sgmii_tx_clk_falling_edge = true;
  42
  43                         if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
  44 -                               priv->sgmii_rx_clk_falling_edge = true;
  45 +                               priv->ports_config.sgmii_rx_clk_falling_edge = true;
  46
  47                         if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
  48 -                               priv->sgmii_enable_pll = true;
  49 +                               priv->ports_config.sgmii_enable_pll = true;
  50
  51                                 if (priv->switch_id == QCA8K_ID_QCA8327) {
  52                                         dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
  53 -                                       priv->sgmii_enable_pll = false;
  54 +                                       priv->ports_config.sgmii_enable_pll = false;
  55                                 }
  56
  57                                 if (priv->switch_revision < 2)
  58 @@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(st
  59          * not enabled. With ID or TX/RXID delay is enabled and set
  60          * to the default and recommended value.
  61          */
  62 -       if (priv->rgmii_tx_delay[cpu_port_index]) {
  63 -               delay = priv->rgmii_tx_delay[cpu_port_index];
  64 +       if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
  65 +               delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
  66
  67                 val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
  68                         QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
  69         }
  70
  71 -       if (priv->rgmii_rx_delay[cpu_port_index]) {
  72 -               delay = priv->rgmii_rx_delay[cpu_port_index];
  73 +       if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
  74 +               delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
  75
  76                 val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
  77                         QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
  78 @@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_swit
  79
  80                 val |= QCA8K_SGMII_EN_SD;
  81
  82 -               if (priv->sgmii_enable_pll)
  83 +               if (priv->ports_config.sgmii_enable_pll)
  84                         val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  85                                QCA8K_SGMII_EN_TX;
  86
  87 @@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_swit
  88                 val = 0;
  89
  90                 /* SGMII Clock phase configuration */
  91 -               if (priv->sgmii_rx_clk_falling_edge)
  92 +               if (priv->ports_config.sgmii_rx_clk_falling_edge)
  93                         val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  94
  95 -               if (priv->sgmii_tx_clk_falling_edge)
  96 +               if (priv->ports_config.sgmii_tx_clk_falling_edge)
  97                         val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  98
  99                 if (val)
 100 --- a/drivers/net/dsa/qca8k.h
 101 +++ b/drivers/net/dsa/qca8k.h
 102 @@ -270,15 +270,19 @@ enum {
 103         QCA8K_CPU_PORT6,
 104  };
 105
 106 -struct qca8k_priv {
 107 -       u8 switch_id;
 108 -       u8 switch_revision;
 109 +struct qca8k_ports_config {
 110         bool sgmii_rx_clk_falling_edge;
 111         bool sgmii_tx_clk_falling_edge;
 112         bool sgmii_enable_pll;
 113         u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 114         u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
 115 +};
 116 +
 117 +struct qca8k_priv {
 118 +       u8 switch_id;
 119 +       u8 switch_revision;
 120         bool legacy_phy_port_mapping;
 121 +       struct qca8k_ports_config ports_config;
 122         struct regmap *regmap;
 123         struct mii_bus *bus;
 124         struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];