git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 198675bbc03d437fb80a35d781ad13d622d0ff68 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Tue, 10 Sep 2024 06:40:24 +0200
   4 Subject: [PATCH 3/3] clk: ralink: mtmips: add mmc related clocks for SoCs
   5  MT7620, MT7628 and MT7688
   6
   7 Original architecture clock code from where this driver was derived did not
   8 include nothing related to mmc clocks. OpenWRT people started to use mtk-sd
   9 upstream driver recently and they were forced to use a dts 'fixed-clock'
  10 node with 48 MHz clock:
  11 - https://github.com/openwrt/openwrt/pull/15896
  12 The proper thing to do to avoid that is to add the mmc related clocks to the
  13 driver to avoid a dts with fixed clocks nodes. The minimal documentation in
  14 the mt7620 programming guide says that there is a BBP_PLL clock of 480 MHz
  15 derived from the 40 MHz XTAL and from there a clock divider by ten produces
  16 the desired SDHC clock of 48 MHz for the mmc. Hence add a fixed clock 'bbppll'
  17 and factor clock 'sdhc' ten divider child to properly set the 'mmc' peripheral
  18 clock with the desired 48 Mhz rate.
  19
  20 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  21 Link: https://lore.kernel.org/r/20240910044024.120009-4-sergio.paracuellos@gmail.com
  22 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  23 ---
  24  drivers/clk/ralink/clk-mtmips.c | 30 +++++++++++++++++++++++-------
  25  1 file changed, 23 insertions(+), 7 deletions(-)
  26
  27 --- a/drivers/clk/ralink/clk-mtmips.c
  28 +++ b/drivers/clk/ralink/clk-mtmips.c
  29 @@ -207,6 +207,7 @@ static struct mtmips_clk mt7620_pherip_c
  30         { CLK_PERIPH("10000b00.spi", "bus") },
  31         { CLK_PERIPH("10000b40.spi", "bus") },
  32         { CLK_PERIPH("10000c00.uartlite", "periph") },
  33 +       { CLK_PERIPH("10130000.mmc", "sdhc") },
  34         { CLK_PERIPH("10180000.wmac", "xtal") }
  35  };
  36
  37 @@ -220,6 +221,7 @@ static struct mtmips_clk mt76x8_pherip_c
  38         { CLK_PERIPH("10000c00.uart0", "periph") },
  39         { CLK_PERIPH("10000d00.uart1", "periph") },
  40         { CLK_PERIPH("10000e00.uart2", "periph") },
  41 +       { CLK_PERIPH("10130000.mmc", "sdhc") },
  42         { CLK_PERIPH("10300000.wmac", "xtal") }
  43  };
  44
  45 @@ -272,8 +274,13 @@ static struct mtmips_clk_fixed rt3352_fi
  46         CLK_FIXED("periph", "xtal", 40000000)
  47  };
  48
  49 +static struct mtmips_clk_fixed mt7620_fixed_clocks[] = {
  50 +       CLK_FIXED("bbppll", "xtal", 480000000)
  51 +};
  52 +
  53  static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
  54 -       CLK_FIXED("pcmi2s", "xtal", 480000000),
  55 +       CLK_FIXED("bbppll", "xtal", 480000000),
  56 +       CLK_FIXED("pcmi2s", "bbppll", 480000000),
  57         CLK_FIXED("periph", "xtal", 40000000)
  58  };
  59
  60 @@ -328,6 +335,15 @@ static struct mtmips_clk_factor rt305x_f
  61         CLK_FACTOR("bus", "cpu", 1, 3)
  62  };
  63
  64 +static struct mtmips_clk_factor mt7620_factor_clocks[] = {
  65 +       CLK_FACTOR("sdhc", "bbppll", 1, 10)
  66 +};
  67 +
  68 +static struct mtmips_clk_factor mt76x8_factor_clocks[] = {
  69 +       CLK_FACTOR("bus", "cpu", 1, 3),
  70 +       CLK_FACTOR("sdhc", "bbppll", 1, 10)
  71 +};
  72 +
  73  static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
  74                                          struct mtmips_clk_priv *priv)
  75  {
  76 @@ -811,10 +827,10 @@ static const struct mtmips_clk_data rt53
  77  static const struct mtmips_clk_data mt7620_clk_data = {
  78         .clk_base = mt7620_clks_base,
  79         .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
  80 -       .clk_fixed = NULL,
  81 -       .num_clk_fixed = 0,
  82 -       .clk_factor = NULL,
  83 -       .num_clk_factor = 0,
  84 +       .clk_fixed = mt7620_fixed_clocks,
  85 +       .num_clk_fixed = ARRAY_SIZE(mt7620_fixed_clocks),
  86 +       .clk_factor = mt7620_factor_clocks,
  87 +       .num_clk_factor = ARRAY_SIZE(mt7620_factor_clocks),
  88         .clk_periph = mt7620_pherip_clks,
  89         .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
  90  };
  91 @@ -824,8 +840,8 @@ static const struct mtmips_clk_data mt76
  92         .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
  93         .clk_fixed = mt76x8_fixed_clocks,
  94         .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
  95 -       .clk_factor = rt305x_factor_clocks,
  96 -       .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
  97 +       .clk_factor = mt76x8_factor_clocks,
  98 +       .num_clk_factor = ARRAY_SIZE(mt76x8_factor_clocks),
  99         .clk_periph = mt76x8_pherip_clks,
 100         .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
 101  };