git.openwrt.org Git - openwrt/staging/lynxis.git/blob

   1 From 9319230ac147067652b58fe849ffe0ceec098665 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Tue, 30 Nov 2021 18:29:03 +0100
   4 Subject: [PATCH] PCI: pci-bridge-emul: Add description for class_revision
   5  field
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 The current assignment to the class_revision member
  11
  12   class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
  13
  14 can make the reader think that class is at high 16 bits of the member and
  15 revision at low 16 bits.
  16
  17 In reality, class is at high 24 bits, but the class for PCI Bridge Normal
  18 Decode is PCI_CLASS_BRIDGE_PCI << 8.
  19
  20 Change the assignment and add a comment to make this clearer.
  21
  22 Link: https://lore.kernel.org/r/20211130172913.9727-2-kabel@kernel.org
  23 Signed-off-by: Pali Rohár <pali@kernel.org>
  24 Signed-off-by: Marek Behún <kabel@kernel.org>
  25 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  26 ---
  27  drivers/pci/pci-bridge-emul.c | 6 +++++-
  28  1 file changed, 5 insertions(+), 1 deletion(-)
  29
  30 diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
  31 index db97cddfc85e..a4af1a533d71 100644
  32 --- a/drivers/pci/pci-bridge-emul.c
  33 +++ b/drivers/pci/pci-bridge-emul.c
  34 @@ -265,7 +265,11 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
  35  {
  36         BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
  37
  38 -       bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
  39 +       /*
  40 +        * class_revision: Class is high 24 bits and revision is low 8 bit of this member,
  41 +        * while class for PCI Bridge Normal Decode has the 24-bit value: PCI_CLASS_BRIDGE_PCI << 8
  42 +        */
  43 +       bridge->conf.class_revision |= cpu_to_le32((PCI_CLASS_BRIDGE_PCI << 8) << 8);
  44         bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
  45         bridge->conf.cache_line_size = 0x10;
  46         bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
  47 --
  48 2.34.1
  49