git.openwrt.org Git - openwrt/staging/blogic.git/blob

   1 From 14f118aa50fe7c7c7330f56d007ecacca487cea8 Mon Sep 17 00:00:00 2001
   2 From: Andre Przywara <andre.przywara@arm.com>
   3 Date: Mon, 19 Feb 2024 15:36:35 +0000
   4 Subject: [PATCH] thermal/drivers/sun8i: Explain unknown H6 register value
   5
   6 So far we were ORing in some "unknown" value into the THS control
   7 register on the Allwinner H6. This part of the register is not explained
   8 in the H6 manual, but the H616 manual details those bits, and on closer
   9 inspection the THS IP blocks in both SoCs seem very close:
  10 - The BSP code for both SoCs writes the same values into THS_CTRL.
  11 - The reset values of at least the first three registers are the same.
  12
  13 Replace the "unknown" value with its proper meaning: "acquire time",
  14 most probably the sample part of the sample & hold circuit of the ADC,
  15 according to its explanation in the H616 manual.
  16
  17 No functional change, just a macro rename and adjustment.
  18
  19 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
  20 Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
  21 Acked-by: Vasily Khoruzhick <anarsoul@gmail.com>
  22 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  23 Link: https://lore.kernel.org/r/20240219153639.179814-4-andre.przywara@arm.com
  24 ---
  25  drivers/thermal/sun8i_thermal.c | 29 ++++++++++++++++-------------
  26  1 file changed, 16 insertions(+), 13 deletions(-)
  27
  28 --- a/drivers/thermal/sun8i_thermal.c
  29 +++ b/drivers/thermal/sun8i_thermal.c
  30 @@ -50,7 +50,8 @@
  31  #define SUN8I_THS_CTRL2_T_ACQ1(x)              ((GENMASK(15, 0) & (x)) << 16)
  32  #define SUN8I_THS_DATA_IRQ_STS(x)              BIT(x + 8)
  33
  34 -#define SUN50I_THS_CTRL0_T_ACQ(x)              ((GENMASK(15, 0) & (x)) << 16)
  35 +#define SUN50I_THS_CTRL0_T_ACQ(x)              (GENMASK(15, 0) & ((x) - 1))
  36 +#define SUN50I_THS_CTRL0_T_SAMPLE_PER(x)       ((GENMASK(15, 0) & ((x) - 1)) << 16)
  37  #define SUN50I_THS_FILTER_EN                   BIT(2)
  38  #define SUN50I_THS_FILTER_TYPE(x)              (GENMASK(1, 0) & (x))
  39  #define SUN50I_H6_THS_PC_TEMP_PERIOD(x)                ((GENMASK(19, 0) & (x)) << 12)
  40 @@ -410,25 +411,27 @@ static int sun8i_h3_thermal_init(struct
  41         return 0;
  42  }
  43
  44 -/*
  45 - * Without this undocumented value, the returned temperatures would
  46 - * be higher than real ones by about 20C.
  47 - */
  48 -#define SUN50I_H6_CTRL0_UNK 0x0000002f
  49 -
  50  static int sun50i_h6_thermal_init(struct ths_device *tmdev)
  51  {
  52         int val;
  53
  54         /*
  55 -        * T_acq = 20us
  56 -        * clkin = 24MHz
  57 -        *
  58 -        * x = T_acq * clkin - 1
  59 -        *   = 479
  60 +        * The manual recommends an overall sample frequency of 50 KHz (20us,
  61 +        * 480 cycles at 24 MHz), which provides plenty of time for both the
  62 +        * acquisition time (>24 cycles) and the actual conversion time
  63 +        * (>14 cycles).
  64 +        * The lower half of the CTRL register holds the "acquire time", in
  65 +        * clock cycles, which the manual recommends to be 2us:
  66 +        * 24MHz * 2us = 48 cycles.
  67 +        * The high half of THS_CTRL encodes the sample frequency, in clock
  68 +        * cycles: 24MHz * 20us = 480 cycles.
  69 +        * This is explained in the H616 manual, but apparently wrongly
  70 +        * described in the H6 manual, although the BSP code does the same
  71 +        * for both SoCs.
  72          */
  73         regmap_write(tmdev->regmap, SUN50I_THS_CTRL0,
  74 -                    SUN50I_H6_CTRL0_UNK | SUN50I_THS_CTRL0_T_ACQ(479));
  75 +                    SUN50I_THS_CTRL0_T_ACQ(48) |
  76 +                    SUN50I_THS_CTRL0_T_SAMPLE_PER(480));
  77         /* average over 4 samples */
  78         regmap_write(tmdev->regmap, SUN50I_H6_THS_MFC,
  79                      SUN50I_THS_FILTER_EN |