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   1 From 2aad36357bbc73bc88ebab35a59a70a8f4ae6ecb Mon Sep 17 00:00:00 2001
   2 From: Christian Lamparter <chunkeey@gmail.com>
   3 Date: Wed, 31 Oct 2018 22:27:27 +0100
   4 Subject: [PATCH 2/2] dmaengine: dw: implement per-channel protection control
   5  setting
   6
   7 This patch adds a new device-tree property that allows to
   8 specify the protection control bits for each DMA channel
   9 individually.
  10
  11 Setting the "correct" bits can have a huge impact on the
  12 PPC460EX and APM82181 that use this DMA engine in combination
  13 with a DesignWare' SATA-II core (sata_dwc_460ex driver).
  14
  15 In the OpenWrt Forum, the user takimata reported that:
  16 |It seems your patch unleashed the full power of the SATA port.
  17 |Where I was previously hitting a really hard limit at around
  18 |82 MB/s for reading and 27 MB/s for writing, I am now getting this:
  19 |
  20 |root@OpenWrt:/mnt# time dd if=/dev/zero of=tempfile bs=1M count=1024
  21 |1024+0 records in
  22 |1024+0 records out
  23 |real    0m 13.65s
  24 |user    0m 0.01s
  25 |sys     0m 11.89s
  26 |
  27 |root@OpenWrt:/mnt# time dd if=tempfile of=/dev/null bs=1M count=1024
  28 |1024+0 records in
  29 |1024+0 records out
  30 |real    0m 8.41s
  31 |user    0m 0.01s
  32 |sys     0m 4.70s
  33 |
  34 |This means: 121 MB/s reading and 75 MB/s writing!
  35 |
  36 |The drive is a WD Green WD10EARX taken from an older MBL Single.
  37 |I repeated the test a few times with even larger files to rule out
  38 |any caching, I'm still seeing the same great performance. OpenWrt is
  39 |now completely on par with the original MBL firmware's performance.
  40
  41 Another user And.short reported:
  42 |I can report that your fix worked! Boots up fine with two
  43 |drives even with more partitions, and no more reboot on
  44 |concurrent disk access!
  45
  46 A closer look into the sata_dwc_460ex code revealed that
  47 the driver did initally set the correct protection control
  48 bits. However, this feature was lost when the sata_dwc_460ex
  49 driver was converted to the generic DMA driver framework.
  50
  51 BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/55
  52 BugLink: https://forum.openwrt.org/t/wd-mybook-live-duo-two-disks/16195/50
  53 Fixes: 8b3444852a2b ("sata_dwc_460ex: move to generic DMA driver")
  54 Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
  55 ---
  56  drivers/dma/dw/core.c                |  2 ++
  57  drivers/dma/dw/platform.c            | 12 +++++++++---
  58  drivers/dma/dw/regs.h                |  4 ++++
  59  include/linux/platform_data/dma-dw.h |  6 ++++++
  60  4 files changed, 21 insertions(+), 3 deletions(-)
  61
  62 --- a/drivers/dma/dw/core.c
  63 +++ b/drivers/dma/dw/core.c
  64 @@ -160,12 +160,14 @@ static void dwc_initialize_chan_idma32(s
  65
  66  static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc)
  67  {
  68 +       struct dw_dma *dw = to_dw_dma(dwc->chan.device);
  69         u32 cfghi = DWC_CFGH_FIFO_MODE;
  70         u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority);
  71         bool hs_polarity = dwc->dws.hs_polarity;
  72
  73         cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id);
  74         cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id);
  75 +       cfghi |= DWC_CFGH_PROTCTL(dw->pdata->protctl);
  76
  77         /* Set polarity of handshake interface */
  78         cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0;
  79 --- a/drivers/dma/dw/platform.c
  80 +++ b/drivers/dma/dw/platform.c
  81 @@ -162,6 +162,12 @@ dw_dma_parse_dt(struct platform_device *
  82                         pdata->multi_block[tmp] = 1;
  83         }
  84
  85 +       if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) {
  86 +               if (tmp > CHAN_PROTCTL_MASK)
  87 +                       return NULL;
  88 +               pdata->protctl = tmp;
  89 +       }
  90 +
  91         return pdata;
  92  }
  93  #else
  94 --- a/drivers/dma/dw/regs.h
  95 +++ b/drivers/dma/dw/regs.h
  96 @@ -200,6 +200,10 @@ enum dw_dma_msize {
  97  #define DWC_CFGH_FCMODE                (1 << 0)
  98  #define DWC_CFGH_FIFO_MODE     (1 << 1)
  99  #define DWC_CFGH_PROTCTL(x)    ((x) << 2)
 100 +#define DWC_CFGH_PROTCTL_DATA  (0 << 2)        /* data access - always set */
 101 +#define DWC_CFGH_PROTCTL_PRIV  (1 << 2)        /* privileged -> AHB HPROT[1] */
 102 +#define DWC_CFGH_PROTCTL_BUFFER        (2 << 2)        /* bufferable -> AHB HPROT[2] */
 103 +#define DWC_CFGH_PROTCTL_CACHE (4 << 2)        /* cacheable  -> AHB HPROT[3] */
 104  #define DWC_CFGH_DS_UPD_EN     (1 << 5)
 105  #define DWC_CFGH_SS_UPD_EN     (1 << 6)
 106  #define DWC_CFGH_SRC_PER(x)    ((x) << 7)
 107 --- a/include/linux/platform_data/dma-dw.h
 108 +++ b/include/linux/platform_data/dma-dw.h
 109 @@ -49,6 +49,7 @@ struct dw_dma_slave {
 110   * @data_width: Maximum data width supported by hardware per AHB master
 111   *             (in bytes, power of 2)
 112   * @multi_block: Multi block transfers supported by hardware per channel.
 113 + * @protctl:   Protection control signals setting per channel.
 114   */
 115  struct dw_dma_platform_data {
 116         unsigned int    nr_channels;
 117 @@ -65,6 +66,11 @@ struct dw_dma_platform_data {
 118         unsigned char   nr_masters;
 119         unsigned char   data_width[DW_DMA_MAX_NR_MASTERS];
 120         unsigned char   multi_block[DW_DMA_MAX_NR_CHANNELS];
 121 +#define CHAN_PROTCTL_PRIVILEGED                BIT(0)
 122 +#define CHAN_PROTCTL_BUFFERABLE                BIT(1)
 123 +#define CHAN_PROTCTL_CACHEABLE         BIT(2)
 124 +#define        CHAN_PROTCTL_MASK               GENMASK(2, 0)
 125 +       unsigned char   protctl;
 126  };
 127
 128  #endif /* _PLATFORM_DATA_DMA_DW_H */