b7528e9f716b55b629208e300d09a9f4533307ba
[openwrt/staging/981213.git] /
1 From 9f66e1dd82e3186aee95282657512ca2aef1afe0 Mon Sep 17 00:00:00 2001
2 From: Linus Walleij <linus.walleij@linaro.org>
3 Date: Wed, 19 Oct 2022 21:34:49 +0200
4 Subject: [PATCH] ARM: dts: bcm53016: Add devicetree for D-Link DWL-8610AP
5
6 This adds a device tree for the BCM53016-based D-Link DWL-8610AP
7 access point wireless router.
8
9 The TRX-format partitions had to be named "firmware" due to
10 an OpenWrt patch that only accepts parting such nodes if they
11 are named "firmware".
12
13 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
14 Link: https://lore.kernel.org/r/20221019193449.3036010-2-linus.walleij@linaro.org
15 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
16 ---
17 arch/arm/boot/dts/Makefile | 1 +
18 .../boot/dts/bcm53016-dlink-dwl-8610ap.dts | 131 ++++++++++++++++++
19 2 files changed, 132 insertions(+)
20 create mode 100644 arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts
21
22 --- a/arch/arm/boot/dts/Makefile
23 +++ b/arch/arm/boot/dts/Makefile
24 @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
25 bcm47094-netgear-r8500.dtb \
26 bcm47094-phicomm-k3.dtb \
27 bcm53015-meraki-mr26.dtb \
28 + bcm53016-dlink-dwl-8610ap.dtb \
29 bcm53016-meraki-mr32.dtb \
30 bcm94708.dtb \
31 bcm94709.dtb \
32 --- /dev/null
33 +++ b/arch/arm/boot/dts/bcm53016-dlink-dwl-8610ap.dts
34 @@ -0,0 +1,131 @@
35 +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
36 +/dts-v1/;
37 +
38 +#include "bcm4709.dtsi"
39 +#include "bcm5301x-nand-cs0-bch8.dtsi"
40 +#include <dt-bindings/leds/common.h>
41 +#include <dt-bindings/input/input.h>
42 +
43 +/ {
44 + model = "D-Link DWL-8610AP";
45 + compatible = "dlink,dwl-8610ap", "brcm,bcm53016", "brcm,bcm4708";
46 +
47 + memory@0 {
48 + device_type = "memory";
49 + /* 512 MB RAM in 2 x Macronix D9PSH chips */
50 + reg = <0x00000000 0x08000000>,
51 + <0x88000000 0x08000000>;
52 + };
53 +
54 + leds {
55 + compatible = "gpio-leds";
56 +
57 + power {
58 + function = LED_FUNCTION_POWER;
59 + color = <LED_COLOR_ID_GREEN>;
60 + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
61 + default-state = "on";
62 + };
63 +
64 + diag {
65 + /* Actually "diag" unclear what this means */
66 + function = LED_FUNCTION_INDICATOR;
67 + color = <LED_COLOR_ID_RED>;
68 + gpios = <&chipcommon 1 GPIO_ACTIVE_LOW>;
69 + default-state = "on";
70 + linux,default-trigger = "heartbeat";
71 + };
72 +
73 + wlan-2g {
74 + function = LED_FUNCTION_WLAN;
75 + color = <LED_COLOR_ID_GREEN>;
76 + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
77 + };
78 +
79 + wlan-5g {
80 + function = LED_FUNCTION_WLAN;
81 + color = <LED_COLOR_ID_GREEN>;
82 + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
83 + };
84 + };
85 +
86 + gpio_keys {
87 + compatible = "gpio-keys";
88 +
89 + button-reset {
90 + debounce-interval = <100>;
91 + wakeup-source;
92 + linux,code = <KEY_RESTART>;
93 + label = "reset";
94 + /* This GPIO is actually stored in NVRAM, but it's not gonna change */
95 + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
96 + };
97 + };
98 +
99 + /*
100 + * Flash memory at 0x1e000000-0x1fffffff
101 + * Macronix 32 64KB blocks; total size 2MB, same that can be
102 + * found attached to the spi_nor SPI controller.
103 + */
104 + nvram@1e080000 {
105 + compatible = "brcm,nvram";
106 + reg = <0x1e080000 0x00020000>;
107 +
108 + et0macaddr: et0macaddr {
109 + };
110 +
111 + et1macaddr: et1macaddr {
112 + };
113 + };
114 +};
115 +
116 +&gmac0 {
117 + nvmem-cells = <&et0macaddr>;
118 + nvmem-cell-names = "mac-address";
119 +};
120 +
121 +&gmac1 {
122 + nvmem-cells = <&et1macaddr>;
123 + nvmem-cell-names = "mac-address";
124 +};
125 +
126 +&spi_nor {
127 + /* Serial SPI NOR Flash MX 25L1606E */
128 + status = "okay";
129 +};
130 +
131 +&nandcs {
132 + /*
133 + * Spansion S34ML01G100TFI00 128 MB NAND Flash memory
134 + *
135 + * This ECC is a bit unorthodox but it is what the stock firmware
136 + * is using, so to be able to mount the original partitions
137 + * this is necessary.
138 + */
139 + nand-ecc-strength = <5>;
140 + partitions {
141 + compatible = "fixed-partitions";
142 + #address-cells = <1>;
143 + #size-cells = <1>;
144 +
145 + /* This is named nflash1.trx in CFE */
146 + trx@0 {
147 + label = "firmware";
148 + reg = <0x00000000 0x02800000>;
149 + compatible = "brcm,trx";
150 + };
151 +
152 + /* This is named nflash1.trx2 in CFE */
153 + trx2@2800000 {
154 + label = "firmware2";
155 + reg = <0x02800000 0x02800000>;
156 + compatible = "brcm,trx";
157 + };
158 +
159 + /* This is named nflash1.rwfs in CFE */
160 + free@5000000 {
161 + label = "free";
162 + reg = <0x05000000 0x03000000>;
163 + };
164 + };
165 +};