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1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
2 Subject: [PATCH] net: phy: cherry-pick Broadcom drivers updates from v4.10
3
4 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
5 ---
6
7 --- a/drivers/net/phy/broadcom.c
8 +++ b/drivers/net/phy/broadcom.c
9 @@ -18,7 +18,7 @@
10 #include <linux/module.h>
11 #include <linux/phy.h>
12 #include <linux/brcmphy.h>
13 -
14 +#include <linux/of.h>
15
16 #define BRCM_PHY_MODEL(phydev) \
17 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
18 @@ -30,9 +30,32 @@ MODULE_DESCRIPTION("Broadcom PHY driver"
19 MODULE_AUTHOR("Maciej W. Rozycki");
20 MODULE_LICENSE("GPL");
21
22 -static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
23 +static int bcm54810_config(struct phy_device *phydev)
24 {
25 - return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
26 + int rc, val;
27 +
28 + val = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
29 + val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
30 + rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
31 + val);
32 + if (rc < 0)
33 + return rc;
34 +
35 + val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
36 + val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
37 + val |= MII_BCM54XX_AUXCTL_MISC_WREN;
38 + rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
39 + val);
40 + if (rc < 0)
41 + return rc;
42 +
43 + val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
44 + val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
45 + rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
46 + if (rc < 0)
47 + return rc;
48 +
49 + return 0;
50 }
51
52 /* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
53 @@ -207,6 +230,12 @@ static int bcm54xx_config_init(struct ph
54 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
55 bcm54xx_adjust_rxrefclk(phydev);
56
57 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
58 + err = bcm54810_config(phydev);
59 + if (err)
60 + return err;
61 + }
62 +
63 bcm54xx_phydsp_config(phydev);
64
65 return 0;
66 @@ -304,6 +333,7 @@ static int bcm5482_read_status(struct ph
67
68 static int bcm5481_config_aneg(struct phy_device *phydev)
69 {
70 + struct device_node *np = phydev->dev.of_node;
71 int ret;
72
73 /* Aneg firsly. */
74 @@ -334,6 +364,49 @@ static int bcm5481_config_aneg(struct ph
75 phy_write(phydev, 0x18, reg);
76 }
77
78 + if (of_property_read_bool(np, "enet-phy-lane-swap")) {
79 + /* Lane Swap - Undocumented register...magic! */
80 + ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
81 + 0x11B);
82 + if (ret < 0)
83 + return ret;
84 + }
85 +
86 + return ret;
87 +}
88 +
89 +static int bcm54612e_config_aneg(struct phy_device *phydev)
90 +{
91 + int ret;
92 +
93 + /* First, auto-negotiate. */
94 + ret = genphy_config_aneg(phydev);
95 +
96 + /* Clear TX internal delay unless requested. */
97 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
98 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
99 + /* Disable TXD to GTXCLK clock delay (default set) */
100 + /* Bit 9 is the only field in shadow register 00011 */
101 + bcm_phy_write_shadow(phydev, 0x03, 0);
102 + }
103 +
104 + /* Clear RX internal delay unless requested. */
105 + if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
106 + (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
107 + u16 reg;
108 +
109 + /* Errata: reads require filling in the write selector field */
110 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
111 + MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC);
112 + reg = phy_read(phydev, MII_BCM54XX_AUX_CTL);
113 + /* Disable RXD to RXC delay (default set) */
114 + reg &= ~MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW;
115 + /* Clear shadow selector field */
116 + reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
117 + bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
118 + MII_BCM54XX_AUXCTL_MISC_WREN | reg);
119 + }
120 +
121 return ret;
122 }
123
124 @@ -488,6 +561,19 @@ static struct phy_driver broadcom_driver
125 .config_intr = bcm_phy_config_intr,
126 .driver = { .owner = THIS_MODULE },
127 }, {
128 + .phy_id = PHY_ID_BCM54612E,
129 + .phy_id_mask = 0xfffffff0,
130 + .name = "Broadcom BCM54612E",
131 + .features = PHY_GBIT_FEATURES |
132 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
133 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
134 + .config_init = bcm54xx_config_init,
135 + .config_aneg = bcm54612e_config_aneg,
136 + .read_status = genphy_read_status,
137 + .ack_interrupt = bcm_phy_ack_intr,
138 + .config_intr = bcm_phy_config_intr,
139 + .driver = { .owner = THIS_MODULE },
140 +}, {
141 .phy_id = PHY_ID_BCM54616S,
142 .phy_id_mask = 0xfffffff0,
143 .name = "Broadcom BCM54616S",
144 @@ -527,6 +613,19 @@ static struct phy_driver broadcom_driver
145 .config_intr = bcm_phy_config_intr,
146 .driver = { .owner = THIS_MODULE },
147 }, {
148 + .phy_id = PHY_ID_BCM54810,
149 + .phy_id_mask = 0xfffffff0,
150 + .name = "Broadcom BCM54810",
151 + .features = PHY_GBIT_FEATURES |
152 + SUPPORTED_Pause | SUPPORTED_Asym_Pause,
153 + .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
154 + .config_init = bcm54xx_config_init,
155 + .config_aneg = bcm5481_config_aneg,
156 + .read_status = genphy_read_status,
157 + .ack_interrupt = bcm_phy_ack_intr,
158 + .config_intr = bcm_phy_config_intr,
159 + .driver = { .owner = THIS_MODULE },
160 +}, {
161 .phy_id = PHY_ID_BCM5482,
162 .phy_id_mask = 0xfffffff0,
163 .name = "Broadcom BCM5482",
164 @@ -612,9 +711,11 @@ static struct mdio_device_id __maybe_unu
165 { PHY_ID_BCM5411, 0xfffffff0 },
166 { PHY_ID_BCM5421, 0xfffffff0 },
167 { PHY_ID_BCM5461, 0xfffffff0 },
168 + { PHY_ID_BCM54612E, 0xfffffff0 },
169 { PHY_ID_BCM54616S, 0xfffffff0 },
170 { PHY_ID_BCM5464, 0xfffffff0 },
171 { PHY_ID_BCM5481, 0xfffffff0 },
172 + { PHY_ID_BCM54810, 0xfffffff0 },
173 { PHY_ID_BCM5482, 0xfffffff0 },
174 { PHY_ID_BCM50610, 0xfffffff0 },
175 { PHY_ID_BCM50610M, 0xfffffff0 },
176 --- a/include/linux/brcmphy.h
177 +++ b/include/linux/brcmphy.h
178 @@ -13,11 +13,13 @@
179 #define PHY_ID_BCM5241 0x0143bc30
180 #define PHY_ID_BCMAC131 0x0143bc70
181 #define PHY_ID_BCM5481 0x0143bca0
182 +#define PHY_ID_BCM54810 0x03625d00
183 #define PHY_ID_BCM5482 0x0143bcb0
184 #define PHY_ID_BCM5411 0x00206070
185 #define PHY_ID_BCM5421 0x002060e0
186 #define PHY_ID_BCM5464 0x002060b0
187 #define PHY_ID_BCM5461 0x002060c0
188 +#define PHY_ID_BCM54612E 0x03625e60
189 #define PHY_ID_BCM54616S 0x03625d10
190 #define PHY_ID_BCM57780 0x03625d90
191
192 @@ -52,6 +54,7 @@
193 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
194 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
195 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
196 +
197 /* Broadcom BCM7xxx specific workarounds */
198 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
199 #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
200 @@ -102,11 +105,14 @@
201 #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800
202
203 #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000
204 +#define MII_BCM54XX_AUXCTL_MISC_RXD_RXC_SKEW 0x0100
205 #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200
206 #define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC 0x7000
207 #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
208 +#define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12
209 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN (1 << 8)
210
211 -#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x0000
212 +#define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007
213
214 /*
215 * Broadcom LED source encodings. These are used in BCM5461, BCM5481,
216 @@ -186,6 +192,12 @@
217 #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
218 #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
219
220 +/* BCM54810 Registers */
221 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
222 +#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0)
223 +#define BCM54810_SHD_CLK_CTL 0x3
224 +#define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9)
225 +
226
227 /*****************************************************************************/
228 /* Fast Ethernet Transceiver definitions. */
229 --- a/drivers/net/phy/Kconfig
230 +++ b/drivers/net/phy/Kconfig
231 @@ -77,7 +77,7 @@ config BROADCOM_PHY
232 select BCM_NET_PHYLIB
233 ---help---
234 Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
235 - BCM5481 and BCM5482 PHYs.
236 + BCM5481, BCM54810 and BCM5482 PHYs.
237
238 config BCM_CYGNUS_PHY
239 tristate "Drivers for Broadcom Cygnus SoC internal PHY"
240 --- a/drivers/net/phy/bcm-phy-lib.c
241 +++ b/drivers/net/phy/bcm-phy-lib.c
242 @@ -50,6 +50,23 @@ int bcm_phy_read_exp(struct phy_device *
243 }
244 EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
245
246 +int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
247 +{
248 + /* The register must be written to both the Shadow Register Select and
249 + * the Shadow Read Register Selector
250 + */
251 + phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
252 + regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
253 + return phy_read(phydev, MII_BCM54XX_AUX_CTL);
254 +}
255 +EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
256 +
257 +int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
258 +{
259 + return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
260 +}
261 +EXPORT_SYMBOL(bcm54xx_auxctl_write);
262 +
263 int bcm_phy_write_misc(struct phy_device *phydev,
264 u16 reg, u16 chl, u16 val)
265 {
266 --- a/drivers/net/phy/bcm-phy-lib.h
267 +++ b/drivers/net/phy/bcm-phy-lib.h
268 @@ -19,6 +19,9 @@
269 int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val);
270 int bcm_phy_read_exp(struct phy_device *phydev, u16 reg);
271
272 +int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val);
273 +int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum);
274 +
275 int bcm_phy_write_misc(struct phy_device *phydev,
276 u16 reg, u16 chl, u16 value);
277 int bcm_phy_read_misc(struct phy_device *phydev,
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