git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From b7aa228813bdf014d6ad173ca3abfced30f1ed37 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Wed, 17 Jun 2020 12:50:40 +0200
   4 Subject: [PATCH 8/9] mips: bmips: dts: add BCM63268 reset controller support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 BCM63268 SoCs have a reset controller for certain components.
  10
  11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  12 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  15 ---
  16  arch/mips/boot/dts/brcm/bcm63268.dtsi      |  6 +++++
  17  include/dt-bindings/reset/bcm63268-reset.h | 26 ++++++++++++++++++++++
  18  2 files changed, 32 insertions(+)
  19  create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
  20
  21 --- a/arch/mips/boot/dts/brcm/bcm63268.dtsi
  22 +++ b/arch/mips/boot/dts/brcm/bcm63268.dtsi
  23 @@ -70,6 +70,12 @@
  24                         mask = <0x1>;
  25                 };
  26
  27 +               periph_rst: reset-controller@10000010 {
  28 +                       compatible = "brcm,bcm6345-reset";
  29 +                       reg = <0x10000010 0x4>;
  30 +                       #reset-cells = <1>;
  31 +               };
  32 +
  33                 periph_intc: interrupt-controller@10000020 {
  34                         compatible = "brcm,bcm6345-l1-intc";
  35                         reg = <0x10000020 0x20>,
  36 --- /dev/null
  37 +++ b/include/dt-bindings/reset/bcm63268-reset.h
  38 @@ -0,0 +1,26 @@
  39 +/* SPDX-License-Identifier: GPL-2.0+ */
  40 +
  41 +#ifndef __DT_BINDINGS_RESET_BCM63268_H
  42 +#define __DT_BINDINGS_RESET_BCM63268_H
  43 +
  44 +#define BCM63268_RST_SPI       0
  45 +#define BCM63268_RST_IPSEC     1
  46 +#define BCM63268_RST_EPHY      2
  47 +#define BCM63268_RST_SAR       3
  48 +#define BCM63268_RST_ENETSW    4
  49 +#define BCM63268_RST_USBS      5
  50 +#define BCM63268_RST_USBH      6
  51 +#define BCM63268_RST_PCM       7
  52 +#define BCM63268_RST_PCIE_CORE 8
  53 +#define BCM63268_RST_PCIE      9
  54 +#define BCM63268_RST_PCIE_EXT  10
  55 +#define BCM63268_RST_WLAN_SHIM 11
  56 +#define BCM63268_RST_DDR_PHY   12
  57 +#define BCM63268_RST_FAP0      13
  58 +#define BCM63268_RST_WLAN_UBUS 14
  59 +#define BCM63268_RST_DECT      15
  60 +#define BCM63268_RST_FAP1      16
  61 +#define BCM63268_RST_PCIE_HARD 17
  62 +#define BCM63268_RST_GPHY      18
  63 +
  64 +#endif /* __DT_BINDINGS_RESET_BCM63268_H */