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1 From 1416a9b2ba710d31954131c06d46f298e340aa2c Mon Sep 17 00:00:00 2001
2 From: Heiner Kallweit <hkallweit1@gmail.com>
3 Date: Sat, 11 Jan 2025 21:50:19 +0100
4 Subject: [PATCH] net: phy: move realtek PHY driver to its own subdirectory
5
6 In preparation of adding a source file with hwmon support, move the
7 Realtek PHY driver to its own subdirectory and rename realtek.c to
8 realtek_main.c.
9
10 Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
12 Link: https://patch.msgid.link/c566551b-c915-4e34-9b33-129a6ddd6e4c@gmail.com
13 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
14 ---
15 drivers/net/phy/Kconfig | 5 +----
16 drivers/net/phy/Makefile | 2 +-
17 drivers/net/phy/realtek/Kconfig | 5 +++++
18 drivers/net/phy/realtek/Makefile | 3 +++
19 drivers/net/phy/{realtek.c => realtek/realtek_main.c} | 0
20 5 files changed, 10 insertions(+), 5 deletions(-)
21 create mode 100644 drivers/net/phy/realtek/Kconfig
22 create mode 100644 drivers/net/phy/realtek/Makefile
23 rename drivers/net/phy/{realtek.c => realtek/realtek_main.c} (100%)
24
25 --- a/drivers/net/phy/Kconfig
26 +++ b/drivers/net/phy/Kconfig
27 @@ -325,10 +325,7 @@ config QSEMI_PHY
28 help
29 Currently supports the qs6612
30
31 -config REALTEK_PHY
32 - tristate "Realtek PHYs"
33 - help
34 - Supports the Realtek 821x PHY.
35 +source "drivers/net/phy/realtek/Kconfig"
36
37 config RENESAS_PHY
38 tristate "Renesas PHYs"
39 --- a/drivers/net/phy/Makefile
40 +++ b/drivers/net/phy/Makefile
41 @@ -83,7 +83,7 @@ obj-$(CONFIG_NXP_CBTX_PHY) += nxp-cbtx.o
42 obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
43 obj-y += qcom/
44 obj-$(CONFIG_QSEMI_PHY) += qsemi.o
45 -obj-$(CONFIG_REALTEK_PHY) += realtek.o
46 +obj-$(CONFIG_REALTEK_PHY) += realtek/
47 obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
48 obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o
49 obj-$(CONFIG_SMSC_PHY) += smsc.o
50 --- /dev/null
51 +++ b/drivers/net/phy/realtek/Kconfig
52 @@ -0,0 +1,5 @@
53 +# SPDX-License-Identifier: GPL-2.0-only
54 +config REALTEK_PHY
55 + tristate "Realtek PHYs"
56 + help
57 + Currently supports RTL821x/RTL822x and fast ethernet PHYs
58 --- /dev/null
59 +++ b/drivers/net/phy/realtek/Makefile
60 @@ -0,0 +1,3 @@
61 +# SPDX-License-Identifier: GPL-2.0
62 +realtek-y += realtek_main.o
63 +obj-$(CONFIG_REALTEK_PHY) += realtek.o
64 --- a/drivers/net/phy/realtek.c
65 +++ /dev/null
66 @@ -1,1590 +0,0 @@
67 -// SPDX-License-Identifier: GPL-2.0+
68 -/* drivers/net/phy/realtek.c
69 - *
70 - * Driver for Realtek PHYs
71 - *
72 - * Author: Johnson Leung <r58129@freescale.com>
73 - *
74 - * Copyright (c) 2004 Freescale Semiconductor, Inc.
75 - */
76 -#include <linux/bitops.h>
77 -#include <linux/of.h>
78 -#include <linux/phy.h>
79 -#include <linux/module.h>
80 -#include <linux/delay.h>
81 -#include <linux/clk.h>
82 -
83 -#define RTL821x_PHYSR 0x11
84 -#define RTL821x_PHYSR_DUPLEX BIT(13)
85 -#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
86 -
87 -#define RTL821x_INER 0x12
88 -#define RTL8211B_INER_INIT 0x6400
89 -#define RTL8211E_INER_LINK_STATUS BIT(10)
90 -#define RTL8211F_INER_LINK_STATUS BIT(4)
91 -
92 -#define RTL821x_INSR 0x13
93 -
94 -#define RTL821x_EXT_PAGE_SELECT 0x1e
95 -#define RTL821x_PAGE_SELECT 0x1f
96 -
97 -#define RTL8211F_PHYCR1 0x18
98 -#define RTL8211F_PHYCR2 0x19
99 -#define RTL8211F_INSR 0x1d
100 -
101 -#define RTL8211F_LEDCR 0x10
102 -#define RTL8211F_LEDCR_MODE BIT(15)
103 -#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
104 -#define RTL8211F_LEDCR_LINK_1000 BIT(3)
105 -#define RTL8211F_LEDCR_LINK_100 BIT(1)
106 -#define RTL8211F_LEDCR_LINK_10 BIT(0)
107 -#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
108 -#define RTL8211F_LEDCR_SHIFT 5
109 -
110 -#define RTL8211F_TX_DELAY BIT(8)
111 -#define RTL8211F_RX_DELAY BIT(3)
112 -
113 -#define RTL8211F_ALDPS_PLL_OFF BIT(1)
114 -#define RTL8211F_ALDPS_ENABLE BIT(2)
115 -#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
116 -
117 -#define RTL8211E_CTRL_DELAY BIT(13)
118 -#define RTL8211E_TX_DELAY BIT(12)
119 -#define RTL8211E_RX_DELAY BIT(11)
120 -
121 -#define RTL8211F_CLKOUT_EN BIT(0)
122 -
123 -#define RTL8201F_ISR 0x1e
124 -#define RTL8201F_ISR_ANERR BIT(15)
125 -#define RTL8201F_ISR_DUPLEX BIT(13)
126 -#define RTL8201F_ISR_LINK BIT(11)
127 -#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
128 - RTL8201F_ISR_DUPLEX | \
129 - RTL8201F_ISR_LINK)
130 -#define RTL8201F_IER 0x13
131 -
132 -#define RTL822X_VND1_SERDES_OPTION 0x697a
133 -#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
134 -#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
135 -#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
136 -
137 -#define RTL822X_VND1_SERDES_CTRL3 0x7580
138 -#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
139 -#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
140 -#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
141 -
142 -/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
143 - * is set, they cannot be accessed by C45-over-C22.
144 - */
145 -#define RTL822X_VND2_GBCR 0xa412
146 -
147 -#define RTL822X_VND2_GANLPAR 0xa414
148 -
149 -#define RTL8366RB_POWER_SAVE 0x15
150 -#define RTL8366RB_POWER_SAVE_ON BIT(12)
151 -
152 -#define RTL9000A_GINMR 0x14
153 -#define RTL9000A_GINMR_LINK_STATUS BIT(4)
154 -
155 -#define RTL_VND2_PHYSR 0xa434
156 -#define RTL_VND2_PHYSR_DUPLEX BIT(3)
157 -#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
158 -#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
159 -#define RTL_VND2_PHYSR_MASTER BIT(11)
160 -#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
161 -
162 -#define RTL_GENERIC_PHYID 0x001cc800
163 -#define RTL_8211FVD_PHYID 0x001cc878
164 -#define RTL_8221B 0x001cc840
165 -#define RTL_8221B_VB_CG 0x001cc849
166 -#define RTL_8221B_VN_CG 0x001cc84a
167 -#define RTL_8251B 0x001cc862
168 -
169 -#define RTL8211F_LED_COUNT 3
170 -
171 -MODULE_DESCRIPTION("Realtek PHY driver");
172 -MODULE_AUTHOR("Johnson Leung");
173 -MODULE_LICENSE("GPL");
174 -
175 -struct rtl821x_priv {
176 - u16 phycr1;
177 - u16 phycr2;
178 - bool has_phycr2;
179 - struct clk *clk;
180 -};
181 -
182 -static int rtl821x_read_page(struct phy_device *phydev)
183 -{
184 - return __phy_read(phydev, RTL821x_PAGE_SELECT);
185 -}
186 -
187 -static int rtl821x_write_page(struct phy_device *phydev, int page)
188 -{
189 - return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
190 -}
191 -
192 -static int rtl821x_probe(struct phy_device *phydev)
193 -{
194 - struct device *dev = &phydev->mdio.dev;
195 - struct rtl821x_priv *priv;
196 - u32 phy_id = phydev->drv->phy_id;
197 - int ret;
198 -
199 - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
200 - if (!priv)
201 - return -ENOMEM;
202 -
203 - priv->clk = devm_clk_get_optional_enabled(dev, NULL);
204 - if (IS_ERR(priv->clk))
205 - return dev_err_probe(dev, PTR_ERR(priv->clk),
206 - "failed to get phy clock\n");
207 -
208 - ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
209 - if (ret < 0)
210 - return ret;
211 -
212 - priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
213 - if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
214 - priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
215 -
216 - priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
217 - if (priv->has_phycr2) {
218 - ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
219 - if (ret < 0)
220 - return ret;
221 -
222 - priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
223 - if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
224 - priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
225 - }
226 -
227 - phydev->priv = priv;
228 -
229 - return 0;
230 -}
231 -
232 -static int rtl8201_ack_interrupt(struct phy_device *phydev)
233 -{
234 - int err;
235 -
236 - err = phy_read(phydev, RTL8201F_ISR);
237 -
238 - return (err < 0) ? err : 0;
239 -}
240 -
241 -static int rtl821x_ack_interrupt(struct phy_device *phydev)
242 -{
243 - int err;
244 -
245 - err = phy_read(phydev, RTL821x_INSR);
246 -
247 - return (err < 0) ? err : 0;
248 -}
249 -
250 -static int rtl8211f_ack_interrupt(struct phy_device *phydev)
251 -{
252 - int err;
253 -
254 - err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
255 -
256 - return (err < 0) ? err : 0;
257 -}
258 -
259 -static int rtl8201_config_intr(struct phy_device *phydev)
260 -{
261 - u16 val;
262 - int err;
263 -
264 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
265 - err = rtl8201_ack_interrupt(phydev);
266 - if (err)
267 - return err;
268 -
269 - val = BIT(13) | BIT(12) | BIT(11);
270 - err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
271 - } else {
272 - val = 0;
273 - err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
274 - if (err)
275 - return err;
276 -
277 - err = rtl8201_ack_interrupt(phydev);
278 - }
279 -
280 - return err;
281 -}
282 -
283 -static int rtl8211b_config_intr(struct phy_device *phydev)
284 -{
285 - int err;
286 -
287 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
288 - err = rtl821x_ack_interrupt(phydev);
289 - if (err)
290 - return err;
291 -
292 - err = phy_write(phydev, RTL821x_INER,
293 - RTL8211B_INER_INIT);
294 - } else {
295 - err = phy_write(phydev, RTL821x_INER, 0);
296 - if (err)
297 - return err;
298 -
299 - err = rtl821x_ack_interrupt(phydev);
300 - }
301 -
302 - return err;
303 -}
304 -
305 -static int rtl8211e_config_intr(struct phy_device *phydev)
306 -{
307 - int err;
308 -
309 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
310 - err = rtl821x_ack_interrupt(phydev);
311 - if (err)
312 - return err;
313 -
314 - err = phy_write(phydev, RTL821x_INER,
315 - RTL8211E_INER_LINK_STATUS);
316 - } else {
317 - err = phy_write(phydev, RTL821x_INER, 0);
318 - if (err)
319 - return err;
320 -
321 - err = rtl821x_ack_interrupt(phydev);
322 - }
323 -
324 - return err;
325 -}
326 -
327 -static int rtl8211f_config_intr(struct phy_device *phydev)
328 -{
329 - u16 val;
330 - int err;
331 -
332 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
333 - err = rtl8211f_ack_interrupt(phydev);
334 - if (err)
335 - return err;
336 -
337 - val = RTL8211F_INER_LINK_STATUS;
338 - err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
339 - } else {
340 - val = 0;
341 - err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
342 - if (err)
343 - return err;
344 -
345 - err = rtl8211f_ack_interrupt(phydev);
346 - }
347 -
348 - return err;
349 -}
350 -
351 -static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
352 -{
353 - int irq_status;
354 -
355 - irq_status = phy_read(phydev, RTL8201F_ISR);
356 - if (irq_status < 0) {
357 - phy_error(phydev);
358 - return IRQ_NONE;
359 - }
360 -
361 - if (!(irq_status & RTL8201F_ISR_MASK))
362 - return IRQ_NONE;
363 -
364 - phy_trigger_machine(phydev);
365 -
366 - return IRQ_HANDLED;
367 -}
368 -
369 -static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
370 -{
371 - int irq_status, irq_enabled;
372 -
373 - irq_status = phy_read(phydev, RTL821x_INSR);
374 - if (irq_status < 0) {
375 - phy_error(phydev);
376 - return IRQ_NONE;
377 - }
378 -
379 - irq_enabled = phy_read(phydev, RTL821x_INER);
380 - if (irq_enabled < 0) {
381 - phy_error(phydev);
382 - return IRQ_NONE;
383 - }
384 -
385 - if (!(irq_status & irq_enabled))
386 - return IRQ_NONE;
387 -
388 - phy_trigger_machine(phydev);
389 -
390 - return IRQ_HANDLED;
391 -}
392 -
393 -static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
394 -{
395 - int irq_status;
396 -
397 - irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
398 - if (irq_status < 0) {
399 - phy_error(phydev);
400 - return IRQ_NONE;
401 - }
402 -
403 - if (!(irq_status & RTL8211F_INER_LINK_STATUS))
404 - return IRQ_NONE;
405 -
406 - phy_trigger_machine(phydev);
407 -
408 - return IRQ_HANDLED;
409 -}
410 -
411 -static int rtl8211_config_aneg(struct phy_device *phydev)
412 -{
413 - int ret;
414 -
415 - ret = genphy_config_aneg(phydev);
416 - if (ret < 0)
417 - return ret;
418 -
419 - /* Quirk was copied from vendor driver. Unfortunately it includes no
420 - * description of the magic numbers.
421 - */
422 - if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
423 - phy_write(phydev, 0x17, 0x2138);
424 - phy_write(phydev, 0x0e, 0x0260);
425 - } else {
426 - phy_write(phydev, 0x17, 0x2108);
427 - phy_write(phydev, 0x0e, 0x0000);
428 - }
429 -
430 - return 0;
431 -}
432 -
433 -static int rtl8211c_config_init(struct phy_device *phydev)
434 -{
435 - /* RTL8211C has an issue when operating in Gigabit slave mode */
436 - return phy_set_bits(phydev, MII_CTRL1000,
437 - CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
438 -}
439 -
440 -static int rtl8211f_config_init(struct phy_device *phydev)
441 -{
442 - struct rtl821x_priv *priv = phydev->priv;
443 - struct device *dev = &phydev->mdio.dev;
444 - u16 val_txdly, val_rxdly;
445 - int ret;
446 -
447 - ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
448 - RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
449 - priv->phycr1);
450 - if (ret < 0) {
451 - dev_err(dev, "aldps mode configuration failed: %pe\n",
452 - ERR_PTR(ret));
453 - return ret;
454 - }
455 -
456 - switch (phydev->interface) {
457 - case PHY_INTERFACE_MODE_RGMII:
458 - val_txdly = 0;
459 - val_rxdly = 0;
460 - break;
461 -
462 - case PHY_INTERFACE_MODE_RGMII_RXID:
463 - val_txdly = 0;
464 - val_rxdly = RTL8211F_RX_DELAY;
465 - break;
466 -
467 - case PHY_INTERFACE_MODE_RGMII_TXID:
468 - val_txdly = RTL8211F_TX_DELAY;
469 - val_rxdly = 0;
470 - break;
471 -
472 - case PHY_INTERFACE_MODE_RGMII_ID:
473 - val_txdly = RTL8211F_TX_DELAY;
474 - val_rxdly = RTL8211F_RX_DELAY;
475 - break;
476 -
477 - default: /* the rest of the modes imply leaving delay as is. */
478 - return 0;
479 - }
480 -
481 - ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
482 - val_txdly);
483 - if (ret < 0) {
484 - dev_err(dev, "Failed to update the TX delay register\n");
485 - return ret;
486 - } else if (ret) {
487 - dev_dbg(dev,
488 - "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
489 - val_txdly ? "Enabling" : "Disabling");
490 - } else {
491 - dev_dbg(dev,
492 - "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
493 - val_txdly ? "enabled" : "disabled");
494 - }
495 -
496 - ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
497 - val_rxdly);
498 - if (ret < 0) {
499 - dev_err(dev, "Failed to update the RX delay register\n");
500 - return ret;
501 - } else if (ret) {
502 - dev_dbg(dev,
503 - "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
504 - val_rxdly ? "Enabling" : "Disabling");
505 - } else {
506 - dev_dbg(dev,
507 - "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
508 - val_rxdly ? "enabled" : "disabled");
509 - }
510 -
511 - if (priv->has_phycr2) {
512 - ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
513 - RTL8211F_CLKOUT_EN, priv->phycr2);
514 - if (ret < 0) {
515 - dev_err(dev, "clkout configuration failed: %pe\n",
516 - ERR_PTR(ret));
517 - return ret;
518 - }
519 -
520 - return genphy_soft_reset(phydev);
521 - }
522 -
523 - return 0;
524 -}
525 -
526 -static int rtl821x_suspend(struct phy_device *phydev)
527 -{
528 - struct rtl821x_priv *priv = phydev->priv;
529 - int ret = 0;
530 -
531 - if (!phydev->wol_enabled) {
532 - ret = genphy_suspend(phydev);
533 -
534 - if (ret)
535 - return ret;
536 -
537 - clk_disable_unprepare(priv->clk);
538 - }
539 -
540 - return ret;
541 -}
542 -
543 -static int rtl821x_resume(struct phy_device *phydev)
544 -{
545 - struct rtl821x_priv *priv = phydev->priv;
546 - int ret;
547 -
548 - if (!phydev->wol_enabled)
549 - clk_prepare_enable(priv->clk);
550 -
551 - ret = genphy_resume(phydev);
552 - if (ret < 0)
553 - return ret;
554 -
555 - msleep(20);
556 -
557 - return 0;
558 -}
559 -
560 -static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
561 - unsigned long rules)
562 -{
563 - const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
564 - BIT(TRIGGER_NETDEV_LINK_100) |
565 - BIT(TRIGGER_NETDEV_LINK_1000) |
566 - BIT(TRIGGER_NETDEV_RX) |
567 - BIT(TRIGGER_NETDEV_TX);
568 -
569 - /* The RTL8211F PHY supports these LED settings on up to three LEDs:
570 - * - Link: Configurable subset of 10/100/1000 link rates
571 - * - Active: Blink on activity, RX or TX is not differentiated
572 - * The Active option has two modes, A and B:
573 - * - A: Link and Active indication at configurable, but matching,
574 - * subset of 10/100/1000 link rates
575 - * - B: Link indication at configurable subset of 10/100/1000 link
576 - * rates and Active indication always at all three 10+100+1000
577 - * link rates.
578 - * This code currently uses mode B only.
579 - */
580 -
581 - if (index >= RTL8211F_LED_COUNT)
582 - return -EINVAL;
583 -
584 - /* Filter out any other unsupported triggers. */
585 - if (rules & ~mask)
586 - return -EOPNOTSUPP;
587 -
588 - /* RX and TX are not differentiated, either both are set or not set. */
589 - if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
590 - return -EOPNOTSUPP;
591 -
592 - return 0;
593 -}
594 -
595 -static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
596 - unsigned long *rules)
597 -{
598 - int val;
599 -
600 - if (index >= RTL8211F_LED_COUNT)
601 - return -EINVAL;
602 -
603 - val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
604 - if (val < 0)
605 - return val;
606 -
607 - val >>= RTL8211F_LEDCR_SHIFT * index;
608 - val &= RTL8211F_LEDCR_MASK;
609 -
610 - if (val & RTL8211F_LEDCR_LINK_10)
611 - set_bit(TRIGGER_NETDEV_LINK_10, rules);
612 -
613 - if (val & RTL8211F_LEDCR_LINK_100)
614 - set_bit(TRIGGER_NETDEV_LINK_100, rules);
615 -
616 - if (val & RTL8211F_LEDCR_LINK_1000)
617 - set_bit(TRIGGER_NETDEV_LINK_1000, rules);
618 -
619 - if (val & RTL8211F_LEDCR_ACT_TXRX) {
620 - set_bit(TRIGGER_NETDEV_RX, rules);
621 - set_bit(TRIGGER_NETDEV_TX, rules);
622 - }
623 -
624 - return 0;
625 -}
626 -
627 -static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
628 - unsigned long rules)
629 -{
630 - const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
631 - u16 reg = 0;
632 -
633 - if (index >= RTL8211F_LED_COUNT)
634 - return -EINVAL;
635 -
636 - if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
637 - reg |= RTL8211F_LEDCR_LINK_10;
638 -
639 - if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
640 - reg |= RTL8211F_LEDCR_LINK_100;
641 -
642 - if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
643 - reg |= RTL8211F_LEDCR_LINK_1000;
644 -
645 - if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
646 - test_bit(TRIGGER_NETDEV_TX, &rules)) {
647 - reg |= RTL8211F_LEDCR_ACT_TXRX;
648 - }
649 -
650 - reg <<= RTL8211F_LEDCR_SHIFT * index;
651 - reg |= RTL8211F_LEDCR_MODE; /* Mode B */
652 -
653 - return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
654 -}
655 -
656 -static int rtl8211e_config_init(struct phy_device *phydev)
657 -{
658 - int ret = 0, oldpage;
659 - u16 val;
660 -
661 - /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
662 - switch (phydev->interface) {
663 - case PHY_INTERFACE_MODE_RGMII:
664 - val = RTL8211E_CTRL_DELAY | 0;
665 - break;
666 - case PHY_INTERFACE_MODE_RGMII_ID:
667 - val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
668 - break;
669 - case PHY_INTERFACE_MODE_RGMII_RXID:
670 - val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
671 - break;
672 - case PHY_INTERFACE_MODE_RGMII_TXID:
673 - val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
674 - break;
675 - default: /* the rest of the modes imply leaving delays as is. */
676 - return 0;
677 - }
678 -
679 - /* According to a sample driver there is a 0x1c config register on the
680 - * 0xa4 extension page (0x7) layout. It can be used to disable/enable
681 - * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
682 - * The configuration register definition:
683 - * 14 = reserved
684 - * 13 = Force Tx RX Delay controlled by bit12 bit11,
685 - * 12 = RX Delay, 11 = TX Delay
686 - * 10:0 = Test && debug settings reserved by realtek
687 - */
688 - oldpage = phy_select_page(phydev, 0x7);
689 - if (oldpage < 0)
690 - goto err_restore_page;
691 -
692 - ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
693 - if (ret)
694 - goto err_restore_page;
695 -
696 - ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
697 - | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
698 - val);
699 -
700 -err_restore_page:
701 - return phy_restore_page(phydev, oldpage, ret);
702 -}
703 -
704 -static int rtl8211b_suspend(struct phy_device *phydev)
705 -{
706 - phy_write(phydev, MII_MMD_DATA, BIT(9));
707 -
708 - return genphy_suspend(phydev);
709 -}
710 -
711 -static int rtl8211b_resume(struct phy_device *phydev)
712 -{
713 - phy_write(phydev, MII_MMD_DATA, 0);
714 -
715 - return genphy_resume(phydev);
716 -}
717 -
718 -static int rtl8366rb_config_init(struct phy_device *phydev)
719 -{
720 - int ret;
721 -
722 - ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
723 - RTL8366RB_POWER_SAVE_ON);
724 - if (ret) {
725 - dev_err(&phydev->mdio.dev,
726 - "error enabling power management\n");
727 - }
728 -
729 - return ret;
730 -}
731 -
732 -/* get actual speed to cover the downshift case */
733 -static void rtlgen_decode_physr(struct phy_device *phydev, int val)
734 -{
735 - /* bit 3
736 - * 0: Half Duplex
737 - * 1: Full Duplex
738 - */
739 - if (val & RTL_VND2_PHYSR_DUPLEX)
740 - phydev->duplex = DUPLEX_FULL;
741 - else
742 - phydev->duplex = DUPLEX_HALF;
743 -
744 - switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
745 - case 0x0000:
746 - phydev->speed = SPEED_10;
747 - break;
748 - case 0x0010:
749 - phydev->speed = SPEED_100;
750 - break;
751 - case 0x0020:
752 - phydev->speed = SPEED_1000;
753 - break;
754 - case 0x0200:
755 - phydev->speed = SPEED_10000;
756 - break;
757 - case 0x0210:
758 - phydev->speed = SPEED_2500;
759 - break;
760 - case 0x0220:
761 - phydev->speed = SPEED_5000;
762 - break;
763 - default:
764 - break;
765 - }
766 -
767 - /* bit 11
768 - * 0: Slave Mode
769 - * 1: Master Mode
770 - */
771 - if (phydev->speed >= 1000) {
772 - if (val & RTL_VND2_PHYSR_MASTER)
773 - phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
774 - else
775 - phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
776 - } else {
777 - phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
778 - }
779 -}
780 -
781 -static int rtlgen_read_status(struct phy_device *phydev)
782 -{
783 - int ret, val;
784 -
785 - ret = genphy_read_status(phydev);
786 - if (ret < 0)
787 - return ret;
788 -
789 - if (!phydev->link)
790 - return 0;
791 -
792 - val = phy_read_paged(phydev, 0xa43, 0x12);
793 - if (val < 0)
794 - return val;
795 -
796 - rtlgen_decode_physr(phydev, val);
797 -
798 - return 0;
799 -}
800 -
801 -static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
802 -{
803 - int ret;
804 -
805 - if (devnum == MDIO_MMD_VEND2) {
806 - rtl821x_write_page(phydev, regnum >> 4);
807 - ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
808 - rtl821x_write_page(phydev, 0);
809 - } else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
810 - rtl821x_write_page(phydev, 0xa5c);
811 - ret = __phy_read(phydev, 0x12);
812 - rtl821x_write_page(phydev, 0);
813 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
814 - rtl821x_write_page(phydev, 0xa5d);
815 - ret = __phy_read(phydev, 0x10);
816 - rtl821x_write_page(phydev, 0);
817 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
818 - rtl821x_write_page(phydev, 0xa5d);
819 - ret = __phy_read(phydev, 0x11);
820 - rtl821x_write_page(phydev, 0);
821 - } else {
822 - ret = -EOPNOTSUPP;
823 - }
824 -
825 - return ret;
826 -}
827 -
828 -static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
829 - u16 val)
830 -{
831 - int ret;
832 -
833 - if (devnum == MDIO_MMD_VEND2) {
834 - rtl821x_write_page(phydev, regnum >> 4);
835 - ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
836 - rtl821x_write_page(phydev, 0);
837 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
838 - rtl821x_write_page(phydev, 0xa5d);
839 - ret = __phy_write(phydev, 0x10, val);
840 - rtl821x_write_page(phydev, 0);
841 - } else {
842 - ret = -EOPNOTSUPP;
843 - }
844 -
845 - return ret;
846 -}
847 -
848 -static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
849 -{
850 - int ret = rtlgen_read_mmd(phydev, devnum, regnum);
851 -
852 - if (ret != -EOPNOTSUPP)
853 - return ret;
854 -
855 - if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
856 - rtl821x_write_page(phydev, 0xa6e);
857 - ret = __phy_read(phydev, 0x16);
858 - rtl821x_write_page(phydev, 0);
859 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
860 - rtl821x_write_page(phydev, 0xa6d);
861 - ret = __phy_read(phydev, 0x12);
862 - rtl821x_write_page(phydev, 0);
863 - } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
864 - rtl821x_write_page(phydev, 0xa6d);
865 - ret = __phy_read(phydev, 0x10);
866 - rtl821x_write_page(phydev, 0);
867 - }
868 -
869 - return ret;
870 -}
871 -
872 -static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
873 - u16 val)
874 -{
875 - int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
876 -
877 - if (ret != -EOPNOTSUPP)
878 - return ret;
879 -
880 - if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
881 - rtl821x_write_page(phydev, 0xa6d);
882 - ret = __phy_write(phydev, 0x12, val);
883 - rtl821x_write_page(phydev, 0);
884 - }
885 -
886 - return ret;
887 -}
888 -
889 -static int rtl822xb_config_init(struct phy_device *phydev)
890 -{
891 - bool has_2500, has_sgmii;
892 - u16 mode;
893 - int ret;
894 -
895 - has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
896 - phydev->host_interfaces) ||
897 - phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
898 -
899 - has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
900 - phydev->host_interfaces) ||
901 - phydev->interface == PHY_INTERFACE_MODE_SGMII;
902 -
903 - /* fill in possible interfaces */
904 - __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
905 - has_2500);
906 - __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
907 - has_sgmii);
908 -
909 - if (!has_2500 && !has_sgmii)
910 - return 0;
911 -
912 - /* determine SerDes option mode */
913 - if (has_2500 && !has_sgmii) {
914 - mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
915 - phydev->rate_matching = RATE_MATCH_PAUSE;
916 - } else {
917 - mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
918 - phydev->rate_matching = RATE_MATCH_NONE;
919 - }
920 -
921 - /* the following sequence with magic numbers sets up the SerDes
922 - * option mode
923 - */
924 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
925 - if (ret < 0)
926 - return ret;
927 -
928 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
929 - RTL822X_VND1_SERDES_OPTION,
930 - RTL822X_VND1_SERDES_OPTION_MODE_MASK,
931 - mode);
932 - if (ret < 0)
933 - return ret;
934 -
935 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
936 - if (ret < 0)
937 - return ret;
938 -
939 - ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
940 - if (ret < 0)
941 - return ret;
942 -
943 - return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
944 -}
945 -
946 -static int rtl822xb_get_rate_matching(struct phy_device *phydev,
947 - phy_interface_t iface)
948 -{
949 - int val;
950 -
951 - /* Only rate matching at 2500base-x */
952 - if (iface != PHY_INTERFACE_MODE_2500BASEX)
953 - return RATE_MATCH_NONE;
954 -
955 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
956 - if (val < 0)
957 - return val;
958 -
959 - if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
960 - RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
961 - return RATE_MATCH_PAUSE;
962 -
963 - /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
964 - return RATE_MATCH_NONE;
965 -}
966 -
967 -static int rtl822x_get_features(struct phy_device *phydev)
968 -{
969 - int val;
970 -
971 - val = phy_read_paged(phydev, 0xa61, 0x13);
972 - if (val < 0)
973 - return val;
974 -
975 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
976 - phydev->supported, val & MDIO_PMA_SPEED_2_5G);
977 - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
978 - phydev->supported, val & MDIO_PMA_SPEED_5G);
979 - linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
980 - phydev->supported, val & MDIO_SPEED_10G);
981 -
982 - return genphy_read_abilities(phydev);
983 -}
984 -
985 -static int rtl822x_config_aneg(struct phy_device *phydev)
986 -{
987 - int ret = 0;
988 -
989 - if (phydev->autoneg == AUTONEG_ENABLE) {
990 - u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
991 -
992 - ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
993 - MDIO_AN_10GBT_CTRL_ADV2_5G |
994 - MDIO_AN_10GBT_CTRL_ADV5G,
995 - adv);
996 - if (ret < 0)
997 - return ret;
998 - }
999 -
1000 - return __genphy_config_aneg(phydev, ret);
1001 -}
1002 -
1003 -static void rtl822xb_update_interface(struct phy_device *phydev)
1004 -{
1005 - int val;
1006 -
1007 - if (!phydev->link)
1008 - return;
1009 -
1010 - /* Change interface according to serdes mode */
1011 - val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
1012 - if (val < 0)
1013 - return;
1014 -
1015 - switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
1016 - case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
1017 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
1018 - break;
1019 - case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
1020 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
1021 - break;
1022 - }
1023 -}
1024 -
1025 -static int rtl822x_read_status(struct phy_device *phydev)
1026 -{
1027 - int lpadv, ret;
1028 -
1029 - ret = rtlgen_read_status(phydev);
1030 - if (ret < 0)
1031 - return ret;
1032 -
1033 - if (phydev->autoneg == AUTONEG_DISABLE ||
1034 - !phydev->autoneg_complete) {
1035 - mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1036 - return 0;
1037 - }
1038 -
1039 - lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
1040 - if (lpadv < 0)
1041 - return lpadv;
1042 -
1043 - mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
1044 -
1045 - return 0;
1046 -}
1047 -
1048 -static int rtl822xb_read_status(struct phy_device *phydev)
1049 -{
1050 - int ret;
1051 -
1052 - ret = rtl822x_read_status(phydev);
1053 - if (ret < 0)
1054 - return ret;
1055 -
1056 - rtl822xb_update_interface(phydev);
1057 -
1058 - return 0;
1059 -}
1060 -
1061 -static int rtl822x_c45_get_features(struct phy_device *phydev)
1062 -{
1063 - linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
1064 - phydev->supported);
1065 -
1066 - return genphy_c45_pma_read_abilities(phydev);
1067 -}
1068 -
1069 -static int rtl822x_c45_config_aneg(struct phy_device *phydev)
1070 -{
1071 - bool changed = false;
1072 - int ret, val;
1073 -
1074 - if (phydev->autoneg == AUTONEG_DISABLE)
1075 - return genphy_c45_pma_setup_forced(phydev);
1076 -
1077 - ret = genphy_c45_an_config_aneg(phydev);
1078 - if (ret < 0)
1079 - return ret;
1080 - if (ret > 0)
1081 - changed = true;
1082 -
1083 - val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
1084 -
1085 - /* Vendor register as C45 has no standardized support for 1000BaseT */
1086 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
1087 - ADVERTISE_1000FULL, val);
1088 - if (ret < 0)
1089 - return ret;
1090 - if (ret > 0)
1091 - changed = true;
1092 -
1093 - return genphy_c45_check_and_restart_aneg(phydev, changed);
1094 -}
1095 -
1096 -static int rtl822x_c45_read_status(struct phy_device *phydev)
1097 -{
1098 - int ret, val;
1099 -
1100 - ret = genphy_c45_read_status(phydev);
1101 - if (ret < 0)
1102 - return ret;
1103 -
1104 - if (phydev->autoneg == AUTONEG_DISABLE ||
1105 - !genphy_c45_aneg_done(phydev))
1106 - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
1107 -
1108 - /* Vendor register as C45 has no standardized support for 1000BaseT */
1109 - if (phydev->autoneg == AUTONEG_ENABLE) {
1110 - val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
1111 - RTL822X_VND2_GANLPAR);
1112 - if (val < 0)
1113 - return val;
1114 -
1115 - mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
1116 - }
1117 -
1118 - if (!phydev->link)
1119 - return 0;
1120 -
1121 - /* Read actual speed from vendor register. */
1122 - val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
1123 - if (val < 0)
1124 - return val;
1125 -
1126 - rtlgen_decode_physr(phydev, val);
1127 -
1128 - return 0;
1129 -}
1130 -
1131 -static int rtl822xb_c45_read_status(struct phy_device *phydev)
1132 -{
1133 - int ret;
1134 -
1135 - ret = rtl822x_c45_read_status(phydev);
1136 - if (ret < 0)
1137 - return ret;
1138 -
1139 - rtl822xb_update_interface(phydev);
1140 -
1141 - return 0;
1142 -}
1143 -
1144 -static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
1145 -{
1146 - int val;
1147 -
1148 - phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
1149 - val = phy_read(phydev, 0x13);
1150 - phy_write(phydev, RTL821x_PAGE_SELECT, 0);
1151 -
1152 - return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
1153 -}
1154 -
1155 -/* On internal PHY's MMD reads over C22 always return 0.
1156 - * Check a MMD register which is known to be non-zero.
1157 - */
1158 -static bool rtlgen_supports_mmd(struct phy_device *phydev)
1159 -{
1160 - int val;
1161 -
1162 - phy_lock_mdio_bus(phydev);
1163 - __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
1164 - __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
1165 - __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
1166 - val = __phy_read(phydev, MII_MMD_DATA);
1167 - phy_unlock_mdio_bus(phydev);
1168 -
1169 - return val > 0;
1170 -}
1171 -
1172 -static int rtlgen_match_phy_device(struct phy_device *phydev)
1173 -{
1174 - return phydev->phy_id == RTL_GENERIC_PHYID &&
1175 - !rtlgen_supports_2_5gbps(phydev);
1176 -}
1177 -
1178 -static int rtl8226_match_phy_device(struct phy_device *phydev)
1179 -{
1180 - return phydev->phy_id == RTL_GENERIC_PHYID &&
1181 - rtlgen_supports_2_5gbps(phydev) &&
1182 - rtlgen_supports_mmd(phydev);
1183 -}
1184 -
1185 -static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
1186 - bool is_c45)
1187 -{
1188 - if (phydev->is_c45)
1189 - return is_c45 && (id == phydev->c45_ids.device_ids[1]);
1190 - else
1191 - return !is_c45 && (id == phydev->phy_id);
1192 -}
1193 -
1194 -static int rtl8221b_match_phy_device(struct phy_device *phydev)
1195 -{
1196 - return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
1197 -}
1198 -
1199 -static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
1200 -{
1201 - return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
1202 -}
1203 -
1204 -static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
1205 -{
1206 - return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
1207 -}
1208 -
1209 -static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
1210 -{
1211 - return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
1212 -}
1213 -
1214 -static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
1215 -{
1216 - return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
1217 -}
1218 -
1219 -static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
1220 -{
1221 - if (phydev->is_c45)
1222 - return false;
1223 -
1224 - switch (phydev->phy_id) {
1225 - case RTL_GENERIC_PHYID:
1226 - case RTL_8221B:
1227 - case RTL_8251B:
1228 - case 0x001cc841:
1229 - break;
1230 - default:
1231 - return false;
1232 - }
1233 -
1234 - return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
1235 -}
1236 -
1237 -static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
1238 -{
1239 - return rtlgen_is_c45_match(phydev, RTL_8251B, true);
1240 -}
1241 -
1242 -static int rtlgen_resume(struct phy_device *phydev)
1243 -{
1244 - int ret = genphy_resume(phydev);
1245 -
1246 - /* Internal PHY's from RTL8168h up may not be instantly ready */
1247 - msleep(20);
1248 -
1249 - return ret;
1250 -}
1251 -
1252 -static int rtlgen_c45_resume(struct phy_device *phydev)
1253 -{
1254 - int ret = genphy_c45_pma_resume(phydev);
1255 -
1256 - msleep(20);
1257 -
1258 - return ret;
1259 -}
1260 -
1261 -static int rtl9000a_config_init(struct phy_device *phydev)
1262 -{
1263 - phydev->autoneg = AUTONEG_DISABLE;
1264 - phydev->speed = SPEED_100;
1265 - phydev->duplex = DUPLEX_FULL;
1266 -
1267 - return 0;
1268 -}
1269 -
1270 -static int rtl9000a_config_aneg(struct phy_device *phydev)
1271 -{
1272 - int ret;
1273 - u16 ctl = 0;
1274 -
1275 - switch (phydev->master_slave_set) {
1276 - case MASTER_SLAVE_CFG_MASTER_FORCE:
1277 - ctl |= CTL1000_AS_MASTER;
1278 - break;
1279 - case MASTER_SLAVE_CFG_SLAVE_FORCE:
1280 - break;
1281 - case MASTER_SLAVE_CFG_UNKNOWN:
1282 - case MASTER_SLAVE_CFG_UNSUPPORTED:
1283 - return 0;
1284 - default:
1285 - phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1286 - return -EOPNOTSUPP;
1287 - }
1288 -
1289 - ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1290 - if (ret == 1)
1291 - ret = genphy_soft_reset(phydev);
1292 -
1293 - return ret;
1294 -}
1295 -
1296 -static int rtl9000a_read_status(struct phy_device *phydev)
1297 -{
1298 - int ret;
1299 -
1300 - phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
1301 - phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
1302 -
1303 - ret = genphy_update_link(phydev);
1304 - if (ret)
1305 - return ret;
1306 -
1307 - ret = phy_read(phydev, MII_CTRL1000);
1308 - if (ret < 0)
1309 - return ret;
1310 - if (ret & CTL1000_AS_MASTER)
1311 - phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
1312 - else
1313 - phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
1314 -
1315 - ret = phy_read(phydev, MII_STAT1000);
1316 - if (ret < 0)
1317 - return ret;
1318 - if (ret & LPA_1000MSRES)
1319 - phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
1320 - else
1321 - phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
1322 -
1323 - return 0;
1324 -}
1325 -
1326 -static int rtl9000a_ack_interrupt(struct phy_device *phydev)
1327 -{
1328 - int err;
1329 -
1330 - err = phy_read(phydev, RTL8211F_INSR);
1331 -
1332 - return (err < 0) ? err : 0;
1333 -}
1334 -
1335 -static int rtl9000a_config_intr(struct phy_device *phydev)
1336 -{
1337 - u16 val;
1338 - int err;
1339 -
1340 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1341 - err = rtl9000a_ack_interrupt(phydev);
1342 - if (err)
1343 - return err;
1344 -
1345 - val = (u16)~RTL9000A_GINMR_LINK_STATUS;
1346 - err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1347 - } else {
1348 - val = ~0;
1349 - err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1350 - if (err)
1351 - return err;
1352 -
1353 - err = rtl9000a_ack_interrupt(phydev);
1354 - }
1355 -
1356 - return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
1357 -}
1358 -
1359 -static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
1360 -{
1361 - int irq_status;
1362 -
1363 - irq_status = phy_read(phydev, RTL8211F_INSR);
1364 - if (irq_status < 0) {
1365 - phy_error(phydev);
1366 - return IRQ_NONE;
1367 - }
1368 -
1369 - if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1370 - return IRQ_NONE;
1371 -
1372 - phy_trigger_machine(phydev);
1373 -
1374 - return IRQ_HANDLED;
1375 -}
1376 -
1377 -static struct phy_driver realtek_drvs[] = {
1378 - {
1379 - PHY_ID_MATCH_EXACT(0x00008201),
1380 - .name = "RTL8201CP Ethernet",
1381 - .read_page = rtl821x_read_page,
1382 - .write_page = rtl821x_write_page,
1383 - }, {
1384 - PHY_ID_MATCH_EXACT(0x001cc816),
1385 - .name = "RTL8201F Fast Ethernet",
1386 - .config_intr = &rtl8201_config_intr,
1387 - .handle_interrupt = rtl8201_handle_interrupt,
1388 - .suspend = genphy_suspend,
1389 - .resume = genphy_resume,
1390 - .read_page = rtl821x_read_page,
1391 - .write_page = rtl821x_write_page,
1392 - }, {
1393 - PHY_ID_MATCH_MODEL(0x001cc880),
1394 - .name = "RTL8208 Fast Ethernet",
1395 - .read_mmd = genphy_read_mmd_unsupported,
1396 - .write_mmd = genphy_write_mmd_unsupported,
1397 - .suspend = genphy_suspend,
1398 - .resume = genphy_resume,
1399 - .read_page = rtl821x_read_page,
1400 - .write_page = rtl821x_write_page,
1401 - }, {
1402 - PHY_ID_MATCH_EXACT(0x001cc910),
1403 - .name = "RTL8211 Gigabit Ethernet",
1404 - .config_aneg = rtl8211_config_aneg,
1405 - .read_mmd = &genphy_read_mmd_unsupported,
1406 - .write_mmd = &genphy_write_mmd_unsupported,
1407 - .read_page = rtl821x_read_page,
1408 - .write_page = rtl821x_write_page,
1409 - }, {
1410 - PHY_ID_MATCH_EXACT(0x001cc912),
1411 - .name = "RTL8211B Gigabit Ethernet",
1412 - .config_intr = &rtl8211b_config_intr,
1413 - .handle_interrupt = rtl821x_handle_interrupt,
1414 - .read_mmd = &genphy_read_mmd_unsupported,
1415 - .write_mmd = &genphy_write_mmd_unsupported,
1416 - .suspend = rtl8211b_suspend,
1417 - .resume = rtl8211b_resume,
1418 - .read_page = rtl821x_read_page,
1419 - .write_page = rtl821x_write_page,
1420 - }, {
1421 - PHY_ID_MATCH_EXACT(0x001cc913),
1422 - .name = "RTL8211C Gigabit Ethernet",
1423 - .config_init = rtl8211c_config_init,
1424 - .read_mmd = &genphy_read_mmd_unsupported,
1425 - .write_mmd = &genphy_write_mmd_unsupported,
1426 - .read_page = rtl821x_read_page,
1427 - .write_page = rtl821x_write_page,
1428 - }, {
1429 - PHY_ID_MATCH_EXACT(0x001cc914),
1430 - .name = "RTL8211DN Gigabit Ethernet",
1431 - .config_intr = rtl8211e_config_intr,
1432 - .handle_interrupt = rtl821x_handle_interrupt,
1433 - .suspend = genphy_suspend,
1434 - .resume = genphy_resume,
1435 - .read_page = rtl821x_read_page,
1436 - .write_page = rtl821x_write_page,
1437 - }, {
1438 - PHY_ID_MATCH_EXACT(0x001cc915),
1439 - .name = "RTL8211E Gigabit Ethernet",
1440 - .config_init = &rtl8211e_config_init,
1441 - .config_intr = &rtl8211e_config_intr,
1442 - .handle_interrupt = rtl821x_handle_interrupt,
1443 - .suspend = genphy_suspend,
1444 - .resume = genphy_resume,
1445 - .read_page = rtl821x_read_page,
1446 - .write_page = rtl821x_write_page,
1447 - }, {
1448 - PHY_ID_MATCH_EXACT(0x001cc916),
1449 - .name = "RTL8211F Gigabit Ethernet",
1450 - .probe = rtl821x_probe,
1451 - .config_init = &rtl8211f_config_init,
1452 - .read_status = rtlgen_read_status,
1453 - .config_intr = &rtl8211f_config_intr,
1454 - .handle_interrupt = rtl8211f_handle_interrupt,
1455 - .suspend = rtl821x_suspend,
1456 - .resume = rtl821x_resume,
1457 - .read_page = rtl821x_read_page,
1458 - .write_page = rtl821x_write_page,
1459 - .flags = PHY_ALWAYS_CALL_SUSPEND,
1460 - .led_hw_is_supported = rtl8211f_led_hw_is_supported,
1461 - .led_hw_control_get = rtl8211f_led_hw_control_get,
1462 - .led_hw_control_set = rtl8211f_led_hw_control_set,
1463 - }, {
1464 - PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
1465 - .name = "RTL8211F-VD Gigabit Ethernet",
1466 - .probe = rtl821x_probe,
1467 - .config_init = &rtl8211f_config_init,
1468 - .read_status = rtlgen_read_status,
1469 - .config_intr = &rtl8211f_config_intr,
1470 - .handle_interrupt = rtl8211f_handle_interrupt,
1471 - .suspend = rtl821x_suspend,
1472 - .resume = rtl821x_resume,
1473 - .read_page = rtl821x_read_page,
1474 - .write_page = rtl821x_write_page,
1475 - .flags = PHY_ALWAYS_CALL_SUSPEND,
1476 - }, {
1477 - .name = "Generic FE-GE Realtek PHY",
1478 - .match_phy_device = rtlgen_match_phy_device,
1479 - .read_status = rtlgen_read_status,
1480 - .suspend = genphy_suspend,
1481 - .resume = rtlgen_resume,
1482 - .read_page = rtl821x_read_page,
1483 - .write_page = rtl821x_write_page,
1484 - .read_mmd = rtlgen_read_mmd,
1485 - .write_mmd = rtlgen_write_mmd,
1486 - }, {
1487 - .name = "RTL8226 2.5Gbps PHY",
1488 - .match_phy_device = rtl8226_match_phy_device,
1489 - .get_features = rtl822x_get_features,
1490 - .config_aneg = rtl822x_config_aneg,
1491 - .read_status = rtl822x_read_status,
1492 - .suspend = genphy_suspend,
1493 - .resume = rtlgen_resume,
1494 - .read_page = rtl821x_read_page,
1495 - .write_page = rtl821x_write_page,
1496 - }, {
1497 - .match_phy_device = rtl8221b_match_phy_device,
1498 - .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
1499 - .get_features = rtl822x_get_features,
1500 - .config_aneg = rtl822x_config_aneg,
1501 - .config_init = rtl822xb_config_init,
1502 - .get_rate_matching = rtl822xb_get_rate_matching,
1503 - .read_status = rtl822xb_read_status,
1504 - .suspend = genphy_suspend,
1505 - .resume = rtlgen_resume,
1506 - .read_page = rtl821x_read_page,
1507 - .write_page = rtl821x_write_page,
1508 - }, {
1509 - PHY_ID_MATCH_EXACT(0x001cc838),
1510 - .name = "RTL8226-CG 2.5Gbps PHY",
1511 - .get_features = rtl822x_get_features,
1512 - .config_aneg = rtl822x_config_aneg,
1513 - .read_status = rtl822x_read_status,
1514 - .suspend = genphy_suspend,
1515 - .resume = rtlgen_resume,
1516 - .read_page = rtl821x_read_page,
1517 - .write_page = rtl821x_write_page,
1518 - }, {
1519 - PHY_ID_MATCH_EXACT(0x001cc848),
1520 - .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1521 - .get_features = rtl822x_get_features,
1522 - .config_aneg = rtl822x_config_aneg,
1523 - .config_init = rtl822xb_config_init,
1524 - .get_rate_matching = rtl822xb_get_rate_matching,
1525 - .read_status = rtl822xb_read_status,
1526 - .suspend = genphy_suspend,
1527 - .resume = rtlgen_resume,
1528 - .read_page = rtl821x_read_page,
1529 - .write_page = rtl821x_write_page,
1530 - }, {
1531 - .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
1532 - .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1533 - .get_features = rtl822x_get_features,
1534 - .config_aneg = rtl822x_config_aneg,
1535 - .config_init = rtl822xb_config_init,
1536 - .get_rate_matching = rtl822xb_get_rate_matching,
1537 - .read_status = rtl822xb_read_status,
1538 - .suspend = genphy_suspend,
1539 - .resume = rtlgen_resume,
1540 - .read_page = rtl821x_read_page,
1541 - .write_page = rtl821x_write_page,
1542 - }, {
1543 - .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
1544 - .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1545 - .config_init = rtl822xb_config_init,
1546 - .get_rate_matching = rtl822xb_get_rate_matching,
1547 - .get_features = rtl822x_c45_get_features,
1548 - .config_aneg = rtl822x_c45_config_aneg,
1549 - .read_status = rtl822xb_c45_read_status,
1550 - .suspend = genphy_c45_pma_suspend,
1551 - .resume = rtlgen_c45_resume,
1552 - }, {
1553 - .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
1554 - .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1555 - .get_features = rtl822x_get_features,
1556 - .config_aneg = rtl822x_config_aneg,
1557 - .config_init = rtl822xb_config_init,
1558 - .get_rate_matching = rtl822xb_get_rate_matching,
1559 - .read_status = rtl822xb_read_status,
1560 - .suspend = genphy_suspend,
1561 - .resume = rtlgen_resume,
1562 - .read_page = rtl821x_read_page,
1563 - .write_page = rtl821x_write_page,
1564 - }, {
1565 - .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
1566 - .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1567 - .config_init = rtl822xb_config_init,
1568 - .get_rate_matching = rtl822xb_get_rate_matching,
1569 - .get_features = rtl822x_c45_get_features,
1570 - .config_aneg = rtl822x_c45_config_aneg,
1571 - .read_status = rtl822xb_c45_read_status,
1572 - .suspend = genphy_c45_pma_suspend,
1573 - .resume = rtlgen_c45_resume,
1574 - }, {
1575 - .match_phy_device = rtl8251b_c45_match_phy_device,
1576 - .name = "RTL8251B 5Gbps PHY",
1577 - .get_features = rtl822x_get_features,
1578 - .config_aneg = rtl822x_config_aneg,
1579 - .read_status = rtl822x_read_status,
1580 - .suspend = genphy_suspend,
1581 - .resume = rtlgen_resume,
1582 - .read_page = rtl821x_read_page,
1583 - .write_page = rtl821x_write_page,
1584 - }, {
1585 - .match_phy_device = rtl_internal_nbaset_match_phy_device,
1586 - .name = "Realtek Internal NBASE-T PHY",
1587 - .flags = PHY_IS_INTERNAL,
1588 - .get_features = rtl822x_get_features,
1589 - .config_aneg = rtl822x_config_aneg,
1590 - .read_status = rtl822x_read_status,
1591 - .suspend = genphy_suspend,
1592 - .resume = rtlgen_resume,
1593 - .read_page = rtl821x_read_page,
1594 - .write_page = rtl821x_write_page,
1595 - .read_mmd = rtl822x_read_mmd,
1596 - .write_mmd = rtl822x_write_mmd,
1597 - }, {
1598 - PHY_ID_MATCH_EXACT(0x001ccad0),
1599 - .name = "RTL8224 2.5Gbps PHY",
1600 - .get_features = rtl822x_c45_get_features,
1601 - .config_aneg = rtl822x_c45_config_aneg,
1602 - .read_status = rtl822x_c45_read_status,
1603 - .suspend = genphy_c45_pma_suspend,
1604 - .resume = rtlgen_c45_resume,
1605 - }, {
1606 - PHY_ID_MATCH_EXACT(0x001cc961),
1607 - .name = "RTL8366RB Gigabit Ethernet",
1608 - .config_init = &rtl8366rb_config_init,
1609 - /* These interrupts are handled by the irq controller
1610 - * embedded inside the RTL8366RB, they get unmasked when the
1611 - * irq is requested and ACKed by reading the status register,
1612 - * which is done by the irqchip code.
1613 - */
1614 - .config_intr = genphy_no_config_intr,
1615 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1616 - .suspend = genphy_suspend,
1617 - .resume = genphy_resume,
1618 - }, {
1619 - PHY_ID_MATCH_EXACT(0x001ccb00),
1620 - .name = "RTL9000AA_RTL9000AN Ethernet",
1621 - .features = PHY_BASIC_T1_FEATURES,
1622 - .config_init = rtl9000a_config_init,
1623 - .config_aneg = rtl9000a_config_aneg,
1624 - .read_status = rtl9000a_read_status,
1625 - .config_intr = rtl9000a_config_intr,
1626 - .handle_interrupt = rtl9000a_handle_interrupt,
1627 - .suspend = genphy_suspend,
1628 - .resume = genphy_resume,
1629 - .read_page = rtl821x_read_page,
1630 - .write_page = rtl821x_write_page,
1631 - }, {
1632 - PHY_ID_MATCH_EXACT(0x001cc942),
1633 - .name = "RTL8365MB-VC Gigabit Ethernet",
1634 - /* Interrupt handling analogous to RTL8366RB */
1635 - .config_intr = genphy_no_config_intr,
1636 - .handle_interrupt = genphy_handle_interrupt_no_ack,
1637 - .suspend = genphy_suspend,
1638 - .resume = genphy_resume,
1639 - }, {
1640 - PHY_ID_MATCH_EXACT(0x001cc960),
1641 - .name = "RTL8366S Gigabit Ethernet",
1642 - .suspend = genphy_suspend,
1643 - .resume = genphy_resume,
1644 - .read_mmd = genphy_read_mmd_unsupported,
1645 - .write_mmd = genphy_write_mmd_unsupported,
1646 - },
1647 -};
1648 -
1649 -module_phy_driver(realtek_drvs);
1650 -
1651 -static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1652 - { PHY_ID_MATCH_VENDOR(0x001cc800) },
1653 - { }
1654 -};
1655 -
1656 -MODULE_DEVICE_TABLE(mdio, realtek_tbl);
1657 --- /dev/null
1658 +++ b/drivers/net/phy/realtek/realtek_main.c
1659 @@ -0,0 +1,1590 @@
1660 +// SPDX-License-Identifier: GPL-2.0+
1661 +/* drivers/net/phy/realtek.c
1662 + *
1663 + * Driver for Realtek PHYs
1664 + *
1665 + * Author: Johnson Leung <r58129@freescale.com>
1666 + *
1667 + * Copyright (c) 2004 Freescale Semiconductor, Inc.
1668 + */
1669 +#include <linux/bitops.h>
1670 +#include <linux/of.h>
1671 +#include <linux/phy.h>
1672 +#include <linux/module.h>
1673 +#include <linux/delay.h>
1674 +#include <linux/clk.h>
1675 +
1676 +#define RTL821x_PHYSR 0x11
1677 +#define RTL821x_PHYSR_DUPLEX BIT(13)
1678 +#define RTL821x_PHYSR_SPEED GENMASK(15, 14)
1679 +
1680 +#define RTL821x_INER 0x12
1681 +#define RTL8211B_INER_INIT 0x6400
1682 +#define RTL8211E_INER_LINK_STATUS BIT(10)
1683 +#define RTL8211F_INER_LINK_STATUS BIT(4)
1684 +
1685 +#define RTL821x_INSR 0x13
1686 +
1687 +#define RTL821x_EXT_PAGE_SELECT 0x1e
1688 +#define RTL821x_PAGE_SELECT 0x1f
1689 +
1690 +#define RTL8211F_PHYCR1 0x18
1691 +#define RTL8211F_PHYCR2 0x19
1692 +#define RTL8211F_INSR 0x1d
1693 +
1694 +#define RTL8211F_LEDCR 0x10
1695 +#define RTL8211F_LEDCR_MODE BIT(15)
1696 +#define RTL8211F_LEDCR_ACT_TXRX BIT(4)
1697 +#define RTL8211F_LEDCR_LINK_1000 BIT(3)
1698 +#define RTL8211F_LEDCR_LINK_100 BIT(1)
1699 +#define RTL8211F_LEDCR_LINK_10 BIT(0)
1700 +#define RTL8211F_LEDCR_MASK GENMASK(4, 0)
1701 +#define RTL8211F_LEDCR_SHIFT 5
1702 +
1703 +#define RTL8211F_TX_DELAY BIT(8)
1704 +#define RTL8211F_RX_DELAY BIT(3)
1705 +
1706 +#define RTL8211F_ALDPS_PLL_OFF BIT(1)
1707 +#define RTL8211F_ALDPS_ENABLE BIT(2)
1708 +#define RTL8211F_ALDPS_XTAL_OFF BIT(12)
1709 +
1710 +#define RTL8211E_CTRL_DELAY BIT(13)
1711 +#define RTL8211E_TX_DELAY BIT(12)
1712 +#define RTL8211E_RX_DELAY BIT(11)
1713 +
1714 +#define RTL8211F_CLKOUT_EN BIT(0)
1715 +
1716 +#define RTL8201F_ISR 0x1e
1717 +#define RTL8201F_ISR_ANERR BIT(15)
1718 +#define RTL8201F_ISR_DUPLEX BIT(13)
1719 +#define RTL8201F_ISR_LINK BIT(11)
1720 +#define RTL8201F_ISR_MASK (RTL8201F_ISR_ANERR | \
1721 + RTL8201F_ISR_DUPLEX | \
1722 + RTL8201F_ISR_LINK)
1723 +#define RTL8201F_IER 0x13
1724 +
1725 +#define RTL822X_VND1_SERDES_OPTION 0x697a
1726 +#define RTL822X_VND1_SERDES_OPTION_MODE_MASK GENMASK(5, 0)
1727 +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII 0
1728 +#define RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX 2
1729 +
1730 +#define RTL822X_VND1_SERDES_CTRL3 0x7580
1731 +#define RTL822X_VND1_SERDES_CTRL3_MODE_MASK GENMASK(5, 0)
1732 +#define RTL822X_VND1_SERDES_CTRL3_MODE_SGMII 0x02
1733 +#define RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX 0x16
1734 +
1735 +/* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
1736 + * is set, they cannot be accessed by C45-over-C22.
1737 + */
1738 +#define RTL822X_VND2_GBCR 0xa412
1739 +
1740 +#define RTL822X_VND2_GANLPAR 0xa414
1741 +
1742 +#define RTL8366RB_POWER_SAVE 0x15
1743 +#define RTL8366RB_POWER_SAVE_ON BIT(12)
1744 +
1745 +#define RTL9000A_GINMR 0x14
1746 +#define RTL9000A_GINMR_LINK_STATUS BIT(4)
1747 +
1748 +#define RTL_VND2_PHYSR 0xa434
1749 +#define RTL_VND2_PHYSR_DUPLEX BIT(3)
1750 +#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
1751 +#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
1752 +#define RTL_VND2_PHYSR_MASTER BIT(11)
1753 +#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
1754 +
1755 +#define RTL_GENERIC_PHYID 0x001cc800
1756 +#define RTL_8211FVD_PHYID 0x001cc878
1757 +#define RTL_8221B 0x001cc840
1758 +#define RTL_8221B_VB_CG 0x001cc849
1759 +#define RTL_8221B_VN_CG 0x001cc84a
1760 +#define RTL_8251B 0x001cc862
1761 +
1762 +#define RTL8211F_LED_COUNT 3
1763 +
1764 +MODULE_DESCRIPTION("Realtek PHY driver");
1765 +MODULE_AUTHOR("Johnson Leung");
1766 +MODULE_LICENSE("GPL");
1767 +
1768 +struct rtl821x_priv {
1769 + u16 phycr1;
1770 + u16 phycr2;
1771 + bool has_phycr2;
1772 + struct clk *clk;
1773 +};
1774 +
1775 +static int rtl821x_read_page(struct phy_device *phydev)
1776 +{
1777 + return __phy_read(phydev, RTL821x_PAGE_SELECT);
1778 +}
1779 +
1780 +static int rtl821x_write_page(struct phy_device *phydev, int page)
1781 +{
1782 + return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
1783 +}
1784 +
1785 +static int rtl821x_probe(struct phy_device *phydev)
1786 +{
1787 + struct device *dev = &phydev->mdio.dev;
1788 + struct rtl821x_priv *priv;
1789 + u32 phy_id = phydev->drv->phy_id;
1790 + int ret;
1791 +
1792 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1793 + if (!priv)
1794 + return -ENOMEM;
1795 +
1796 + priv->clk = devm_clk_get_optional_enabled(dev, NULL);
1797 + if (IS_ERR(priv->clk))
1798 + return dev_err_probe(dev, PTR_ERR(priv->clk),
1799 + "failed to get phy clock\n");
1800 +
1801 + ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
1802 + if (ret < 0)
1803 + return ret;
1804 +
1805 + priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
1806 + if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
1807 + priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
1808 +
1809 + priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID);
1810 + if (priv->has_phycr2) {
1811 + ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
1812 + if (ret < 0)
1813 + return ret;
1814 +
1815 + priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
1816 + if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
1817 + priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
1818 + }
1819 +
1820 + phydev->priv = priv;
1821 +
1822 + return 0;
1823 +}
1824 +
1825 +static int rtl8201_ack_interrupt(struct phy_device *phydev)
1826 +{
1827 + int err;
1828 +
1829 + err = phy_read(phydev, RTL8201F_ISR);
1830 +
1831 + return (err < 0) ? err : 0;
1832 +}
1833 +
1834 +static int rtl821x_ack_interrupt(struct phy_device *phydev)
1835 +{
1836 + int err;
1837 +
1838 + err = phy_read(phydev, RTL821x_INSR);
1839 +
1840 + return (err < 0) ? err : 0;
1841 +}
1842 +
1843 +static int rtl8211f_ack_interrupt(struct phy_device *phydev)
1844 +{
1845 + int err;
1846 +
1847 + err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
1848 +
1849 + return (err < 0) ? err : 0;
1850 +}
1851 +
1852 +static int rtl8201_config_intr(struct phy_device *phydev)
1853 +{
1854 + u16 val;
1855 + int err;
1856 +
1857 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1858 + err = rtl8201_ack_interrupt(phydev);
1859 + if (err)
1860 + return err;
1861 +
1862 + val = BIT(13) | BIT(12) | BIT(11);
1863 + err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
1864 + } else {
1865 + val = 0;
1866 + err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
1867 + if (err)
1868 + return err;
1869 +
1870 + err = rtl8201_ack_interrupt(phydev);
1871 + }
1872 +
1873 + return err;
1874 +}
1875 +
1876 +static int rtl8211b_config_intr(struct phy_device *phydev)
1877 +{
1878 + int err;
1879 +
1880 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1881 + err = rtl821x_ack_interrupt(phydev);
1882 + if (err)
1883 + return err;
1884 +
1885 + err = phy_write(phydev, RTL821x_INER,
1886 + RTL8211B_INER_INIT);
1887 + } else {
1888 + err = phy_write(phydev, RTL821x_INER, 0);
1889 + if (err)
1890 + return err;
1891 +
1892 + err = rtl821x_ack_interrupt(phydev);
1893 + }
1894 +
1895 + return err;
1896 +}
1897 +
1898 +static int rtl8211e_config_intr(struct phy_device *phydev)
1899 +{
1900 + int err;
1901 +
1902 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1903 + err = rtl821x_ack_interrupt(phydev);
1904 + if (err)
1905 + return err;
1906 +
1907 + err = phy_write(phydev, RTL821x_INER,
1908 + RTL8211E_INER_LINK_STATUS);
1909 + } else {
1910 + err = phy_write(phydev, RTL821x_INER, 0);
1911 + if (err)
1912 + return err;
1913 +
1914 + err = rtl821x_ack_interrupt(phydev);
1915 + }
1916 +
1917 + return err;
1918 +}
1919 +
1920 +static int rtl8211f_config_intr(struct phy_device *phydev)
1921 +{
1922 + u16 val;
1923 + int err;
1924 +
1925 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1926 + err = rtl8211f_ack_interrupt(phydev);
1927 + if (err)
1928 + return err;
1929 +
1930 + val = RTL8211F_INER_LINK_STATUS;
1931 + err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
1932 + } else {
1933 + val = 0;
1934 + err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
1935 + if (err)
1936 + return err;
1937 +
1938 + err = rtl8211f_ack_interrupt(phydev);
1939 + }
1940 +
1941 + return err;
1942 +}
1943 +
1944 +static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
1945 +{
1946 + int irq_status;
1947 +
1948 + irq_status = phy_read(phydev, RTL8201F_ISR);
1949 + if (irq_status < 0) {
1950 + phy_error(phydev);
1951 + return IRQ_NONE;
1952 + }
1953 +
1954 + if (!(irq_status & RTL8201F_ISR_MASK))
1955 + return IRQ_NONE;
1956 +
1957 + phy_trigger_machine(phydev);
1958 +
1959 + return IRQ_HANDLED;
1960 +}
1961 +
1962 +static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
1963 +{
1964 + int irq_status, irq_enabled;
1965 +
1966 + irq_status = phy_read(phydev, RTL821x_INSR);
1967 + if (irq_status < 0) {
1968 + phy_error(phydev);
1969 + return IRQ_NONE;
1970 + }
1971 +
1972 + irq_enabled = phy_read(phydev, RTL821x_INER);
1973 + if (irq_enabled < 0) {
1974 + phy_error(phydev);
1975 + return IRQ_NONE;
1976 + }
1977 +
1978 + if (!(irq_status & irq_enabled))
1979 + return IRQ_NONE;
1980 +
1981 + phy_trigger_machine(phydev);
1982 +
1983 + return IRQ_HANDLED;
1984 +}
1985 +
1986 +static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
1987 +{
1988 + int irq_status;
1989 +
1990 + irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
1991 + if (irq_status < 0) {
1992 + phy_error(phydev);
1993 + return IRQ_NONE;
1994 + }
1995 +
1996 + if (!(irq_status & RTL8211F_INER_LINK_STATUS))
1997 + return IRQ_NONE;
1998 +
1999 + phy_trigger_machine(phydev);
2000 +
2001 + return IRQ_HANDLED;
2002 +}
2003 +
2004 +static int rtl8211_config_aneg(struct phy_device *phydev)
2005 +{
2006 + int ret;
2007 +
2008 + ret = genphy_config_aneg(phydev);
2009 + if (ret < 0)
2010 + return ret;
2011 +
2012 + /* Quirk was copied from vendor driver. Unfortunately it includes no
2013 + * description of the magic numbers.
2014 + */
2015 + if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
2016 + phy_write(phydev, 0x17, 0x2138);
2017 + phy_write(phydev, 0x0e, 0x0260);
2018 + } else {
2019 + phy_write(phydev, 0x17, 0x2108);
2020 + phy_write(phydev, 0x0e, 0x0000);
2021 + }
2022 +
2023 + return 0;
2024 +}
2025 +
2026 +static int rtl8211c_config_init(struct phy_device *phydev)
2027 +{
2028 + /* RTL8211C has an issue when operating in Gigabit slave mode */
2029 + return phy_set_bits(phydev, MII_CTRL1000,
2030 + CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
2031 +}
2032 +
2033 +static int rtl8211f_config_init(struct phy_device *phydev)
2034 +{
2035 + struct rtl821x_priv *priv = phydev->priv;
2036 + struct device *dev = &phydev->mdio.dev;
2037 + u16 val_txdly, val_rxdly;
2038 + int ret;
2039 +
2040 + ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
2041 + RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
2042 + priv->phycr1);
2043 + if (ret < 0) {
2044 + dev_err(dev, "aldps mode configuration failed: %pe\n",
2045 + ERR_PTR(ret));
2046 + return ret;
2047 + }
2048 +
2049 + switch (phydev->interface) {
2050 + case PHY_INTERFACE_MODE_RGMII:
2051 + val_txdly = 0;
2052 + val_rxdly = 0;
2053 + break;
2054 +
2055 + case PHY_INTERFACE_MODE_RGMII_RXID:
2056 + val_txdly = 0;
2057 + val_rxdly = RTL8211F_RX_DELAY;
2058 + break;
2059 +
2060 + case PHY_INTERFACE_MODE_RGMII_TXID:
2061 + val_txdly = RTL8211F_TX_DELAY;
2062 + val_rxdly = 0;
2063 + break;
2064 +
2065 + case PHY_INTERFACE_MODE_RGMII_ID:
2066 + val_txdly = RTL8211F_TX_DELAY;
2067 + val_rxdly = RTL8211F_RX_DELAY;
2068 + break;
2069 +
2070 + default: /* the rest of the modes imply leaving delay as is. */
2071 + return 0;
2072 + }
2073 +
2074 + ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
2075 + val_txdly);
2076 + if (ret < 0) {
2077 + dev_err(dev, "Failed to update the TX delay register\n");
2078 + return ret;
2079 + } else if (ret) {
2080 + dev_dbg(dev,
2081 + "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
2082 + val_txdly ? "Enabling" : "Disabling");
2083 + } else {
2084 + dev_dbg(dev,
2085 + "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
2086 + val_txdly ? "enabled" : "disabled");
2087 + }
2088 +
2089 + ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
2090 + val_rxdly);
2091 + if (ret < 0) {
2092 + dev_err(dev, "Failed to update the RX delay register\n");
2093 + return ret;
2094 + } else if (ret) {
2095 + dev_dbg(dev,
2096 + "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
2097 + val_rxdly ? "Enabling" : "Disabling");
2098 + } else {
2099 + dev_dbg(dev,
2100 + "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
2101 + val_rxdly ? "enabled" : "disabled");
2102 + }
2103 +
2104 + if (priv->has_phycr2) {
2105 + ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
2106 + RTL8211F_CLKOUT_EN, priv->phycr2);
2107 + if (ret < 0) {
2108 + dev_err(dev, "clkout configuration failed: %pe\n",
2109 + ERR_PTR(ret));
2110 + return ret;
2111 + }
2112 +
2113 + return genphy_soft_reset(phydev);
2114 + }
2115 +
2116 + return 0;
2117 +}
2118 +
2119 +static int rtl821x_suspend(struct phy_device *phydev)
2120 +{
2121 + struct rtl821x_priv *priv = phydev->priv;
2122 + int ret = 0;
2123 +
2124 + if (!phydev->wol_enabled) {
2125 + ret = genphy_suspend(phydev);
2126 +
2127 + if (ret)
2128 + return ret;
2129 +
2130 + clk_disable_unprepare(priv->clk);
2131 + }
2132 +
2133 + return ret;
2134 +}
2135 +
2136 +static int rtl821x_resume(struct phy_device *phydev)
2137 +{
2138 + struct rtl821x_priv *priv = phydev->priv;
2139 + int ret;
2140 +
2141 + if (!phydev->wol_enabled)
2142 + clk_prepare_enable(priv->clk);
2143 +
2144 + ret = genphy_resume(phydev);
2145 + if (ret < 0)
2146 + return ret;
2147 +
2148 + msleep(20);
2149 +
2150 + return 0;
2151 +}
2152 +
2153 +static int rtl8211f_led_hw_is_supported(struct phy_device *phydev, u8 index,
2154 + unsigned long rules)
2155 +{
2156 + const unsigned long mask = BIT(TRIGGER_NETDEV_LINK_10) |
2157 + BIT(TRIGGER_NETDEV_LINK_100) |
2158 + BIT(TRIGGER_NETDEV_LINK_1000) |
2159 + BIT(TRIGGER_NETDEV_RX) |
2160 + BIT(TRIGGER_NETDEV_TX);
2161 +
2162 + /* The RTL8211F PHY supports these LED settings on up to three LEDs:
2163 + * - Link: Configurable subset of 10/100/1000 link rates
2164 + * - Active: Blink on activity, RX or TX is not differentiated
2165 + * The Active option has two modes, A and B:
2166 + * - A: Link and Active indication at configurable, but matching,
2167 + * subset of 10/100/1000 link rates
2168 + * - B: Link indication at configurable subset of 10/100/1000 link
2169 + * rates and Active indication always at all three 10+100+1000
2170 + * link rates.
2171 + * This code currently uses mode B only.
2172 + */
2173 +
2174 + if (index >= RTL8211F_LED_COUNT)
2175 + return -EINVAL;
2176 +
2177 + /* Filter out any other unsupported triggers. */
2178 + if (rules & ~mask)
2179 + return -EOPNOTSUPP;
2180 +
2181 + /* RX and TX are not differentiated, either both are set or not set. */
2182 + if (!(rules & BIT(TRIGGER_NETDEV_RX)) ^ !(rules & BIT(TRIGGER_NETDEV_TX)))
2183 + return -EOPNOTSUPP;
2184 +
2185 + return 0;
2186 +}
2187 +
2188 +static int rtl8211f_led_hw_control_get(struct phy_device *phydev, u8 index,
2189 + unsigned long *rules)
2190 +{
2191 + int val;
2192 +
2193 + if (index >= RTL8211F_LED_COUNT)
2194 + return -EINVAL;
2195 +
2196 + val = phy_read_paged(phydev, 0xd04, RTL8211F_LEDCR);
2197 + if (val < 0)
2198 + return val;
2199 +
2200 + val >>= RTL8211F_LEDCR_SHIFT * index;
2201 + val &= RTL8211F_LEDCR_MASK;
2202 +
2203 + if (val & RTL8211F_LEDCR_LINK_10)
2204 + set_bit(TRIGGER_NETDEV_LINK_10, rules);
2205 +
2206 + if (val & RTL8211F_LEDCR_LINK_100)
2207 + set_bit(TRIGGER_NETDEV_LINK_100, rules);
2208 +
2209 + if (val & RTL8211F_LEDCR_LINK_1000)
2210 + set_bit(TRIGGER_NETDEV_LINK_1000, rules);
2211 +
2212 + if (val & RTL8211F_LEDCR_ACT_TXRX) {
2213 + set_bit(TRIGGER_NETDEV_RX, rules);
2214 + set_bit(TRIGGER_NETDEV_TX, rules);
2215 + }
2216 +
2217 + return 0;
2218 +}
2219 +
2220 +static int rtl8211f_led_hw_control_set(struct phy_device *phydev, u8 index,
2221 + unsigned long rules)
2222 +{
2223 + const u16 mask = RTL8211F_LEDCR_MASK << (RTL8211F_LEDCR_SHIFT * index);
2224 + u16 reg = 0;
2225 +
2226 + if (index >= RTL8211F_LED_COUNT)
2227 + return -EINVAL;
2228 +
2229 + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
2230 + reg |= RTL8211F_LEDCR_LINK_10;
2231 +
2232 + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
2233 + reg |= RTL8211F_LEDCR_LINK_100;
2234 +
2235 + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
2236 + reg |= RTL8211F_LEDCR_LINK_1000;
2237 +
2238 + if (test_bit(TRIGGER_NETDEV_RX, &rules) ||
2239 + test_bit(TRIGGER_NETDEV_TX, &rules)) {
2240 + reg |= RTL8211F_LEDCR_ACT_TXRX;
2241 + }
2242 +
2243 + reg <<= RTL8211F_LEDCR_SHIFT * index;
2244 + reg |= RTL8211F_LEDCR_MODE; /* Mode B */
2245 +
2246 + return phy_modify_paged(phydev, 0xd04, RTL8211F_LEDCR, mask, reg);
2247 +}
2248 +
2249 +static int rtl8211e_config_init(struct phy_device *phydev)
2250 +{
2251 + int ret = 0, oldpage;
2252 + u16 val;
2253 +
2254 + /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
2255 + switch (phydev->interface) {
2256 + case PHY_INTERFACE_MODE_RGMII:
2257 + val = RTL8211E_CTRL_DELAY | 0;
2258 + break;
2259 + case PHY_INTERFACE_MODE_RGMII_ID:
2260 + val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
2261 + break;
2262 + case PHY_INTERFACE_MODE_RGMII_RXID:
2263 + val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
2264 + break;
2265 + case PHY_INTERFACE_MODE_RGMII_TXID:
2266 + val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
2267 + break;
2268 + default: /* the rest of the modes imply leaving delays as is. */
2269 + return 0;
2270 + }
2271 +
2272 + /* According to a sample driver there is a 0x1c config register on the
2273 + * 0xa4 extension page (0x7) layout. It can be used to disable/enable
2274 + * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
2275 + * The configuration register definition:
2276 + * 14 = reserved
2277 + * 13 = Force Tx RX Delay controlled by bit12 bit11,
2278 + * 12 = RX Delay, 11 = TX Delay
2279 + * 10:0 = Test && debug settings reserved by realtek
2280 + */
2281 + oldpage = phy_select_page(phydev, 0x7);
2282 + if (oldpage < 0)
2283 + goto err_restore_page;
2284 +
2285 + ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
2286 + if (ret)
2287 + goto err_restore_page;
2288 +
2289 + ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
2290 + | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
2291 + val);
2292 +
2293 +err_restore_page:
2294 + return phy_restore_page(phydev, oldpage, ret);
2295 +}
2296 +
2297 +static int rtl8211b_suspend(struct phy_device *phydev)
2298 +{
2299 + phy_write(phydev, MII_MMD_DATA, BIT(9));
2300 +
2301 + return genphy_suspend(phydev);
2302 +}
2303 +
2304 +static int rtl8211b_resume(struct phy_device *phydev)
2305 +{
2306 + phy_write(phydev, MII_MMD_DATA, 0);
2307 +
2308 + return genphy_resume(phydev);
2309 +}
2310 +
2311 +static int rtl8366rb_config_init(struct phy_device *phydev)
2312 +{
2313 + int ret;
2314 +
2315 + ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
2316 + RTL8366RB_POWER_SAVE_ON);
2317 + if (ret) {
2318 + dev_err(&phydev->mdio.dev,
2319 + "error enabling power management\n");
2320 + }
2321 +
2322 + return ret;
2323 +}
2324 +
2325 +/* get actual speed to cover the downshift case */
2326 +static void rtlgen_decode_physr(struct phy_device *phydev, int val)
2327 +{
2328 + /* bit 3
2329 + * 0: Half Duplex
2330 + * 1: Full Duplex
2331 + */
2332 + if (val & RTL_VND2_PHYSR_DUPLEX)
2333 + phydev->duplex = DUPLEX_FULL;
2334 + else
2335 + phydev->duplex = DUPLEX_HALF;
2336 +
2337 + switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
2338 + case 0x0000:
2339 + phydev->speed = SPEED_10;
2340 + break;
2341 + case 0x0010:
2342 + phydev->speed = SPEED_100;
2343 + break;
2344 + case 0x0020:
2345 + phydev->speed = SPEED_1000;
2346 + break;
2347 + case 0x0200:
2348 + phydev->speed = SPEED_10000;
2349 + break;
2350 + case 0x0210:
2351 + phydev->speed = SPEED_2500;
2352 + break;
2353 + case 0x0220:
2354 + phydev->speed = SPEED_5000;
2355 + break;
2356 + default:
2357 + break;
2358 + }
2359 +
2360 + /* bit 11
2361 + * 0: Slave Mode
2362 + * 1: Master Mode
2363 + */
2364 + if (phydev->speed >= 1000) {
2365 + if (val & RTL_VND2_PHYSR_MASTER)
2366 + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
2367 + else
2368 + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
2369 + } else {
2370 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
2371 + }
2372 +}
2373 +
2374 +static int rtlgen_read_status(struct phy_device *phydev)
2375 +{
2376 + int ret, val;
2377 +
2378 + ret = genphy_read_status(phydev);
2379 + if (ret < 0)
2380 + return ret;
2381 +
2382 + if (!phydev->link)
2383 + return 0;
2384 +
2385 + val = phy_read_paged(phydev, 0xa43, 0x12);
2386 + if (val < 0)
2387 + return val;
2388 +
2389 + rtlgen_decode_physr(phydev, val);
2390 +
2391 + return 0;
2392 +}
2393 +
2394 +static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
2395 +{
2396 + int ret;
2397 +
2398 + if (devnum == MDIO_MMD_VEND2) {
2399 + rtl821x_write_page(phydev, regnum >> 4);
2400 + ret = __phy_read(phydev, 0x10 + ((regnum & 0xf) >> 1));
2401 + rtl821x_write_page(phydev, 0);
2402 + } else if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
2403 + rtl821x_write_page(phydev, 0xa5c);
2404 + ret = __phy_read(phydev, 0x12);
2405 + rtl821x_write_page(phydev, 0);
2406 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
2407 + rtl821x_write_page(phydev, 0xa5d);
2408 + ret = __phy_read(phydev, 0x10);
2409 + rtl821x_write_page(phydev, 0);
2410 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
2411 + rtl821x_write_page(phydev, 0xa5d);
2412 + ret = __phy_read(phydev, 0x11);
2413 + rtl821x_write_page(phydev, 0);
2414 + } else {
2415 + ret = -EOPNOTSUPP;
2416 + }
2417 +
2418 + return ret;
2419 +}
2420 +
2421 +static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
2422 + u16 val)
2423 +{
2424 + int ret;
2425 +
2426 + if (devnum == MDIO_MMD_VEND2) {
2427 + rtl821x_write_page(phydev, regnum >> 4);
2428 + ret = __phy_write(phydev, 0x10 + ((regnum & 0xf) >> 1), val);
2429 + rtl821x_write_page(phydev, 0);
2430 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
2431 + rtl821x_write_page(phydev, 0xa5d);
2432 + ret = __phy_write(phydev, 0x10, val);
2433 + rtl821x_write_page(phydev, 0);
2434 + } else {
2435 + ret = -EOPNOTSUPP;
2436 + }
2437 +
2438 + return ret;
2439 +}
2440 +
2441 +static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
2442 +{
2443 + int ret = rtlgen_read_mmd(phydev, devnum, regnum);
2444 +
2445 + if (ret != -EOPNOTSUPP)
2446 + return ret;
2447 +
2448 + if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
2449 + rtl821x_write_page(phydev, 0xa6e);
2450 + ret = __phy_read(phydev, 0x16);
2451 + rtl821x_write_page(phydev, 0);
2452 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
2453 + rtl821x_write_page(phydev, 0xa6d);
2454 + ret = __phy_read(phydev, 0x12);
2455 + rtl821x_write_page(phydev, 0);
2456 + } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
2457 + rtl821x_write_page(phydev, 0xa6d);
2458 + ret = __phy_read(phydev, 0x10);
2459 + rtl821x_write_page(phydev, 0);
2460 + }
2461 +
2462 + return ret;
2463 +}
2464 +
2465 +static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
2466 + u16 val)
2467 +{
2468 + int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
2469 +
2470 + if (ret != -EOPNOTSUPP)
2471 + return ret;
2472 +
2473 + if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
2474 + rtl821x_write_page(phydev, 0xa6d);
2475 + ret = __phy_write(phydev, 0x12, val);
2476 + rtl821x_write_page(phydev, 0);
2477 + }
2478 +
2479 + return ret;
2480 +}
2481 +
2482 +static int rtl822xb_config_init(struct phy_device *phydev)
2483 +{
2484 + bool has_2500, has_sgmii;
2485 + u16 mode;
2486 + int ret;
2487 +
2488 + has_2500 = test_bit(PHY_INTERFACE_MODE_2500BASEX,
2489 + phydev->host_interfaces) ||
2490 + phydev->interface == PHY_INTERFACE_MODE_2500BASEX;
2491 +
2492 + has_sgmii = test_bit(PHY_INTERFACE_MODE_SGMII,
2493 + phydev->host_interfaces) ||
2494 + phydev->interface == PHY_INTERFACE_MODE_SGMII;
2495 +
2496 + /* fill in possible interfaces */
2497 + __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces,
2498 + has_2500);
2499 + __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces,
2500 + has_sgmii);
2501 +
2502 + if (!has_2500 && !has_sgmii)
2503 + return 0;
2504 +
2505 + /* determine SerDes option mode */
2506 + if (has_2500 && !has_sgmii) {
2507 + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX;
2508 + phydev->rate_matching = RATE_MATCH_PAUSE;
2509 + } else {
2510 + mode = RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII;
2511 + phydev->rate_matching = RATE_MATCH_NONE;
2512 + }
2513 +
2514 + /* the following sequence with magic numbers sets up the SerDes
2515 + * option mode
2516 + */
2517 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x75f3, 0);
2518 + if (ret < 0)
2519 + return ret;
2520 +
2521 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND1,
2522 + RTL822X_VND1_SERDES_OPTION,
2523 + RTL822X_VND1_SERDES_OPTION_MODE_MASK,
2524 + mode);
2525 + if (ret < 0)
2526 + return ret;
2527 +
2528 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6a04, 0x0503);
2529 + if (ret < 0)
2530 + return ret;
2531 +
2532 + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f10, 0xd455);
2533 + if (ret < 0)
2534 + return ret;
2535 +
2536 + return phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x6f11, 0x8020);
2537 +}
2538 +
2539 +static int rtl822xb_get_rate_matching(struct phy_device *phydev,
2540 + phy_interface_t iface)
2541 +{
2542 + int val;
2543 +
2544 + /* Only rate matching at 2500base-x */
2545 + if (iface != PHY_INTERFACE_MODE_2500BASEX)
2546 + return RATE_MATCH_NONE;
2547 +
2548 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_OPTION);
2549 + if (val < 0)
2550 + return val;
2551 +
2552 + if ((val & RTL822X_VND1_SERDES_OPTION_MODE_MASK) ==
2553 + RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX)
2554 + return RATE_MATCH_PAUSE;
2555 +
2556 + /* RTL822X_VND1_SERDES_OPTION_MODE_2500BASEX_SGMII */
2557 + return RATE_MATCH_NONE;
2558 +}
2559 +
2560 +static int rtl822x_get_features(struct phy_device *phydev)
2561 +{
2562 + int val;
2563 +
2564 + val = phy_read_paged(phydev, 0xa61, 0x13);
2565 + if (val < 0)
2566 + return val;
2567 +
2568 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2569 + phydev->supported, val & MDIO_PMA_SPEED_2_5G);
2570 + linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2571 + phydev->supported, val & MDIO_PMA_SPEED_5G);
2572 + linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2573 + phydev->supported, val & MDIO_SPEED_10G);
2574 +
2575 + return genphy_read_abilities(phydev);
2576 +}
2577 +
2578 +static int rtl822x_config_aneg(struct phy_device *phydev)
2579 +{
2580 + int ret = 0;
2581 +
2582 + if (phydev->autoneg == AUTONEG_ENABLE) {
2583 + u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising);
2584 +
2585 + ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
2586 + MDIO_AN_10GBT_CTRL_ADV2_5G |
2587 + MDIO_AN_10GBT_CTRL_ADV5G,
2588 + adv);
2589 + if (ret < 0)
2590 + return ret;
2591 + }
2592 +
2593 + return __genphy_config_aneg(phydev, ret);
2594 +}
2595 +
2596 +static void rtl822xb_update_interface(struct phy_device *phydev)
2597 +{
2598 + int val;
2599 +
2600 + if (!phydev->link)
2601 + return;
2602 +
2603 + /* Change interface according to serdes mode */
2604 + val = phy_read_mmd(phydev, MDIO_MMD_VEND1, RTL822X_VND1_SERDES_CTRL3);
2605 + if (val < 0)
2606 + return;
2607 +
2608 + switch (val & RTL822X_VND1_SERDES_CTRL3_MODE_MASK) {
2609 + case RTL822X_VND1_SERDES_CTRL3_MODE_2500BASEX:
2610 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
2611 + break;
2612 + case RTL822X_VND1_SERDES_CTRL3_MODE_SGMII:
2613 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
2614 + break;
2615 + }
2616 +}
2617 +
2618 +static int rtl822x_read_status(struct phy_device *phydev)
2619 +{
2620 + int lpadv, ret;
2621 +
2622 + ret = rtlgen_read_status(phydev);
2623 + if (ret < 0)
2624 + return ret;
2625 +
2626 + if (phydev->autoneg == AUTONEG_DISABLE ||
2627 + !phydev->autoneg_complete) {
2628 + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
2629 + return 0;
2630 + }
2631 +
2632 + lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
2633 + if (lpadv < 0)
2634 + return lpadv;
2635 +
2636 + mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv);
2637 +
2638 + return 0;
2639 +}
2640 +
2641 +static int rtl822xb_read_status(struct phy_device *phydev)
2642 +{
2643 + int ret;
2644 +
2645 + ret = rtl822x_read_status(phydev);
2646 + if (ret < 0)
2647 + return ret;
2648 +
2649 + rtl822xb_update_interface(phydev);
2650 +
2651 + return 0;
2652 +}
2653 +
2654 +static int rtl822x_c45_get_features(struct phy_device *phydev)
2655 +{
2656 + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT,
2657 + phydev->supported);
2658 +
2659 + return genphy_c45_pma_read_abilities(phydev);
2660 +}
2661 +
2662 +static int rtl822x_c45_config_aneg(struct phy_device *phydev)
2663 +{
2664 + bool changed = false;
2665 + int ret, val;
2666 +
2667 + if (phydev->autoneg == AUTONEG_DISABLE)
2668 + return genphy_c45_pma_setup_forced(phydev);
2669 +
2670 + ret = genphy_c45_an_config_aneg(phydev);
2671 + if (ret < 0)
2672 + return ret;
2673 + if (ret > 0)
2674 + changed = true;
2675 +
2676 + val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
2677 +
2678 + /* Vendor register as C45 has no standardized support for 1000BaseT */
2679 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_VEND2, RTL822X_VND2_GBCR,
2680 + ADVERTISE_1000FULL, val);
2681 + if (ret < 0)
2682 + return ret;
2683 + if (ret > 0)
2684 + changed = true;
2685 +
2686 + return genphy_c45_check_and_restart_aneg(phydev, changed);
2687 +}
2688 +
2689 +static int rtl822x_c45_read_status(struct phy_device *phydev)
2690 +{
2691 + int ret, val;
2692 +
2693 + ret = genphy_c45_read_status(phydev);
2694 + if (ret < 0)
2695 + return ret;
2696 +
2697 + if (phydev->autoneg == AUTONEG_DISABLE ||
2698 + !genphy_c45_aneg_done(phydev))
2699 + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 0);
2700 +
2701 + /* Vendor register as C45 has no standardized support for 1000BaseT */
2702 + if (phydev->autoneg == AUTONEG_ENABLE) {
2703 + val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
2704 + RTL822X_VND2_GANLPAR);
2705 + if (val < 0)
2706 + return val;
2707 +
2708 + mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val);
2709 + }
2710 +
2711 + if (!phydev->link)
2712 + return 0;
2713 +
2714 + /* Read actual speed from vendor register. */
2715 + val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
2716 + if (val < 0)
2717 + return val;
2718 +
2719 + rtlgen_decode_physr(phydev, val);
2720 +
2721 + return 0;
2722 +}
2723 +
2724 +static int rtl822xb_c45_read_status(struct phy_device *phydev)
2725 +{
2726 + int ret;
2727 +
2728 + ret = rtl822x_c45_read_status(phydev);
2729 + if (ret < 0)
2730 + return ret;
2731 +
2732 + rtl822xb_update_interface(phydev);
2733 +
2734 + return 0;
2735 +}
2736 +
2737 +static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
2738 +{
2739 + int val;
2740 +
2741 + phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
2742 + val = phy_read(phydev, 0x13);
2743 + phy_write(phydev, RTL821x_PAGE_SELECT, 0);
2744 +
2745 + return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
2746 +}
2747 +
2748 +/* On internal PHY's MMD reads over C22 always return 0.
2749 + * Check a MMD register which is known to be non-zero.
2750 + */
2751 +static bool rtlgen_supports_mmd(struct phy_device *phydev)
2752 +{
2753 + int val;
2754 +
2755 + phy_lock_mdio_bus(phydev);
2756 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
2757 + __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
2758 + __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
2759 + val = __phy_read(phydev, MII_MMD_DATA);
2760 + phy_unlock_mdio_bus(phydev);
2761 +
2762 + return val > 0;
2763 +}
2764 +
2765 +static int rtlgen_match_phy_device(struct phy_device *phydev)
2766 +{
2767 + return phydev->phy_id == RTL_GENERIC_PHYID &&
2768 + !rtlgen_supports_2_5gbps(phydev);
2769 +}
2770 +
2771 +static int rtl8226_match_phy_device(struct phy_device *phydev)
2772 +{
2773 + return phydev->phy_id == RTL_GENERIC_PHYID &&
2774 + rtlgen_supports_2_5gbps(phydev) &&
2775 + rtlgen_supports_mmd(phydev);
2776 +}
2777 +
2778 +static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
2779 + bool is_c45)
2780 +{
2781 + if (phydev->is_c45)
2782 + return is_c45 && (id == phydev->c45_ids.device_ids[1]);
2783 + else
2784 + return !is_c45 && (id == phydev->phy_id);
2785 +}
2786 +
2787 +static int rtl8221b_match_phy_device(struct phy_device *phydev)
2788 +{
2789 + return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
2790 +}
2791 +
2792 +static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
2793 +{
2794 + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
2795 +}
2796 +
2797 +static int rtl8221b_vb_cg_c45_match_phy_device(struct phy_device *phydev)
2798 +{
2799 + return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, true);
2800 +}
2801 +
2802 +static int rtl8221b_vn_cg_c22_match_phy_device(struct phy_device *phydev)
2803 +{
2804 + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, false);
2805 +}
2806 +
2807 +static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
2808 +{
2809 + return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
2810 +}
2811 +
2812 +static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
2813 +{
2814 + if (phydev->is_c45)
2815 + return false;
2816 +
2817 + switch (phydev->phy_id) {
2818 + case RTL_GENERIC_PHYID:
2819 + case RTL_8221B:
2820 + case RTL_8251B:
2821 + case 0x001cc841:
2822 + break;
2823 + default:
2824 + return false;
2825 + }
2826 +
2827 + return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
2828 +}
2829 +
2830 +static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
2831 +{
2832 + return rtlgen_is_c45_match(phydev, RTL_8251B, true);
2833 +}
2834 +
2835 +static int rtlgen_resume(struct phy_device *phydev)
2836 +{
2837 + int ret = genphy_resume(phydev);
2838 +
2839 + /* Internal PHY's from RTL8168h up may not be instantly ready */
2840 + msleep(20);
2841 +
2842 + return ret;
2843 +}
2844 +
2845 +static int rtlgen_c45_resume(struct phy_device *phydev)
2846 +{
2847 + int ret = genphy_c45_pma_resume(phydev);
2848 +
2849 + msleep(20);
2850 +
2851 + return ret;
2852 +}
2853 +
2854 +static int rtl9000a_config_init(struct phy_device *phydev)
2855 +{
2856 + phydev->autoneg = AUTONEG_DISABLE;
2857 + phydev->speed = SPEED_100;
2858 + phydev->duplex = DUPLEX_FULL;
2859 +
2860 + return 0;
2861 +}
2862 +
2863 +static int rtl9000a_config_aneg(struct phy_device *phydev)
2864 +{
2865 + int ret;
2866 + u16 ctl = 0;
2867 +
2868 + switch (phydev->master_slave_set) {
2869 + case MASTER_SLAVE_CFG_MASTER_FORCE:
2870 + ctl |= CTL1000_AS_MASTER;
2871 + break;
2872 + case MASTER_SLAVE_CFG_SLAVE_FORCE:
2873 + break;
2874 + case MASTER_SLAVE_CFG_UNKNOWN:
2875 + case MASTER_SLAVE_CFG_UNSUPPORTED:
2876 + return 0;
2877 + default:
2878 + phydev_warn(phydev, "Unsupported Master/Slave mode\n");
2879 + return -EOPNOTSUPP;
2880 + }
2881 +
2882 + ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
2883 + if (ret == 1)
2884 + ret = genphy_soft_reset(phydev);
2885 +
2886 + return ret;
2887 +}
2888 +
2889 +static int rtl9000a_read_status(struct phy_device *phydev)
2890 +{
2891 + int ret;
2892 +
2893 + phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
2894 + phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
2895 +
2896 + ret = genphy_update_link(phydev);
2897 + if (ret)
2898 + return ret;
2899 +
2900 + ret = phy_read(phydev, MII_CTRL1000);
2901 + if (ret < 0)
2902 + return ret;
2903 + if (ret & CTL1000_AS_MASTER)
2904 + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
2905 + else
2906 + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
2907 +
2908 + ret = phy_read(phydev, MII_STAT1000);
2909 + if (ret < 0)
2910 + return ret;
2911 + if (ret & LPA_1000MSRES)
2912 + phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
2913 + else
2914 + phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
2915 +
2916 + return 0;
2917 +}
2918 +
2919 +static int rtl9000a_ack_interrupt(struct phy_device *phydev)
2920 +{
2921 + int err;
2922 +
2923 + err = phy_read(phydev, RTL8211F_INSR);
2924 +
2925 + return (err < 0) ? err : 0;
2926 +}
2927 +
2928 +static int rtl9000a_config_intr(struct phy_device *phydev)
2929 +{
2930 + u16 val;
2931 + int err;
2932 +
2933 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2934 + err = rtl9000a_ack_interrupt(phydev);
2935 + if (err)
2936 + return err;
2937 +
2938 + val = (u16)~RTL9000A_GINMR_LINK_STATUS;
2939 + err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2940 + } else {
2941 + val = ~0;
2942 + err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2943 + if (err)
2944 + return err;
2945 +
2946 + err = rtl9000a_ack_interrupt(phydev);
2947 + }
2948 +
2949 + return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
2950 +}
2951 +
2952 +static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
2953 +{
2954 + int irq_status;
2955 +
2956 + irq_status = phy_read(phydev, RTL8211F_INSR);
2957 + if (irq_status < 0) {
2958 + phy_error(phydev);
2959 + return IRQ_NONE;
2960 + }
2961 +
2962 + if (!(irq_status & RTL8211F_INER_LINK_STATUS))
2963 + return IRQ_NONE;
2964 +
2965 + phy_trigger_machine(phydev);
2966 +
2967 + return IRQ_HANDLED;
2968 +}
2969 +
2970 +static struct phy_driver realtek_drvs[] = {
2971 + {
2972 + PHY_ID_MATCH_EXACT(0x00008201),
2973 + .name = "RTL8201CP Ethernet",
2974 + .read_page = rtl821x_read_page,
2975 + .write_page = rtl821x_write_page,
2976 + }, {
2977 + PHY_ID_MATCH_EXACT(0x001cc816),
2978 + .name = "RTL8201F Fast Ethernet",
2979 + .config_intr = &rtl8201_config_intr,
2980 + .handle_interrupt = rtl8201_handle_interrupt,
2981 + .suspend = genphy_suspend,
2982 + .resume = genphy_resume,
2983 + .read_page = rtl821x_read_page,
2984 + .write_page = rtl821x_write_page,
2985 + }, {
2986 + PHY_ID_MATCH_MODEL(0x001cc880),
2987 + .name = "RTL8208 Fast Ethernet",
2988 + .read_mmd = genphy_read_mmd_unsupported,
2989 + .write_mmd = genphy_write_mmd_unsupported,
2990 + .suspend = genphy_suspend,
2991 + .resume = genphy_resume,
2992 + .read_page = rtl821x_read_page,
2993 + .write_page = rtl821x_write_page,
2994 + }, {
2995 + PHY_ID_MATCH_EXACT(0x001cc910),
2996 + .name = "RTL8211 Gigabit Ethernet",
2997 + .config_aneg = rtl8211_config_aneg,
2998 + .read_mmd = &genphy_read_mmd_unsupported,
2999 + .write_mmd = &genphy_write_mmd_unsupported,
3000 + .read_page = rtl821x_read_page,
3001 + .write_page = rtl821x_write_page,
3002 + }, {
3003 + PHY_ID_MATCH_EXACT(0x001cc912),
3004 + .name = "RTL8211B Gigabit Ethernet",
3005 + .config_intr = &rtl8211b_config_intr,
3006 + .handle_interrupt = rtl821x_handle_interrupt,
3007 + .read_mmd = &genphy_read_mmd_unsupported,
3008 + .write_mmd = &genphy_write_mmd_unsupported,
3009 + .suspend = rtl8211b_suspend,
3010 + .resume = rtl8211b_resume,
3011 + .read_page = rtl821x_read_page,
3012 + .write_page = rtl821x_write_page,
3013 + }, {
3014 + PHY_ID_MATCH_EXACT(0x001cc913),
3015 + .name = "RTL8211C Gigabit Ethernet",
3016 + .config_init = rtl8211c_config_init,
3017 + .read_mmd = &genphy_read_mmd_unsupported,
3018 + .write_mmd = &genphy_write_mmd_unsupported,
3019 + .read_page = rtl821x_read_page,
3020 + .write_page = rtl821x_write_page,
3021 + }, {
3022 + PHY_ID_MATCH_EXACT(0x001cc914),
3023 + .name = "RTL8211DN Gigabit Ethernet",
3024 + .config_intr = rtl8211e_config_intr,
3025 + .handle_interrupt = rtl821x_handle_interrupt,
3026 + .suspend = genphy_suspend,
3027 + .resume = genphy_resume,
3028 + .read_page = rtl821x_read_page,
3029 + .write_page = rtl821x_write_page,
3030 + }, {
3031 + PHY_ID_MATCH_EXACT(0x001cc915),
3032 + .name = "RTL8211E Gigabit Ethernet",
3033 + .config_init = &rtl8211e_config_init,
3034 + .config_intr = &rtl8211e_config_intr,
3035 + .handle_interrupt = rtl821x_handle_interrupt,
3036 + .suspend = genphy_suspend,
3037 + .resume = genphy_resume,
3038 + .read_page = rtl821x_read_page,
3039 + .write_page = rtl821x_write_page,
3040 + }, {
3041 + PHY_ID_MATCH_EXACT(0x001cc916),
3042 + .name = "RTL8211F Gigabit Ethernet",
3043 + .probe = rtl821x_probe,
3044 + .config_init = &rtl8211f_config_init,
3045 + .read_status = rtlgen_read_status,
3046 + .config_intr = &rtl8211f_config_intr,
3047 + .handle_interrupt = rtl8211f_handle_interrupt,
3048 + .suspend = rtl821x_suspend,
3049 + .resume = rtl821x_resume,
3050 + .read_page = rtl821x_read_page,
3051 + .write_page = rtl821x_write_page,
3052 + .flags = PHY_ALWAYS_CALL_SUSPEND,
3053 + .led_hw_is_supported = rtl8211f_led_hw_is_supported,
3054 + .led_hw_control_get = rtl8211f_led_hw_control_get,
3055 + .led_hw_control_set = rtl8211f_led_hw_control_set,
3056 + }, {
3057 + PHY_ID_MATCH_EXACT(RTL_8211FVD_PHYID),
3058 + .name = "RTL8211F-VD Gigabit Ethernet",
3059 + .probe = rtl821x_probe,
3060 + .config_init = &rtl8211f_config_init,
3061 + .read_status = rtlgen_read_status,
3062 + .config_intr = &rtl8211f_config_intr,
3063 + .handle_interrupt = rtl8211f_handle_interrupt,
3064 + .suspend = rtl821x_suspend,
3065 + .resume = rtl821x_resume,
3066 + .read_page = rtl821x_read_page,
3067 + .write_page = rtl821x_write_page,
3068 + .flags = PHY_ALWAYS_CALL_SUSPEND,
3069 + }, {
3070 + .name = "Generic FE-GE Realtek PHY",
3071 + .match_phy_device = rtlgen_match_phy_device,
3072 + .read_status = rtlgen_read_status,
3073 + .suspend = genphy_suspend,
3074 + .resume = rtlgen_resume,
3075 + .read_page = rtl821x_read_page,
3076 + .write_page = rtl821x_write_page,
3077 + .read_mmd = rtlgen_read_mmd,
3078 + .write_mmd = rtlgen_write_mmd,
3079 + }, {
3080 + .name = "RTL8226 2.5Gbps PHY",
3081 + .match_phy_device = rtl8226_match_phy_device,
3082 + .get_features = rtl822x_get_features,
3083 + .config_aneg = rtl822x_config_aneg,
3084 + .read_status = rtl822x_read_status,
3085 + .suspend = genphy_suspend,
3086 + .resume = rtlgen_resume,
3087 + .read_page = rtl821x_read_page,
3088 + .write_page = rtl821x_write_page,
3089 + }, {
3090 + .match_phy_device = rtl8221b_match_phy_device,
3091 + .name = "RTL8226B_RTL8221B 2.5Gbps PHY",
3092 + .get_features = rtl822x_get_features,
3093 + .config_aneg = rtl822x_config_aneg,
3094 + .config_init = rtl822xb_config_init,
3095 + .get_rate_matching = rtl822xb_get_rate_matching,
3096 + .read_status = rtl822xb_read_status,
3097 + .suspend = genphy_suspend,
3098 + .resume = rtlgen_resume,
3099 + .read_page = rtl821x_read_page,
3100 + .write_page = rtl821x_write_page,
3101 + }, {
3102 + PHY_ID_MATCH_EXACT(0x001cc838),
3103 + .name = "RTL8226-CG 2.5Gbps PHY",
3104 + .get_features = rtl822x_get_features,
3105 + .config_aneg = rtl822x_config_aneg,
3106 + .read_status = rtl822x_read_status,
3107 + .suspend = genphy_suspend,
3108 + .resume = rtlgen_resume,
3109 + .read_page = rtl821x_read_page,
3110 + .write_page = rtl821x_write_page,
3111 + }, {
3112 + PHY_ID_MATCH_EXACT(0x001cc848),
3113 + .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
3114 + .get_features = rtl822x_get_features,
3115 + .config_aneg = rtl822x_config_aneg,
3116 + .config_init = rtl822xb_config_init,
3117 + .get_rate_matching = rtl822xb_get_rate_matching,
3118 + .read_status = rtl822xb_read_status,
3119 + .suspend = genphy_suspend,
3120 + .resume = rtlgen_resume,
3121 + .read_page = rtl821x_read_page,
3122 + .write_page = rtl821x_write_page,
3123 + }, {
3124 + .match_phy_device = rtl8221b_vb_cg_c22_match_phy_device,
3125 + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
3126 + .get_features = rtl822x_get_features,
3127 + .config_aneg = rtl822x_config_aneg,
3128 + .config_init = rtl822xb_config_init,
3129 + .get_rate_matching = rtl822xb_get_rate_matching,
3130 + .read_status = rtl822xb_read_status,
3131 + .suspend = genphy_suspend,
3132 + .resume = rtlgen_resume,
3133 + .read_page = rtl821x_read_page,
3134 + .write_page = rtl821x_write_page,
3135 + }, {
3136 + .match_phy_device = rtl8221b_vb_cg_c45_match_phy_device,
3137 + .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
3138 + .config_init = rtl822xb_config_init,
3139 + .get_rate_matching = rtl822xb_get_rate_matching,
3140 + .get_features = rtl822x_c45_get_features,
3141 + .config_aneg = rtl822x_c45_config_aneg,
3142 + .read_status = rtl822xb_c45_read_status,
3143 + .suspend = genphy_c45_pma_suspend,
3144 + .resume = rtlgen_c45_resume,
3145 + }, {
3146 + .match_phy_device = rtl8221b_vn_cg_c22_match_phy_device,
3147 + .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
3148 + .get_features = rtl822x_get_features,
3149 + .config_aneg = rtl822x_config_aneg,
3150 + .config_init = rtl822xb_config_init,
3151 + .get_rate_matching = rtl822xb_get_rate_matching,
3152 + .read_status = rtl822xb_read_status,
3153 + .suspend = genphy_suspend,
3154 + .resume = rtlgen_resume,
3155 + .read_page = rtl821x_read_page,
3156 + .write_page = rtl821x_write_page,
3157 + }, {
3158 + .match_phy_device = rtl8221b_vn_cg_c45_match_phy_device,
3159 + .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
3160 + .config_init = rtl822xb_config_init,
3161 + .get_rate_matching = rtl822xb_get_rate_matching,
3162 + .get_features = rtl822x_c45_get_features,
3163 + .config_aneg = rtl822x_c45_config_aneg,
3164 + .read_status = rtl822xb_c45_read_status,
3165 + .suspend = genphy_c45_pma_suspend,
3166 + .resume = rtlgen_c45_resume,
3167 + }, {
3168 + .match_phy_device = rtl8251b_c45_match_phy_device,
3169 + .name = "RTL8251B 5Gbps PHY",
3170 + .get_features = rtl822x_get_features,
3171 + .config_aneg = rtl822x_config_aneg,
3172 + .read_status = rtl822x_read_status,
3173 + .suspend = genphy_suspend,
3174 + .resume = rtlgen_resume,
3175 + .read_page = rtl821x_read_page,
3176 + .write_page = rtl821x_write_page,
3177 + }, {
3178 + .match_phy_device = rtl_internal_nbaset_match_phy_device,
3179 + .name = "Realtek Internal NBASE-T PHY",
3180 + .flags = PHY_IS_INTERNAL,
3181 + .get_features = rtl822x_get_features,
3182 + .config_aneg = rtl822x_config_aneg,
3183 + .read_status = rtl822x_read_status,
3184 + .suspend = genphy_suspend,
3185 + .resume = rtlgen_resume,
3186 + .read_page = rtl821x_read_page,
3187 + .write_page = rtl821x_write_page,
3188 + .read_mmd = rtl822x_read_mmd,
3189 + .write_mmd = rtl822x_write_mmd,
3190 + }, {
3191 + PHY_ID_MATCH_EXACT(0x001ccad0),
3192 + .name = "RTL8224 2.5Gbps PHY",
3193 + .get_features = rtl822x_c45_get_features,
3194 + .config_aneg = rtl822x_c45_config_aneg,
3195 + .read_status = rtl822x_c45_read_status,
3196 + .suspend = genphy_c45_pma_suspend,
3197 + .resume = rtlgen_c45_resume,
3198 + }, {
3199 + PHY_ID_MATCH_EXACT(0x001cc961),
3200 + .name = "RTL8366RB Gigabit Ethernet",
3201 + .config_init = &rtl8366rb_config_init,
3202 + /* These interrupts are handled by the irq controller
3203 + * embedded inside the RTL8366RB, they get unmasked when the
3204 + * irq is requested and ACKed by reading the status register,
3205 + * which is done by the irqchip code.
3206 + */
3207 + .config_intr = genphy_no_config_intr,
3208 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3209 + .suspend = genphy_suspend,
3210 + .resume = genphy_resume,
3211 + }, {
3212 + PHY_ID_MATCH_EXACT(0x001ccb00),
3213 + .name = "RTL9000AA_RTL9000AN Ethernet",
3214 + .features = PHY_BASIC_T1_FEATURES,
3215 + .config_init = rtl9000a_config_init,
3216 + .config_aneg = rtl9000a_config_aneg,
3217 + .read_status = rtl9000a_read_status,
3218 + .config_intr = rtl9000a_config_intr,
3219 + .handle_interrupt = rtl9000a_handle_interrupt,
3220 + .suspend = genphy_suspend,
3221 + .resume = genphy_resume,
3222 + .read_page = rtl821x_read_page,
3223 + .write_page = rtl821x_write_page,
3224 + }, {
3225 + PHY_ID_MATCH_EXACT(0x001cc942),
3226 + .name = "RTL8365MB-VC Gigabit Ethernet",
3227 + /* Interrupt handling analogous to RTL8366RB */
3228 + .config_intr = genphy_no_config_intr,
3229 + .handle_interrupt = genphy_handle_interrupt_no_ack,
3230 + .suspend = genphy_suspend,
3231 + .resume = genphy_resume,
3232 + }, {
3233 + PHY_ID_MATCH_EXACT(0x001cc960),
3234 + .name = "RTL8366S Gigabit Ethernet",
3235 + .suspend = genphy_suspend,
3236 + .resume = genphy_resume,
3237 + .read_mmd = genphy_read_mmd_unsupported,
3238 + .write_mmd = genphy_write_mmd_unsupported,
3239 + },
3240 +};
3241 +
3242 +module_phy_driver(realtek_drvs);
3243 +
3244 +static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
3245 + { PHY_ID_MATCH_VENDOR(0x001cc800) },
3246 + { }
3247 +};
3248 +
3249 +MODULE_DEVICE_TABLE(mdio, realtek_tbl);
Staging tree of David Bauer