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1 From 4db59ee0d7224e0c8008534c9247480a83889034 Mon Sep 17 00:00:00 2001
2 From: Fugang Duan <fugang.duan@nxp.com>
3 Date: Wed, 11 Sep 2019 17:01:45 +0800
4 Subject: [PATCH] tty: serial: lpuart: enable wakeup source for lpuart
5
6 When use lpuart with DMA mode as wake up source, it still switch to
7 cpu mode in .suspend() that enable cpu interrupts RIE and ILIE as
8 wakeup source. Enable the wakeup irq bits in .suspend_noirq() and
9 disable the wakeup irq bits in .resume_noirq().
10
11 For DMA mode, after system resume back, it needs to setup DMA again,
12 if DMA setup is failed, it switchs to CPU mode. .resume() will share
13 the HW setup code with .startup(), so abstract the same code to the
14 api like lpuartx_hw_setup().
15
16 Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
17 ---
18 drivers/tty/serial/fsl_lpuart.c | 285 ++++++++++++++++++++++++++++------------
19 1 file changed, 198 insertions(+), 87 deletions(-)
20
21 --- a/drivers/tty/serial/fsl_lpuart.c
22 +++ b/drivers/tty/serial/fsl_lpuart.c
23 @@ -21,6 +21,7 @@
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 +#include <linux/pinctrl/consumer.h>
28 #include <linux/pm_domain.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/reset.h>
31 @@ -1709,10 +1710,23 @@ static void lpuart_rx_dma_startup(struct
32 }
33 }
34
35 +static void lpuart_hw_setup(struct lpuart_port *sport)
36 +{
37 + unsigned long flags;
38 +
39 + spin_lock_irqsave(&sport->port.lock, flags);
40 +
41 + lpuart_setup_watermark_enable(sport);
42 +
43 + lpuart_rx_dma_startup(sport);
44 + lpuart_tx_dma_startup(sport);
45 +
46 + spin_unlock_irqrestore(&sport->port.lock, flags);
47 +}
48 +
49 static int lpuart_startup(struct uart_port *port)
50 {
51 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
52 - unsigned long flags;
53 unsigned char temp;
54
55 /* determine FIFO size and enable FIFO mode */
56 @@ -1725,14 +1739,7 @@ static int lpuart_startup(struct uart_po
57 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
58 UARTPFIFO_FIFOSIZE_MASK);
59
60 - spin_lock_irqsave(&sport->port.lock, flags);
61 -
62 - lpuart_setup_watermark_enable(sport);
63 -
64 - lpuart_rx_dma_startup(sport);
65 - lpuart_tx_dma_startup(sport);
66 -
67 - spin_unlock_irqrestore(&sport->port.lock, flags);
68 + lpuart_hw_setup(sport);
69
70 return 0;
71 }
72 @@ -1759,11 +1766,27 @@ static void lpuart32_configure(struct lp
73 lpuart32_write(&sport->port, temp, UARTCTRL);
74 }
75
76 +static void lpuart32_hw_setup(struct lpuart_port *sport)
77 +{
78 + unsigned long flags;
79 +
80 + spin_lock_irqsave(&sport->port.lock, flags);
81 +
82 + lpuart32_hw_disable(sport);
83 +
84 + lpuart_rx_dma_startup(sport);
85 + lpuart_tx_dma_startup(sport);
86 +
87 + lpuart32_setup_watermark_enable(sport);
88 + lpuart32_configure(sport);
89 +
90 + spin_unlock_irqrestore(&sport->port.lock, flags);
91 +}
92 +
93 static int lpuart32_startup(struct uart_port *port)
94 {
95 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
96 struct tty_port *tty_port = &sport->port.state->port;
97 - unsigned long flags;
98 unsigned long temp;
99 int ret;
100
101 @@ -1784,17 +1807,8 @@ static int lpuart32_startup(struct uart_
102 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
103 UARTFIFO_FIFOSIZE_MASK);
104
105 - spin_lock_irqsave(&sport->port.lock, flags);
106 -
107 - lpuart32_hw_disable(sport);
108 -
109 - lpuart_rx_dma_startup(sport);
110 - lpuart_tx_dma_startup(sport);
111 -
112 - lpuart32_setup_watermark_enable(sport);
113 - lpuart32_configure(sport);
114 + lpuart32_hw_setup(sport);
115
116 - spin_unlock_irqrestore(&sport->port.lock, flags);
117 return 0;
118 }
119
120 @@ -2852,108 +2866,205 @@ static int lpuart_runtime_resume(struct
121 return lpuart_enable_clks(sport);
122 };
123
124 -static int lpuart_suspend(struct device *dev)
125 +static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
126 {
127 - struct lpuart_port *sport = dev_get_drvdata(dev);
128 - unsigned long temp;
129 - bool irq_wake;
130 - int ret;
131 -
132 - ret = clk_prepare_enable(sport->ipg_clk);
133 - if (ret)
134 - return ret;
135 + unsigned int val;
136
137 if (lpuart_is_32(sport)) {
138 - /* disable Rx/Tx and interrupts */
139 - temp = lpuart32_read(&sport->port, UARTCTRL);
140 - temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
141 - lpuart32_write(&sport->port, temp, UARTCTRL);
142 + val = lpuart32_read(&sport->port, UARTCTRL);
143 + if (on)
144 + val |= (UARTCTRL_RIE | UARTCTRL_ILIE);
145 + else
146 + val &= ~(UARTCTRL_RIE | UARTCTRL_ILIE);
147 + lpuart32_write(&sport->port, val, UARTCTRL);
148 } else {
149 - /* disable Rx/Tx and interrupts */
150 - temp = readb(sport->port.membase + UARTCR2);
151 - temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
152 - writeb(temp, sport->port.membase + UARTCR2);
153 + val = readb(sport->port.membase + UARTCR2);
154 + if (on)
155 + val |= UARTCR2_RIE;
156 + else
157 + val &= ~UARTCR2_RIE;
158 + writeb(val, sport->port.membase + UARTCR2);
159 }
160 +}
161
162 - clk_disable_unprepare(sport->ipg_clk);
163 +static bool lpuart_uport_is_active(struct lpuart_port *sport)
164 +{
165 + struct tty_port *port = &sport->port.state->port;
166 + struct tty_struct *tty;
167 + struct device *tty_dev;
168 + int may_wake = 0;
169
170 - uart_suspend_port(&lpuart_reg, &sport->port);
171 + tty = tty_port_tty_get(port);
172 + if (tty) {
173 + tty_dev = tty->dev;
174 + may_wake = device_may_wakeup(tty_dev);
175 + tty_kref_put(tty);
176 + }
177
178 - /* uart_suspend_port() might set wakeup flag */
179 - irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
180 - if (sport->port.suspended && !irq_wake)
181 - return 0;
182 + if ((tty_port_initialized(port) && may_wake) ||
183 + (!console_suspend_enabled && uart_console(&sport->port)))
184 + return true;
185
186 - if (sport->lpuart_dma_rx_use) {
187 - /*
188 - * EDMA driver during suspend will forcefully release any
189 - * non-idle DMA channels. If port wakeup is enabled or if port
190 - * is console port or 'no_console_suspend' is set the Rx DMA
191 - * cannot resume as as expected, hence gracefully release the
192 - * Rx DMA path before suspend and start Rx DMA path on resume.
193 - */
194 - if (irq_wake) {
195 - lpuart_del_timer_sync(sport);
196 - lpuart_dma_rx_free(&sport->port);
197 - }
198 + return false;
199 +}
200
201 - /* Disable Rx DMA to use UART port as wakeup source */
202 +static int lpuart_suspend_noirq(struct device *dev)
203 +{
204 + struct lpuart_port *sport = dev_get_drvdata(dev);
205 + bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
206 +
207 + if (lpuart_uport_is_active(sport))
208 + serial_lpuart_enable_wakeup(sport, !!irq_wake);
209 +
210 + pinctrl_pm_select_sleep_state(dev);
211 +
212 + return 0;
213 +}
214 +
215 +static int lpuart_resume_noirq(struct device *dev)
216 +{
217 + struct lpuart_port *sport = dev_get_drvdata(dev);
218 + unsigned int val;
219 +
220 + pinctrl_pm_select_default_state(dev);
221 +
222 + if (lpuart_uport_is_active(sport)) {
223 + serial_lpuart_enable_wakeup(sport, false);
224 +
225 + /* clear the wakeup flags */
226 if (lpuart_is_32(sport)) {
227 - temp = lpuart32_read(&sport->port, UARTBAUD);
228 - lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
229 - UARTBAUD);
230 - } else {
231 - writeb(readb(sport->port.membase + UARTCR5) &
232 - ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
233 + val = lpuart32_read(&sport->port, UARTSTAT);
234 + lpuart32_write(&sport->port, val, UARTSTAT);
235 }
236 }
237
238 - if (sport->lpuart_dma_tx_use) {
239 - sport->dma_tx_in_progress = false;
240 - dmaengine_terminate_all(sport->dma_tx_chan);
241 - }
242 -
243 return 0;
244 }
245
246 -static int lpuart_resume(struct device *dev)
247 +static int lpuart_suspend(struct device *dev)
248 {
249 struct lpuart_port *sport = dev_get_drvdata(dev);
250 - bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
251 - int ret;
252 + unsigned long temp;
253 + unsigned long flags;
254
255 - ret = clk_prepare_enable(sport->ipg_clk);
256 - if (ret)
257 - return ret;
258 + uart_suspend_port(&lpuart_reg, &sport->port);
259
260 - if (lpuart_is_32(sport))
261 - lpuart32_setup_watermark_enable(sport);
262 - else
263 - lpuart_setup_watermark_enable(sport);
264 + if (lpuart_uport_is_active(sport)) {
265 + spin_lock_irqsave(&sport->port.lock, flags);
266 + if (lpuart_is_32(sport)) {
267 + temp = lpuart32_read(&sport->port, UARTCTRL);
268 + temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
269 + lpuart32_write(&sport->port, temp, UARTCTRL);
270 + } else {
271 + temp = readb(sport->port.membase + UARTCR2);
272 + temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
273 + writeb(temp, sport->port.membase + UARTCR2);
274 + }
275 + spin_unlock_irqrestore(&sport->port.lock, flags);
276
277 - if (sport->lpuart_dma_rx_use) {
278 - if (irq_wake) {
279 - if (!lpuart_start_rx_dma(sport))
280 - rx_dma_timer_init(sport);
281 - else
282 - sport->lpuart_dma_rx_use = false;
283 + if (sport->lpuart_dma_rx_use) {
284 + /*
285 + * EDMA driver during suspend will forcefully release any
286 + * non-idle DMA channels. If port wakeup is enabled or if port
287 + * is console port or 'no_console_suspend' is set the Rx DMA
288 + * cannot resume as as expected, hence gracefully release the
289 + * Rx DMA path before suspend and start Rx DMA path on resume.
290 + */
291 + lpuart_del_timer_sync(sport);
292 + lpuart_dma_rx_free(&sport->port);
293 +
294 + /* Disable Rx DMA to use UART port as wakeup source */
295 + spin_lock_irqsave(&sport->port.lock, flags);
296 + if (lpuart_is_32(sport)) {
297 + temp = lpuart32_read(&sport->port, UARTBAUD);
298 + lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
299 + UARTBAUD);
300 + } else {
301 + writeb(readb(sport->port.membase + UARTCR5) &
302 + ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
303 + }
304 + spin_unlock_irqrestore(&sport->port.lock, flags);
305 + }
306 +
307 + if (sport->lpuart_dma_tx_use) {
308 + spin_lock_irqsave(&sport->port.lock, flags);
309 + if (lpuart_is_32(sport)) {
310 + temp = lpuart32_read(&sport->port, UARTBAUD);
311 + temp &= ~UARTBAUD_TDMAE;
312 + lpuart32_write(&sport->port, temp, UARTBAUD);
313 + } else {
314 + temp = readb(sport->port.membase + UARTCR5);
315 + temp &= ~UARTCR5_TDMAS;
316 + writeb(temp, sport->port.membase + UARTCR5);
317 + }
318 + spin_unlock_irqrestore(&sport->port.lock, flags);
319 + sport->dma_tx_in_progress = false;
320 + dmaengine_terminate_all(sport->dma_tx_chan);
321 }
322 + } else if (pm_runtime_active(sport->port.dev)) {
323 + lpuart_disable_clks(sport);
324 + pm_runtime_disable(sport->port.dev);
325 + pm_runtime_set_suspended(sport->port.dev);
326 }
327
328 - lpuart_tx_dma_startup(sport);
329 + return 0;
330 +}
331
332 - if (lpuart_is_32(sport))
333 - lpuart32_configure(sport);
334 +static void lpuart_console_fixup(struct lpuart_port *sport)
335 +{
336 + struct tty_port *port = &sport->port.state->port;
337 + struct uart_port *uport = &sport->port;
338 + struct ktermios termios;
339
340 - clk_disable_unprepare(sport->ipg_clk);
341 + /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
342 + * all lost no matter the port is wakeup source.
343 + * For console port, console baud rate setting lost and print messy
344 + * log when enable the console port as wakeup source. To avoid the
345 + * issue happen, user should not enable uart port as wakeup source
346 + * in VLLS mode, or restore console setting here.
347 + */
348 + if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
349 + console_suspend_enabled && uart_console(&sport->port)) {
350 +
351 + mutex_lock(&port->mutex);
352 + memset(&termios, 0, sizeof(struct ktermios));
353 + termios.c_cflag = uport->cons->cflag;
354 + if (port->tty && termios.c_cflag == 0)
355 + termios = port->tty->termios;
356 + uport->ops->set_termios(uport, &termios, NULL);
357 + mutex_unlock(&port->mutex);
358 + }
359 +}
360 +
361 +static int lpuart_resume(struct device *dev)
362 +{
363 + struct lpuart_port *sport = dev_get_drvdata(dev);
364 + int ret;
365
366 + if (lpuart_uport_is_active(sport)) {
367 + if (lpuart_is_32(sport))
368 + lpuart32_hw_setup(sport);
369 + else
370 + lpuart_hw_setup(sport);
371 + } else if (pm_runtime_active(sport->port.dev)) {
372 + ret = lpuart_enable_clks(sport);
373 + if (ret)
374 + return ret;
375 + pm_runtime_set_active(sport->port.dev);
376 + pm_runtime_enable(sport->port.dev);
377 + }
378 +
379 + lpuart_console_fixup(sport);
380 uart_resume_port(&lpuart_reg, &sport->port);
381
382 return 0;
383 }
384 +
385 static const struct dev_pm_ops lpuart_pm_ops = {
386 SET_RUNTIME_PM_OPS(lpuart_runtime_suspend,
387 lpuart_runtime_resume, NULL)
388 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
389 + lpuart_resume_noirq)
390 SET_SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
391 };
392 #define SERIAL_LPUART_PM_OPS (&lpuart_pm_ops)
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