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1 From 5fcaebde5b5cd58630ea70bbfe0c62f8229469c5 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.org>
3 Date: Wed, 25 Mar 2015 17:49:47 +0000
4 Subject: [PATCH] Adding bcm2835-sdhost driver, and an overlay to
5 enable it
6
7 BCM2835 has two SD card interfaces. This driver uses the other one.
8
9 bcm2835-sdhost: Error handling fix, and code clarification
10
11 bcm2835-sdhost: Adding overclocking option
12
13 Allow a different clock speed to be substitued for a requested 50MHz.
14 This option is exposed using the "overclock_50" DT parameter.
15 Note that the sdhost interface is restricted to integer divisions of
16 core_freq, and the highest sensible option for a core_freq of 250MHz
17 is 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too
18 high.
19
20 Use at your own risk.
21
22 bcm2835-sdhost: Round up the overclock, so 62 works for 62.5Mhz
23
24 Also only warn once for each overclock setting.
25
26 bcm2835-sdhost: Improve error handling and recovery
27
28 1) Expose the hw_reset method to the MMC framework, removing many
29 internal calls by the driver.
30
31 2) Reduce overclock setting on error.
32
33 3) Increase timeout to cope with high capacity cards.
34
35 4) Add properties and parameters to control pio_limit and debug.
36
37 5) Reduce messages at probe time.
38
39 bcm2835-sdhost: Further improve overclock back-off
40
41 bcm2835-sdhost: Clear HBLC for PIO mode
42
43 Also update pio_limit default in overlay README.
44
45 bcm2835-sdhost: Add the ERASE capability
46
47 See: https://github.com/raspberrypi/linux/issues/1076
48
49 bcm2835-sdhost: Ignore CRC7 for MMC CMD1
50
51 It seems that the sdhost interface returns CRC7 errors for CMD1,
52 which is the MMC-specific SEND_OP_COND. Returning these errors to
53 the MMC layer causes a downward spiral, but ignoring them seems
54 to be harmless.
55
56 bcm2835-mmc/sdhost: Remove ARCH_BCM2835 differences
57
58 The bcm2835-mmc driver (and -sdhost driver that copied from it)
59 contains code to handle SDIO interrupts in a threaded interrupt
60 handler rather than waking the MMC framework thread. The change
61 follows a patch from Russell King that adds the facility as the
62 preferred way of working.
63
64 However, the new code path is only present in ARCH_BCM2835
65 builds, which I have taken to be a way of testing the waters
66 rather than making the change across the board; I can't see
67 any technical reason why it wouldn't be enabled for MACH_BCM270X
68 builds. So this patch standardises on the ARCH_BCM2835 code,
69 removing the old code paths.
70
71 bcm2835-sdhost: Don't log timeout errors unless debug=1
72
73 The MMC card-discovery process generates timeouts. This is
74 expected behaviour, so reporting it to the user serves no purpose.
75 Suppress the reporting of timeout errors unless the debug flag
76 is on.
77
78 bcm2835-sdhost: Add workaround for odd behaviour on some cards
79
80 For reasons not understood, the sdhost driver fails when reading
81 sectors very near the end of some SD cards. The problem could
82 be related to the similar issue that reading the final sector
83 of any card as part of a multiple read never completes, and the
84 workaround is an extension of the mechanism introduced to solve
85 that problem which ensures those sectors are always read singly.
86
87 bcm2835-sdhost: Major revision
88
89 This is a significant revision of the bcm2835-sdhost driver. It
90 improves on the original in a number of ways:
91
92 1) Through the use of CMD23 for reads it appears to avoid problems
93 reading some sectors on certain high speed cards.
94 2) Better atomicity to prevent crashes.
95 3) Higher performance.
96 4) Activity logging included, for easier diagnosis in the event
97 of a problem.
98
99 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
100
101 bcm2835-sdhost: Restore ATOMIC flag to PIO sg mapping
102
103 Allocation problems have been seen in a wireless driver, and
104 this is the only change which might have been responsible.
105
106 SQUASH: bcm2835-sdhost: Only claim one DMA channel
107
108 With both MMC controllers enabled there are few DMA channels left. The
109 bcm2835-sdhost driver only uses DMA in one direction at a time, so it
110 doesn't need to claim two channels.
111
112 See: https://github.com/raspberrypi/linux/issues/1327
113
114 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
115
116 bcm2835-sdhost: Workaround for "slow" sectors
117
118 Some cards have been seen to cause timeouts after certain sectors are
119 read. This workaround enforces a minimum delay between the stop after
120 reading one of those sectors and a subsequent data command.
121
122 Using CMD23 (SET_BLOCK_COUNT) avoids this problem, so good cards will
123 not be penalised by this workaround.
124
125 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
126
127 bcm2835-sdhost: Firmware manages the clock divisor
128
129 The bcm2835-sdhost driver hands control of the CDIV clock divisor
130 register to matching firmware, allowing it to adjust to a changing
131 core clock. This removes the need to use the performance governor or
132 to enable io_is_busy on the on-demand governor in order to get the
133 best SD performance.
134
135 N.B. As SD clocks must be an integer divisor of the core clock, it is
136 possible that the SD clock for "turbo" mode can be different (even
137 lower) than "normal" mode.
138
139 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
140
141 bcm2835-sdhost: Reset the clock in task context
142
143 Since reprogramming the clock can now involve a round-trip to the
144 firmware it must not be done at atomic context, and a tasklet
145 is not a task.
146
147 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
148
149 bcm2835-sdhost: Don't exit cmd wait loop on error
150
151 The FAIL flag can be set in the CMD register before command processing
152 is complete, leading to spurious "failed to complete" errors. This has
153 the effect of promoting harmless CRC7 errors during CMD1 processing
154 into errors that can delay and even prevent booting.
155
156 Also:
157 1) Convert the last KERN_ERROR message in the register dumping to
158 KERN_INFO.
159 2) Remove an unnecessary reset call from bcm2835_sdhost_add_host.
160
161 See: https://github.com/raspberrypi/linux/pull/1492
162
163 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
164
165 bcm2835-sdhost: mmc_card_blockaddr fix
166
167 Get the definition of mmc_card_blockaddr from drivers/mmc/core/card.h.
168
169 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
170
171 bcm2835-sdhost: New timer API
172
173 mmc: bcm2835-sdhost: Support underclocking
174
175 Support underclocking of the SD bus in two ways:
176 1. using the max-frequency DT property (which currently has no DT
177 parameter), and
178 2. using the exiting sd_overclock parameter.
179
180 The two methods differ slightly - in the former the MMC subsystem is
181 aware of the underclocking, while in the latter it isn't - but the
182 end results should be the same.
183
184 See: https://github.com/raspberrypi/linux/issues/2350
185
186 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
187
188 mmc: bcm2835-sdhost: Add include
189
190 highmem.h (needed for kmap_atomic) is pulled in by one of the other
191 include files, but only with some CONFIG settings. Make the inclusion
192 explicit to cater for cases where the CONFIG setting is absent.
193
194 See: https://github.com/raspberrypi/linux/issues/2366
195
196 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
197 ---
198 drivers/mmc/host/Kconfig | 10 +
199 drivers/mmc/host/Makefile | 1 +
200 drivers/mmc/host/bcm2835-sdhost.c | 2191 +++++++++++++++++++++++++++++
201 3 files changed, 2202 insertions(+)
202 create mode 100644 drivers/mmc/host/bcm2835-sdhost.c
203
204 --- a/drivers/mmc/host/Kconfig
205 +++ b/drivers/mmc/host/Kconfig
206 @@ -33,6 +33,16 @@ config MMC_BCM2835_PIO_DMA_BARRIER
207
208 If unsure, say 2 here.
209
210 +config MMC_BCM2835_SDHOST
211 + tristate "Support for the SDHost controller on BCM2708/9"
212 + depends on ARCH_BCM2835
213 + help
214 + This selects the SDHost controller on BCM2835/6.
215 +
216 + If you have a controller with this interface, say Y or M here.
217 +
218 + If unsure, say N.
219 +
220 config MMC_DEBUG
221 bool "MMC host drivers debugging"
222 depends on MMC != n
223 --- a/drivers/mmc/host/Makefile
224 +++ b/drivers/mmc/host/Makefile
225 @@ -22,6 +22,7 @@ obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci
226 obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
227 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
228 obj-$(CONFIG_MMC_BCM2835_MMC) += bcm2835-mmc.o
229 +obj-$(CONFIG_MMC_BCM2835_SDHOST) += bcm2835-sdhost.o
230 obj-$(CONFIG_MMC_WBSD) += wbsd.o
231 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
232 obj-$(CONFIG_MMC_MTK) += mtk-sd.o
233 --- /dev/null
234 +++ b/drivers/mmc/host/bcm2835-sdhost.c
235 @@ -0,0 +1,2191 @@
236 +/*
237 + * BCM2835 SD host driver.
238 + *
239 + * Author: Phil Elwell <phil@raspberrypi.org>
240 + * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
241 + *
242 + * Based on
243 + * mmc-bcm2835.c by Gellert Weisz
244 + * which is, in turn, based on
245 + * sdhci-bcm2708.c by Broadcom
246 + * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
247 + * sdhci.c and sdhci-pci.c by Pierre Ossman
248 + *
249 + * This program is free software; you can redistribute it and/or modify it
250 + * under the terms and conditions of the GNU General Public License,
251 + * version 2, as published by the Free Software Foundation.
252 + *
253 + * This program is distributed in the hope it will be useful, but WITHOUT
254 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
255 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
256 + * more details.
257 + *
258 + * You should have received a copy of the GNU General Public License
259 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
260 + */
261 +
262 +#define FIFO_READ_THRESHOLD 4
263 +#define FIFO_WRITE_THRESHOLD 4
264 +#define ALLOW_CMD23_READ 1
265 +#define ALLOW_CMD23_WRITE 0
266 +#define ENABLE_LOG 1
267 +#define SDDATA_FIFO_PIO_BURST 8
268 +#define CMD_DALLY_US 1
269 +
270 +#include <linux/delay.h>
271 +#include <linux/module.h>
272 +#include <linux/io.h>
273 +#include <linux/mmc/mmc.h>
274 +#include <linux/mmc/host.h>
275 +#include <linux/mmc/sd.h>
276 +#include <linux/mmc/sdio.h>
277 +#include <linux/scatterlist.h>
278 +#include <linux/of_address.h>
279 +#include <linux/of_irq.h>
280 +#include <linux/clk.h>
281 +#include <linux/platform_device.h>
282 +#include <linux/err.h>
283 +#include <linux/blkdev.h>
284 +#include <linux/dmaengine.h>
285 +#include <linux/dma-mapping.h>
286 +#include <linux/of_dma.h>
287 +#include <linux/time.h>
288 +#include <linux/workqueue.h>
289 +#include <linux/interrupt.h>
290 +#include <linux/highmem.h>
291 +#include <soc/bcm2835/raspberrypi-firmware.h>
292 +
293 +/* For mmc_card_blockaddr */
294 +#include "../core/card.h"
295 +
296 +#define DRIVER_NAME "sdhost-bcm2835"
297 +
298 +#define SDCMD 0x00 /* Command to SD card - 16 R/W */
299 +#define SDARG 0x04 /* Argument to SD card - 32 R/W */
300 +#define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
301 +#define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
302 +#define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
303 +#define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
304 +#define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
305 +#define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
306 +#define SDHSTS 0x20 /* SD host status - 11 R */
307 +#define SDVDD 0x30 /* SD card power control - 1 R/W */
308 +#define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
309 +#define SDHCFG 0x38 /* Host configuration - 2 R/W */
310 +#define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
311 +#define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
312 +#define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
313 +
314 +#define SDCMD_NEW_FLAG 0x8000
315 +#define SDCMD_FAIL_FLAG 0x4000
316 +#define SDCMD_BUSYWAIT 0x800
317 +#define SDCMD_NO_RESPONSE 0x400
318 +#define SDCMD_LONG_RESPONSE 0x200
319 +#define SDCMD_WRITE_CMD 0x80
320 +#define SDCMD_READ_CMD 0x40
321 +#define SDCMD_CMD_MASK 0x3f
322 +
323 +#define SDCDIV_MAX_CDIV 0x7ff
324 +
325 +#define SDHSTS_BUSY_IRPT 0x400
326 +#define SDHSTS_BLOCK_IRPT 0x200
327 +#define SDHSTS_SDIO_IRPT 0x100
328 +#define SDHSTS_REW_TIME_OUT 0x80
329 +#define SDHSTS_CMD_TIME_OUT 0x40
330 +#define SDHSTS_CRC16_ERROR 0x20
331 +#define SDHSTS_CRC7_ERROR 0x10
332 +#define SDHSTS_FIFO_ERROR 0x08
333 +/* Reserved */
334 +/* Reserved */
335 +#define SDHSTS_DATA_FLAG 0x01
336 +
337 +#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR)
338 +#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK)
339 +
340 +#define SDHCFG_BUSY_IRPT_EN (1<<10)
341 +#define SDHCFG_BLOCK_IRPT_EN (1<<8)
342 +#define SDHCFG_SDIO_IRPT_EN (1<<5)
343 +#define SDHCFG_DATA_IRPT_EN (1<<4)
344 +#define SDHCFG_SLOW_CARD (1<<3)
345 +#define SDHCFG_WIDE_EXT_BUS (1<<2)
346 +#define SDHCFG_WIDE_INT_BUS (1<<1)
347 +#define SDHCFG_REL_CMD_LINE (1<<0)
348 +
349 +#define SDEDM_FORCE_DATA_MODE (1<<19)
350 +#define SDEDM_CLOCK_PULSE (1<<20)
351 +#define SDEDM_BYPASS (1<<21)
352 +
353 +#define SDEDM_WRITE_THRESHOLD_SHIFT 9
354 +#define SDEDM_READ_THRESHOLD_SHIFT 14
355 +#define SDEDM_THRESHOLD_MASK 0x1f
356 +
357 +#define SDEDM_FSM_MASK 0xf
358 +#define SDEDM_FSM_IDENTMODE 0x0
359 +#define SDEDM_FSM_DATAMODE 0x1
360 +#define SDEDM_FSM_READDATA 0x2
361 +#define SDEDM_FSM_WRITEDATA 0x3
362 +#define SDEDM_FSM_READWAIT 0x4
363 +#define SDEDM_FSM_READCRC 0x5
364 +#define SDEDM_FSM_WRITECRC 0x6
365 +#define SDEDM_FSM_WRITEWAIT1 0x7
366 +#define SDEDM_FSM_POWERDOWN 0x8
367 +#define SDEDM_FSM_POWERUP 0x9
368 +#define SDEDM_FSM_WRITESTART1 0xa
369 +#define SDEDM_FSM_WRITESTART2 0xb
370 +#define SDEDM_FSM_GENPULSES 0xc
371 +#define SDEDM_FSM_WRITEWAIT2 0xd
372 +#define SDEDM_FSM_STARTPOWDOWN 0xf
373 +
374 +#define SDDATA_FIFO_WORDS 16
375 +
376 +#define USE_CMD23_FLAGS ((ALLOW_CMD23_READ * MMC_DATA_READ) | \
377 + (ALLOW_CMD23_WRITE * MMC_DATA_WRITE))
378 +
379 +#define MHZ 1000000
380 +
381 +
382 +struct bcm2835_host {
383 + spinlock_t lock;
384 +
385 + void __iomem *ioaddr;
386 + u32 bus_addr;
387 +
388 + struct mmc_host *mmc;
389 +
390 + u32 pio_timeout; /* In jiffies */
391 +
392 + int clock; /* Current clock speed */
393 +
394 + bool slow_card; /* Force 11-bit divisor */
395 +
396 + unsigned int max_clk; /* Max possible freq */
397 +
398 + struct tasklet_struct finish_tasklet; /* Tasklet structures */
399 +
400 + struct work_struct cmd_wait_wq; /* Workqueue function */
401 +
402 + struct timer_list timer; /* Timer for timeouts */
403 +
404 + struct sg_mapping_iter sg_miter; /* SG state for PIO */
405 + unsigned int blocks; /* remaining PIO blocks */
406 +
407 + int irq; /* Device IRQ */
408 +
409 + u32 cmd_quick_poll_retries;
410 + u32 ns_per_fifo_word;
411 +
412 + /* cached registers */
413 + u32 hcfg;
414 + u32 cdiv;
415 +
416 + struct mmc_request *mrq; /* Current request */
417 + struct mmc_command *cmd; /* Current command */
418 + struct mmc_data *data; /* Current data request */
419 + unsigned int data_complete:1; /* Data finished before cmd */
420 +
421 + unsigned int flush_fifo:1; /* Drain the fifo when finishing */
422 +
423 + unsigned int use_busy:1; /* Wait for busy interrupt */
424 +
425 + unsigned int use_sbc:1; /* Send CMD23 */
426 +
427 + unsigned int debug:1; /* Enable debug output */
428 + unsigned int firmware_sets_cdiv:1; /* Let the firmware manage the clock */
429 + unsigned int reset_clock:1; /* Reset the clock fore the next request */
430 +
431 + /*DMA part*/
432 + struct dma_chan *dma_chan_rxtx; /* DMA channel for reads and writes */
433 + struct dma_chan *dma_chan; /* Channel in use */
434 + struct dma_slave_config dma_cfg_rx;
435 + struct dma_slave_config dma_cfg_tx;
436 + struct dma_async_tx_descriptor *dma_desc;
437 + u32 dma_dir;
438 + u32 drain_words;
439 + struct page *drain_page;
440 + u32 drain_offset;
441 +
442 + bool allow_dma;
443 + bool use_dma;
444 + /*end of DMA part*/
445 +
446 + int max_delay; /* maximum length of time spent waiting */
447 + struct timeval stop_time; /* when the last stop was issued */
448 + u32 delay_after_stop; /* minimum time between stop and subsequent data transfer */
449 + u32 delay_after_this_stop; /* minimum time between this stop and subsequent data transfer */
450 + u32 user_overclock_50; /* User's preferred frequency to use when 50MHz is requested (in MHz) */
451 + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
452 + u32 overclock; /* Current frequency if overclocked, else zero */
453 + u32 pio_limit; /* Maximum block count for PIO (0 = always DMA) */
454 +
455 + u32 sectors; /* Cached card size in sectors */
456 +};
457 +
458 +#if ENABLE_LOG
459 +
460 +struct log_entry_struct {
461 + char event[4];
462 + u32 timestamp;
463 + u32 param1;
464 + u32 param2;
465 +};
466 +
467 +typedef struct log_entry_struct LOG_ENTRY_T;
468 +
469 +LOG_ENTRY_T *sdhost_log_buf;
470 +dma_addr_t sdhost_log_addr;
471 +static u32 sdhost_log_idx;
472 +static spinlock_t log_lock;
473 +static void __iomem *timer_base;
474 +
475 +#define LOG_ENTRIES (256*1)
476 +#define LOG_SIZE (sizeof(LOG_ENTRY_T)*LOG_ENTRIES)
477 +
478 +static void log_init(struct device *dev, u32 bus_to_phys)
479 +{
480 + spin_lock_init(&log_lock);
481 + sdhost_log_buf = dma_zalloc_coherent(dev, LOG_SIZE, &sdhost_log_addr,
482 + GFP_KERNEL);
483 + if (sdhost_log_buf) {
484 + pr_info("sdhost: log_buf @ %p (%x)\n",
485 + sdhost_log_buf, sdhost_log_addr);
486 + timer_base = ioremap_nocache(bus_to_phys + 0x7e003000, SZ_4K);
487 + if (!timer_base)
488 + pr_err("sdhost: failed to remap timer\n");
489 + }
490 + else
491 + pr_err("sdhost: failed to allocate log buf\n");
492 +}
493 +
494 +static void log_event_impl(const char *event, u32 param1, u32 param2)
495 +{
496 + if (sdhost_log_buf) {
497 + LOG_ENTRY_T *entry;
498 + unsigned long flags;
499 +
500 + spin_lock_irqsave(&log_lock, flags);
501 +
502 + entry = sdhost_log_buf + sdhost_log_idx;
503 + memcpy(entry->event, event, 4);
504 + entry->timestamp = (readl(timer_base + 4) & 0x3fffffff) +
505 + (smp_processor_id()<<30);
506 + entry->param1 = param1;
507 + entry->param2 = param2;
508 + sdhost_log_idx = (sdhost_log_idx + 1) % LOG_ENTRIES;
509 +
510 + spin_unlock_irqrestore(&log_lock, flags);
511 + }
512 +}
513 +
514 +static void log_dump(void)
515 +{
516 + if (sdhost_log_buf) {
517 + LOG_ENTRY_T *entry;
518 + unsigned long flags;
519 + int idx;
520 +
521 + spin_lock_irqsave(&log_lock, flags);
522 +
523 + idx = sdhost_log_idx;
524 + do {
525 + entry = sdhost_log_buf + idx;
526 + if (entry->event[0] != '\0')
527 + pr_info("[%08x] %.4s %x %x\n",
528 + entry->timestamp,
529 + entry->event,
530 + entry->param1,
531 + entry->param2);
532 + idx = (idx + 1) % LOG_ENTRIES;
533 + } while (idx != sdhost_log_idx);
534 +
535 + spin_unlock_irqrestore(&log_lock, flags);
536 + }
537 +}
538 +
539 +#define log_event(event, param1, param2) log_event_impl(event, param1, param2)
540 +
541 +#else
542 +
543 +#define log_init(x) (void)0
544 +#define log_event(event, param1, param2) (void)0
545 +#define log_dump() (void)0
546 +
547 +#endif
548 +
549 +static inline void bcm2835_sdhost_write(struct bcm2835_host *host, u32 val, int reg)
550 +{
551 + writel(val, host->ioaddr + reg);
552 +}
553 +
554 +static inline u32 bcm2835_sdhost_read(struct bcm2835_host *host, int reg)
555 +{
556 + return readl(host->ioaddr + reg);
557 +}
558 +
559 +static inline u32 bcm2835_sdhost_read_relaxed(struct bcm2835_host *host, int reg)
560 +{
561 + return readl_relaxed(host->ioaddr + reg);
562 +}
563 +
564 +static void bcm2835_sdhost_dumpcmd(struct bcm2835_host *host,
565 + struct mmc_command *cmd,
566 + const char *label)
567 +{
568 + if (cmd)
569 + pr_info("%s:%c%s op %d arg 0x%x flags 0x%x - resp %08x %08x %08x %08x, err %d\n",
570 + mmc_hostname(host->mmc),
571 + (cmd == host->cmd) ? '>' : ' ',
572 + label, cmd->opcode, cmd->arg, cmd->flags,
573 + cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3],
574 + cmd->error);
575 +}
576 +
577 +static void bcm2835_sdhost_dumpregs(struct bcm2835_host *host)
578 +{
579 + if (host->mrq)
580 + {
581 + bcm2835_sdhost_dumpcmd(host, host->mrq->sbc, "sbc");
582 + bcm2835_sdhost_dumpcmd(host, host->mrq->cmd, "cmd");
583 + if (host->mrq->data)
584 + pr_info("%s: data blocks %x blksz %x - err %d\n",
585 + mmc_hostname(host->mmc),
586 + host->mrq->data->blocks,
587 + host->mrq->data->blksz,
588 + host->mrq->data->error);
589 + bcm2835_sdhost_dumpcmd(host, host->mrq->stop, "stop");
590 + }
591 +
592 + pr_info("%s: =========== REGISTER DUMP ===========\n",
593 + mmc_hostname(host->mmc));
594 +
595 + pr_info("%s: SDCMD 0x%08x\n",
596 + mmc_hostname(host->mmc),
597 + bcm2835_sdhost_read(host, SDCMD));
598 + pr_info("%s: SDARG 0x%08x\n",
599 + mmc_hostname(host->mmc),
600 + bcm2835_sdhost_read(host, SDARG));
601 + pr_info("%s: SDTOUT 0x%08x\n",
602 + mmc_hostname(host->mmc),
603 + bcm2835_sdhost_read(host, SDTOUT));
604 + pr_info("%s: SDCDIV 0x%08x\n",
605 + mmc_hostname(host->mmc),
606 + bcm2835_sdhost_read(host, SDCDIV));
607 + pr_info("%s: SDRSP0 0x%08x\n",
608 + mmc_hostname(host->mmc),
609 + bcm2835_sdhost_read(host, SDRSP0));
610 + pr_info("%s: SDRSP1 0x%08x\n",
611 + mmc_hostname(host->mmc),
612 + bcm2835_sdhost_read(host, SDRSP1));
613 + pr_info("%s: SDRSP2 0x%08x\n",
614 + mmc_hostname(host->mmc),
615 + bcm2835_sdhost_read(host, SDRSP2));
616 + pr_info("%s: SDRSP3 0x%08x\n",
617 + mmc_hostname(host->mmc),
618 + bcm2835_sdhost_read(host, SDRSP3));
619 + pr_info("%s: SDHSTS 0x%08x\n",
620 + mmc_hostname(host->mmc),
621 + bcm2835_sdhost_read(host, SDHSTS));
622 + pr_info("%s: SDVDD 0x%08x\n",
623 + mmc_hostname(host->mmc),
624 + bcm2835_sdhost_read(host, SDVDD));
625 + pr_info("%s: SDEDM 0x%08x\n",
626 + mmc_hostname(host->mmc),
627 + bcm2835_sdhost_read(host, SDEDM));
628 + pr_info("%s: SDHCFG 0x%08x\n",
629 + mmc_hostname(host->mmc),
630 + bcm2835_sdhost_read(host, SDHCFG));
631 + pr_info("%s: SDHBCT 0x%08x\n",
632 + mmc_hostname(host->mmc),
633 + bcm2835_sdhost_read(host, SDHBCT));
634 + pr_info("%s: SDHBLC 0x%08x\n",
635 + mmc_hostname(host->mmc),
636 + bcm2835_sdhost_read(host, SDHBLC));
637 +
638 + pr_info("%s: ===========================================\n",
639 + mmc_hostname(host->mmc));
640 +}
641 +
642 +static void bcm2835_sdhost_set_power(struct bcm2835_host *host, bool on)
643 +{
644 + bcm2835_sdhost_write(host, on ? 1 : 0, SDVDD);
645 +}
646 +
647 +static void bcm2835_sdhost_reset_internal(struct bcm2835_host *host)
648 +{
649 + u32 temp;
650 +
651 + if (host->debug)
652 + pr_info("%s: reset\n", mmc_hostname(host->mmc));
653 +
654 + bcm2835_sdhost_set_power(host, false);
655 +
656 + bcm2835_sdhost_write(host, 0, SDCMD);
657 + bcm2835_sdhost_write(host, 0, SDARG);
658 + bcm2835_sdhost_write(host, 0xf00000, SDTOUT);
659 + bcm2835_sdhost_write(host, 0, SDCDIV);
660 + bcm2835_sdhost_write(host, 0x7f8, SDHSTS); /* Write 1s to clear */
661 + bcm2835_sdhost_write(host, 0, SDHCFG);
662 + bcm2835_sdhost_write(host, 0, SDHBCT);
663 + bcm2835_sdhost_write(host, 0, SDHBLC);
664 +
665 + /* Limit fifo usage due to silicon bug */
666 + temp = bcm2835_sdhost_read(host, SDEDM);
667 + temp &= ~((SDEDM_THRESHOLD_MASK<<SDEDM_READ_THRESHOLD_SHIFT) |
668 + (SDEDM_THRESHOLD_MASK<<SDEDM_WRITE_THRESHOLD_SHIFT));
669 + temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
670 + (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
671 + bcm2835_sdhost_write(host, temp, SDEDM);
672 + mdelay(10);
673 + bcm2835_sdhost_set_power(host, true);
674 + mdelay(10);
675 + host->clock = 0;
676 + host->sectors = 0;
677 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
678 + bcm2835_sdhost_write(host, SDCDIV_MAX_CDIV, SDCDIV);
679 + mmiowb();
680 +}
681 +
682 +static void bcm2835_sdhost_reset(struct mmc_host *mmc)
683 +{
684 + struct bcm2835_host *host = mmc_priv(mmc);
685 + unsigned long flags;
686 + spin_lock_irqsave(&host->lock, flags);
687 + log_event("RST<", 0, 0);
688 +
689 + bcm2835_sdhost_reset_internal(host);
690 +
691 + spin_unlock_irqrestore(&host->lock, flags);
692 +}
693 +
694 +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
695 +
696 +static void bcm2835_sdhost_init(struct bcm2835_host *host, int soft)
697 +{
698 + pr_debug("bcm2835_sdhost_init(%d)\n", soft);
699 +
700 + /* Set interrupt enables */
701 + host->hcfg = SDHCFG_BUSY_IRPT_EN;
702 +
703 + bcm2835_sdhost_reset_internal(host);
704 +
705 + if (soft) {
706 + /* force clock reconfiguration */
707 + host->clock = 0;
708 + bcm2835_sdhost_set_ios(host->mmc, &host->mmc->ios);
709 + }
710 +}
711 +
712 +static void bcm2835_sdhost_wait_transfer_complete(struct bcm2835_host *host)
713 +{
714 + int timediff;
715 + u32 alternate_idle;
716 + u32 edm;
717 +
718 + alternate_idle = (host->mrq->data->flags & MMC_DATA_READ) ?
719 + SDEDM_FSM_READWAIT : SDEDM_FSM_WRITESTART1;
720 +
721 + edm = bcm2835_sdhost_read(host, SDEDM);
722 +
723 + log_event("WTC<", edm, 0);
724 +
725 + timediff = 0;
726 +
727 + while (1) {
728 + u32 fsm = edm & SDEDM_FSM_MASK;
729 + if ((fsm == SDEDM_FSM_IDENTMODE) ||
730 + (fsm == SDEDM_FSM_DATAMODE))
731 + break;
732 + if (fsm == alternate_idle) {
733 + bcm2835_sdhost_write(host,
734 + edm | SDEDM_FORCE_DATA_MODE,
735 + SDEDM);
736 + break;
737 + }
738 +
739 + timediff++;
740 + if (timediff == 100000) {
741 + pr_err("%s: wait_transfer_complete - still waiting after %d retries\n",
742 + mmc_hostname(host->mmc),
743 + timediff);
744 + log_dump();
745 + bcm2835_sdhost_dumpregs(host);
746 + host->mrq->data->error = -ETIMEDOUT;
747 + log_event("WTC!", edm, 0);
748 + return;
749 + }
750 + cpu_relax();
751 + edm = bcm2835_sdhost_read(host, SDEDM);
752 + }
753 + log_event("WTC>", edm, 0);
754 +}
755 +
756 +static void bcm2835_sdhost_finish_data(struct bcm2835_host *host);
757 +
758 +static void bcm2835_sdhost_dma_complete(void *param)
759 +{
760 + struct bcm2835_host *host = param;
761 + struct mmc_data *data = host->data;
762 + unsigned long flags;
763 +
764 + spin_lock_irqsave(&host->lock, flags);
765 + log_event("DMA<", (u32)host->data, bcm2835_sdhost_read(host, SDHSTS));
766 + log_event("DMA ", bcm2835_sdhost_read(host, SDCMD),
767 + bcm2835_sdhost_read(host, SDEDM));
768 +
769 + if (host->dma_chan) {
770 + dma_unmap_sg(host->dma_chan->device->dev,
771 + data->sg, data->sg_len,
772 + host->dma_dir);
773 +
774 + host->dma_chan = NULL;
775 + }
776 +
777 + if (host->drain_words) {
778 + void *page;
779 + u32 *buf;
780 +
781 + page = kmap_atomic(host->drain_page);
782 + buf = page + host->drain_offset;
783 +
784 + while (host->drain_words) {
785 + u32 edm = bcm2835_sdhost_read(host, SDEDM);
786 + if ((edm >> 4) & 0x1f)
787 + *(buf++) = bcm2835_sdhost_read(host,
788 + SDDATA);
789 + host->drain_words--;
790 + }
791 +
792 + kunmap_atomic(page);
793 + }
794 +
795 + bcm2835_sdhost_finish_data(host);
796 +
797 + log_event("DMA>", (u32)host->data, 0);
798 + spin_unlock_irqrestore(&host->lock, flags);
799 +}
800 +
801 +static void bcm2835_sdhost_read_block_pio(struct bcm2835_host *host)
802 +{
803 + unsigned long flags;
804 + size_t blksize, len;
805 + u32 *buf;
806 + unsigned long wait_max;
807 +
808 + blksize = host->data->blksz;
809 +
810 + wait_max = jiffies + msecs_to_jiffies(host->pio_timeout);
811 +
812 + local_irq_save(flags);
813 +
814 + while (blksize) {
815 + int copy_words;
816 + u32 hsts = 0;
817 +
818 + if (!sg_miter_next(&host->sg_miter)) {
819 + host->data->error = -EINVAL;
820 + break;
821 + }
822 +
823 + len = min(host->sg_miter.length, blksize);
824 + if (len % 4) {
825 + host->data->error = -EINVAL;
826 + break;
827 + }
828 +
829 + blksize -= len;
830 + host->sg_miter.consumed = len;
831 +
832 + buf = (u32 *)host->sg_miter.addr;
833 +
834 + copy_words = len/4;
835 +
836 + while (copy_words) {
837 + int burst_words, words;
838 + u32 edm;
839 +
840 + burst_words = SDDATA_FIFO_PIO_BURST;
841 + if (burst_words > copy_words)
842 + burst_words = copy_words;
843 + edm = bcm2835_sdhost_read(host, SDEDM);
844 + words = ((edm >> 4) & 0x1f);
845 +
846 + if (words < burst_words) {
847 + int fsm_state = (edm & SDEDM_FSM_MASK);
848 + if ((fsm_state != SDEDM_FSM_READDATA) &&
849 + (fsm_state != SDEDM_FSM_READWAIT) &&
850 + (fsm_state != SDEDM_FSM_READCRC)) {
851 + hsts = bcm2835_sdhost_read(host,
852 + SDHSTS);
853 + pr_info("%s: fsm %x, hsts %x\n",
854 + mmc_hostname(host->mmc),
855 + fsm_state, hsts);
856 + if (hsts & SDHSTS_ERROR_MASK)
857 + break;
858 + }
859 +
860 + if (time_after(jiffies, wait_max)) {
861 + pr_err("%s: PIO read timeout - EDM %x\n",
862 + mmc_hostname(host->mmc),
863 + edm);
864 + hsts = SDHSTS_REW_TIME_OUT;
865 + break;
866 + }
867 + ndelay((burst_words - words) *
868 + host->ns_per_fifo_word);
869 + continue;
870 + } else if (words > copy_words) {
871 + words = copy_words;
872 + }
873 +
874 + copy_words -= words;
875 +
876 + while (words) {
877 + *(buf++) = bcm2835_sdhost_read(host, SDDATA);
878 + words--;
879 + }
880 + }
881 +
882 + if (hsts & SDHSTS_ERROR_MASK)
883 + break;
884 + }
885 +
886 + sg_miter_stop(&host->sg_miter);
887 +
888 + local_irq_restore(flags);
889 +}
890 +
891 +static void bcm2835_sdhost_write_block_pio(struct bcm2835_host *host)
892 +{
893 + unsigned long flags;
894 + size_t blksize, len;
895 + u32 *buf;
896 + unsigned long wait_max;
897 +
898 + blksize = host->data->blksz;
899 +
900 + wait_max = jiffies + msecs_to_jiffies(host->pio_timeout);
901 +
902 + local_irq_save(flags);
903 +
904 + while (blksize) {
905 + int copy_words;
906 + u32 hsts = 0;
907 +
908 + if (!sg_miter_next(&host->sg_miter)) {
909 + host->data->error = -EINVAL;
910 + break;
911 + }
912 +
913 + len = min(host->sg_miter.length, blksize);
914 + if (len % 4) {
915 + host->data->error = -EINVAL;
916 + break;
917 + }
918 +
919 + blksize -= len;
920 + host->sg_miter.consumed = len;
921 +
922 + buf = (u32 *)host->sg_miter.addr;
923 +
924 + copy_words = len/4;
925 +
926 + while (copy_words) {
927 + int burst_words, words;
928 + u32 edm;
929 +
930 + burst_words = SDDATA_FIFO_PIO_BURST;
931 + if (burst_words > copy_words)
932 + burst_words = copy_words;
933 + edm = bcm2835_sdhost_read(host, SDEDM);
934 + words = SDDATA_FIFO_WORDS - ((edm >> 4) & 0x1f);
935 +
936 + if (words < burst_words) {
937 + int fsm_state = (edm & SDEDM_FSM_MASK);
938 + if ((fsm_state != SDEDM_FSM_WRITEDATA) &&
939 + (fsm_state != SDEDM_FSM_WRITESTART1) &&
940 + (fsm_state != SDEDM_FSM_WRITESTART2)) {
941 + hsts = bcm2835_sdhost_read(host,
942 + SDHSTS);
943 + pr_info("%s: fsm %x, hsts %x\n",
944 + mmc_hostname(host->mmc),
945 + fsm_state, hsts);
946 + if (hsts & SDHSTS_ERROR_MASK)
947 + break;
948 + }
949 +
950 + if (time_after(jiffies, wait_max)) {
951 + pr_err("%s: PIO write timeout - EDM %x\n",
952 + mmc_hostname(host->mmc),
953 + edm);
954 + hsts = SDHSTS_REW_TIME_OUT;
955 + break;
956 + }
957 + ndelay((burst_words - words) *
958 + host->ns_per_fifo_word);
959 + continue;
960 + } else if (words > copy_words) {
961 + words = copy_words;
962 + }
963 +
964 + copy_words -= words;
965 +
966 + while (words) {
967 + bcm2835_sdhost_write(host, *(buf++), SDDATA);
968 + words--;
969 + }
970 + }
971 +
972 + if (hsts & SDHSTS_ERROR_MASK)
973 + break;
974 + }
975 +
976 + sg_miter_stop(&host->sg_miter);
977 +
978 + local_irq_restore(flags);
979 +}
980 +
981 +static void bcm2835_sdhost_transfer_pio(struct bcm2835_host *host)
982 +{
983 + u32 sdhsts;
984 + bool is_read;
985 + BUG_ON(!host->data);
986 + log_event("XFP<", (u32)host->data, host->blocks);
987 +
988 + is_read = (host->data->flags & MMC_DATA_READ) != 0;
989 + if (is_read)
990 + bcm2835_sdhost_read_block_pio(host);
991 + else
992 + bcm2835_sdhost_write_block_pio(host);
993 +
994 + sdhsts = bcm2835_sdhost_read(host, SDHSTS);
995 + if (sdhsts & (SDHSTS_CRC16_ERROR |
996 + SDHSTS_CRC7_ERROR |
997 + SDHSTS_FIFO_ERROR)) {
998 + pr_err("%s: %s transfer error - HSTS %x\n",
999 + mmc_hostname(host->mmc),
1000 + is_read ? "read" : "write",
1001 + sdhsts);
1002 + host->data->error = -EILSEQ;
1003 + } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
1004 + SDHSTS_REW_TIME_OUT))) {
1005 + pr_err("%s: %s timeout error - HSTS %x\n",
1006 + mmc_hostname(host->mmc),
1007 + is_read ? "read" : "write",
1008 + sdhsts);
1009 + host->data->error = -ETIMEDOUT;
1010 + }
1011 + log_event("XFP>", (u32)host->data, host->blocks);
1012 +}
1013 +
1014 +static void bcm2835_sdhost_prepare_dma(struct bcm2835_host *host,
1015 + struct mmc_data *data)
1016 +{
1017 + int len, dir_data, dir_slave;
1018 + struct dma_async_tx_descriptor *desc = NULL;
1019 + struct dma_chan *dma_chan;
1020 +
1021 + log_event("PRD<", (u32)data, 0);
1022 + pr_debug("bcm2835_sdhost_prepare_dma()\n");
1023 +
1024 + dma_chan = host->dma_chan_rxtx;
1025 + if (data->flags & MMC_DATA_READ) {
1026 + dir_data = DMA_FROM_DEVICE;
1027 + dir_slave = DMA_DEV_TO_MEM;
1028 + } else {
1029 + dir_data = DMA_TO_DEVICE;
1030 + dir_slave = DMA_MEM_TO_DEV;
1031 + }
1032 + log_event("PRD1", (u32)dma_chan, 0);
1033 +
1034 + BUG_ON(!dma_chan->device);
1035 + BUG_ON(!dma_chan->device->dev);
1036 + BUG_ON(!data->sg);
1037 +
1038 + /* The block doesn't manage the FIFO DREQs properly for multi-block
1039 + transfers, so don't attempt to DMA the final few words.
1040 + Unfortunately this requires the final sg entry to be trimmed.
1041 + N.B. This code demands that the overspill is contained in
1042 + a single sg entry.
1043 + */
1044 +
1045 + host->drain_words = 0;
1046 + if ((data->blocks > 1) && (dir_data == DMA_FROM_DEVICE)) {
1047 + struct scatterlist *sg;
1048 + u32 len;
1049 + int i;
1050 +
1051 + len = min((u32)(FIFO_READ_THRESHOLD - 1) * 4,
1052 + (u32)data->blocks * data->blksz);
1053 +
1054 + for_each_sg(data->sg, sg, data->sg_len, i) {
1055 + if (sg_is_last(sg)) {
1056 + BUG_ON(sg->length < len);
1057 + sg->length -= len;
1058 + host->drain_page = sg_page(sg);
1059 + host->drain_offset = sg->offset + sg->length;
1060 + }
1061 + }
1062 + host->drain_words = len/4;
1063 + }
1064 +
1065 + /* The parameters have already been validated, so this will not fail */
1066 + (void)dmaengine_slave_config(dma_chan,
1067 + (dir_data == DMA_FROM_DEVICE) ?
1068 + &host->dma_cfg_rx :
1069 + &host->dma_cfg_tx);
1070 +
1071 + len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
1072 + dir_data);
1073 +
1074 + log_event("PRD2", len, 0);
1075 + if (len > 0)
1076 + desc = dmaengine_prep_slave_sg(dma_chan, data->sg,
1077 + len, dir_slave,
1078 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1079 + log_event("PRD3", (u32)desc, 0);
1080 +
1081 + if (desc) {
1082 + desc->callback = bcm2835_sdhost_dma_complete;
1083 + desc->callback_param = host;
1084 + host->dma_desc = desc;
1085 + host->dma_chan = dma_chan;
1086 + host->dma_dir = dir_data;
1087 + }
1088 + log_event("PDM>", (u32)data, 0);
1089 +}
1090 +
1091 +static void bcm2835_sdhost_start_dma(struct bcm2835_host *host)
1092 +{
1093 + log_event("SDMA", (u32)host->data, (u32)host->dma_chan);
1094 + dmaengine_submit(host->dma_desc);
1095 + dma_async_issue_pending(host->dma_chan);
1096 +}
1097 +
1098 +static void bcm2835_sdhost_set_transfer_irqs(struct bcm2835_host *host)
1099 +{
1100 + u32 all_irqs = SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN |
1101 + SDHCFG_BUSY_IRPT_EN;
1102 + if (host->dma_desc)
1103 + host->hcfg = (host->hcfg & ~all_irqs) |
1104 + SDHCFG_BUSY_IRPT_EN;
1105 + else
1106 + host->hcfg = (host->hcfg & ~all_irqs) |
1107 + SDHCFG_DATA_IRPT_EN |
1108 + SDHCFG_BUSY_IRPT_EN;
1109 +
1110 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1111 +}
1112 +
1113 +static void bcm2835_sdhost_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
1114 +{
1115 + struct mmc_data *data = cmd->data;
1116 +
1117 + WARN_ON(host->data);
1118 +
1119 + host->data = data;
1120 + if (!data)
1121 + return;
1122 +
1123 + /* Sanity checks */
1124 + BUG_ON(data->blksz * data->blocks > 524288);
1125 + BUG_ON(data->blksz > host->mmc->max_blk_size);
1126 + BUG_ON(data->blocks > 65535);
1127 +
1128 + host->data_complete = 0;
1129 + host->flush_fifo = 0;
1130 + host->data->bytes_xfered = 0;
1131 +
1132 + if (!host->sectors && host->mmc->card) {
1133 + struct mmc_card *card = host->mmc->card;
1134 + if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
1135 + /*
1136 + * The EXT_CSD sector count is in number of 512 byte
1137 + * sectors.
1138 + */
1139 + host->sectors = card->ext_csd.sectors;
1140 + } else {
1141 + /*
1142 + * The CSD capacity field is in units of read_blkbits.
1143 + * set_capacity takes units of 512 bytes.
1144 + */
1145 + host->sectors = card->csd.capacity <<
1146 + (card->csd.read_blkbits - 9);
1147 + }
1148 + }
1149 +
1150 + if (!host->dma_desc) {
1151 + /* Use PIO */
1152 + int flags = SG_MITER_ATOMIC;
1153 +
1154 + if (data->flags & MMC_DATA_READ)
1155 + flags |= SG_MITER_TO_SG;
1156 + else
1157 + flags |= SG_MITER_FROM_SG;
1158 + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1159 + host->blocks = data->blocks;
1160 + }
1161 +
1162 + bcm2835_sdhost_set_transfer_irqs(host);
1163 +
1164 + bcm2835_sdhost_write(host, data->blksz, SDHBCT);
1165 + bcm2835_sdhost_write(host, data->blocks, SDHBLC);
1166 +
1167 + BUG_ON(!host->data);
1168 +}
1169 +
1170 +bool bcm2835_sdhost_send_command(struct bcm2835_host *host,
1171 + struct mmc_command *cmd)
1172 +{
1173 + u32 sdcmd, sdhsts;
1174 + unsigned long timeout;
1175 + int delay;
1176 +
1177 + WARN_ON(host->cmd);
1178 + log_event("CMD<", cmd->opcode, cmd->arg);
1179 +
1180 + if (cmd->data)
1181 + pr_debug("%s: send_command %d 0x%x "
1182 + "(flags 0x%x) - %s %d*%d\n",
1183 + mmc_hostname(host->mmc),
1184 + cmd->opcode, cmd->arg, cmd->flags,
1185 + (cmd->data->flags & MMC_DATA_READ) ?
1186 + "read" : "write", cmd->data->blocks,
1187 + cmd->data->blksz);
1188 + else
1189 + pr_debug("%s: send_command %d 0x%x (flags 0x%x)\n",
1190 + mmc_hostname(host->mmc),
1191 + cmd->opcode, cmd->arg, cmd->flags);
1192 +
1193 + /* Wait max 100 ms */
1194 + timeout = 10000;
1195 +
1196 + while (bcm2835_sdhost_read(host, SDCMD) & SDCMD_NEW_FLAG) {
1197 + if (timeout == 0) {
1198 + pr_warn("%s: previous command never completed.\n",
1199 + mmc_hostname(host->mmc));
1200 + if (host->debug)
1201 + bcm2835_sdhost_dumpregs(host);
1202 + cmd->error = -EILSEQ;
1203 + tasklet_schedule(&host->finish_tasklet);
1204 + return false;
1205 + }
1206 + timeout--;
1207 + udelay(10);
1208 + }
1209 +
1210 + delay = (10000 - timeout)/100;
1211 + if (delay > host->max_delay) {
1212 + host->max_delay = delay;
1213 + pr_warning("%s: controller hung for %d ms\n",
1214 + mmc_hostname(host->mmc),
1215 + host->max_delay);
1216 + }
1217 +
1218 + timeout = jiffies;
1219 + if (!cmd->data && cmd->busy_timeout > 9000)
1220 + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1221 + else
1222 + timeout += 10 * HZ;
1223 + mod_timer(&host->timer, timeout);
1224 +
1225 + host->cmd = cmd;
1226 +
1227 + /* Clear any error flags */
1228 + sdhsts = bcm2835_sdhost_read(host, SDHSTS);
1229 + if (sdhsts & SDHSTS_ERROR_MASK)
1230 + bcm2835_sdhost_write(host, sdhsts, SDHSTS);
1231 +
1232 + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1233 + pr_err("%s: unsupported response type!\n",
1234 + mmc_hostname(host->mmc));
1235 + cmd->error = -EINVAL;
1236 + tasklet_schedule(&host->finish_tasklet);
1237 + return false;
1238 + }
1239 +
1240 + bcm2835_sdhost_prepare_data(host, cmd);
1241 +
1242 + bcm2835_sdhost_write(host, cmd->arg, SDARG);
1243 +
1244 + sdcmd = cmd->opcode & SDCMD_CMD_MASK;
1245 +
1246 + host->use_busy = 0;
1247 + if (!(cmd->flags & MMC_RSP_PRESENT)) {
1248 + sdcmd |= SDCMD_NO_RESPONSE;
1249 + } else {
1250 + if (cmd->flags & MMC_RSP_136)
1251 + sdcmd |= SDCMD_LONG_RESPONSE;
1252 + if (cmd->flags & MMC_RSP_BUSY) {
1253 + sdcmd |= SDCMD_BUSYWAIT;
1254 + host->use_busy = 1;
1255 + }
1256 + }
1257 +
1258 + if (cmd->data) {
1259 + log_event("CMDD", cmd->data->blocks, cmd->data->blksz);
1260 + if (host->delay_after_this_stop) {
1261 + struct timeval now;
1262 + int time_since_stop;
1263 + do_gettimeofday(&now);
1264 + time_since_stop = (now.tv_sec - host->stop_time.tv_sec);
1265 + if (time_since_stop < 2) {
1266 + /* Possibly less than one second */
1267 + time_since_stop = time_since_stop * 1000000 +
1268 + (now.tv_usec - host->stop_time.tv_usec);
1269 + if (time_since_stop <
1270 + host->delay_after_this_stop)
1271 + udelay(host->delay_after_this_stop -
1272 + time_since_stop);
1273 + }
1274 + }
1275 +
1276 + host->delay_after_this_stop = host->delay_after_stop;
1277 + if ((cmd->data->flags & MMC_DATA_READ) && !host->use_sbc) {
1278 + /* See if read crosses one of the hazardous sectors */
1279 + u32 first_blk, last_blk;
1280 +
1281 + /* Intentionally include the following sector because
1282 + without CMD23/SBC the read may run on. */
1283 + first_blk = host->mrq->cmd->arg;
1284 + last_blk = first_blk + cmd->data->blocks;
1285 +
1286 + if (((last_blk >= (host->sectors - 64)) &&
1287 + (first_blk <= (host->sectors - 64))) ||
1288 + ((last_blk >= (host->sectors - 32)) &&
1289 + (first_blk <= (host->sectors - 32)))) {
1290 + host->delay_after_this_stop =
1291 + max(250u, host->delay_after_stop);
1292 + }
1293 + }
1294 +
1295 + if (cmd->data->flags & MMC_DATA_WRITE)
1296 + sdcmd |= SDCMD_WRITE_CMD;
1297 + if (cmd->data->flags & MMC_DATA_READ)
1298 + sdcmd |= SDCMD_READ_CMD;
1299 + }
1300 +
1301 + bcm2835_sdhost_write(host, sdcmd | SDCMD_NEW_FLAG, SDCMD);
1302 +
1303 + return true;
1304 +}
1305 +
1306 +static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,
1307 + unsigned long *irq_flags);
1308 +static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host);
1309 +
1310 +static void bcm2835_sdhost_finish_data(struct bcm2835_host *host)
1311 +{
1312 + struct mmc_data *data;
1313 +
1314 + data = host->data;
1315 + BUG_ON(!data);
1316 +
1317 + log_event("FDA<", (u32)host->mrq, (u32)host->cmd);
1318 + pr_debug("finish_data(error %d, stop %d, sbc %d)\n",
1319 + data->error, data->stop ? 1 : 0,
1320 + host->mrq->sbc ? 1 : 0);
1321 +
1322 + host->hcfg &= ~(SDHCFG_DATA_IRPT_EN | SDHCFG_BLOCK_IRPT_EN);
1323 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1324 +
1325 + data->bytes_xfered = data->error ? 0 : (data->blksz * data->blocks);
1326 +
1327 + host->data_complete = 1;
1328 +
1329 + if (host->cmd) {
1330 + /*
1331 + * Data managed to finish before the
1332 + * command completed. Make sure we do
1333 + * things in the proper order.
1334 + */
1335 + pr_debug("Finished early - HSTS %x\n",
1336 + bcm2835_sdhost_read(host, SDHSTS));
1337 + }
1338 + else
1339 + bcm2835_sdhost_transfer_complete(host);
1340 + log_event("FDA>", (u32)host->mrq, (u32)host->cmd);
1341 +}
1342 +
1343 +static void bcm2835_sdhost_transfer_complete(struct bcm2835_host *host)
1344 +{
1345 + struct mmc_data *data;
1346 +
1347 + BUG_ON(host->cmd);
1348 + BUG_ON(!host->data);
1349 + BUG_ON(!host->data_complete);
1350 +
1351 + data = host->data;
1352 + host->data = NULL;
1353 +
1354 + log_event("TCM<", (u32)data, data->error);
1355 + pr_debug("transfer_complete(error %d, stop %d)\n",
1356 + data->error, data->stop ? 1 : 0);
1357 +
1358 + /*
1359 + * Need to send CMD12 if -
1360 + * a) open-ended multiblock transfer (no CMD23)
1361 + * b) error in multiblock transfer
1362 + */
1363 + if (host->mrq->stop && (data->error || !host->use_sbc)) {
1364 + if (bcm2835_sdhost_send_command(host, host->mrq->stop)) {
1365 + /* No busy, so poll for completion */
1366 + if (!host->use_busy)
1367 + bcm2835_sdhost_finish_command(host, NULL);
1368 +
1369 + if (host->delay_after_this_stop)
1370 + do_gettimeofday(&host->stop_time);
1371 + }
1372 + } else {
1373 + bcm2835_sdhost_wait_transfer_complete(host);
1374 + tasklet_schedule(&host->finish_tasklet);
1375 + }
1376 + log_event("TCM>", (u32)data, 0);
1377 +}
1378 +
1379 +/* If irq_flags is valid, the caller is in a thread context and is allowed
1380 + to sleep */
1381 +static void bcm2835_sdhost_finish_command(struct bcm2835_host *host,
1382 + unsigned long *irq_flags)
1383 +{
1384 + u32 sdcmd;
1385 + u32 retries;
1386 +#ifdef DEBUG
1387 + struct timeval before, after;
1388 + int timediff = 0;
1389 +#endif
1390 +
1391 + log_event("FCM<", (u32)host->mrq, (u32)host->cmd);
1392 + pr_debug("finish_command(%x)\n", bcm2835_sdhost_read(host, SDCMD));
1393 +
1394 + BUG_ON(!host->cmd || !host->mrq);
1395 +
1396 + /* Poll quickly at first */
1397 +
1398 + retries = host->cmd_quick_poll_retries;
1399 + if (!retries) {
1400 + /* Work out how many polls take 1us by timing 10us */
1401 + struct timeval start, now;
1402 + int us_diff;
1403 +
1404 + retries = 1;
1405 + do {
1406 + int i;
1407 +
1408 + retries *= 2;
1409 +
1410 + do_gettimeofday(&start);
1411 +
1412 + for (i = 0; i < retries; i++) {
1413 + cpu_relax();
1414 + sdcmd = bcm2835_sdhost_read(host, SDCMD);
1415 + }
1416 +
1417 + do_gettimeofday(&now);
1418 + us_diff = (now.tv_sec - start.tv_sec) * 1000000 +
1419 + (now.tv_usec - start.tv_usec);
1420 + } while (us_diff < 10);
1421 +
1422 + host->cmd_quick_poll_retries = ((retries * us_diff + 9)*CMD_DALLY_US)/10 + 1;
1423 + retries = 1; // We've already waited long enough this time
1424 + }
1425 +
1426 + for (sdcmd = bcm2835_sdhost_read(host, SDCMD);
1427 + (sdcmd & SDCMD_NEW_FLAG) && retries;
1428 + retries--) {
1429 + cpu_relax();
1430 + sdcmd = bcm2835_sdhost_read(host, SDCMD);
1431 + }
1432 +
1433 + if (!retries) {
1434 + unsigned long wait_max;
1435 +
1436 + if (!irq_flags) {
1437 + /* Schedule the work */
1438 + log_event("CWWQ", 0, 0);
1439 + schedule_work(&host->cmd_wait_wq);
1440 + return;
1441 + }
1442 +
1443 + /* Wait max 100 ms */
1444 + wait_max = jiffies + msecs_to_jiffies(100);
1445 + while (time_before(jiffies, wait_max)) {
1446 + spin_unlock_irqrestore(&host->lock, *irq_flags);
1447 + usleep_range(1, 10);
1448 + spin_lock_irqsave(&host->lock, *irq_flags);
1449 + sdcmd = bcm2835_sdhost_read(host, SDCMD);
1450 + if (!(sdcmd & SDCMD_NEW_FLAG))
1451 + break;
1452 + }
1453 + }
1454 +
1455 + /* Check for errors */
1456 + if (sdcmd & SDCMD_NEW_FLAG) {
1457 + if (host->debug) {
1458 + pr_err("%s: command %d never completed.\n",
1459 + mmc_hostname(host->mmc), host->cmd->opcode);
1460 + bcm2835_sdhost_dumpregs(host);
1461 + }
1462 + host->cmd->error = -EILSEQ;
1463 + tasklet_schedule(&host->finish_tasklet);
1464 + return;
1465 + } else if (sdcmd & SDCMD_FAIL_FLAG) {
1466 + u32 sdhsts = bcm2835_sdhost_read(host, SDHSTS);
1467 +
1468 + /* Clear the errors */
1469 + bcm2835_sdhost_write(host, SDHSTS_ERROR_MASK, SDHSTS);
1470 +
1471 + if (host->debug)
1472 + pr_info("%s: error detected - CMD %x, HSTS %03x, EDM %x\n",
1473 + mmc_hostname(host->mmc), sdcmd, sdhsts,
1474 + bcm2835_sdhost_read(host, SDEDM));
1475 +
1476 + if ((sdhsts & SDHSTS_CRC7_ERROR) &&
1477 + (host->cmd->opcode == 1)) {
1478 + if (host->debug)
1479 + pr_info("%s: ignoring CRC7 error for CMD1\n",
1480 + mmc_hostname(host->mmc));
1481 + } else {
1482 + if (sdhsts & SDHSTS_CMD_TIME_OUT) {
1483 + if (host->debug)
1484 + pr_warn("%s: command %d timeout\n",
1485 + mmc_hostname(host->mmc),
1486 + host->cmd->opcode);
1487 + host->cmd->error = -ETIMEDOUT;
1488 + } else {
1489 + pr_warn("%s: unexpected command %d error\n",
1490 + mmc_hostname(host->mmc),
1491 + host->cmd->opcode);
1492 + host->cmd->error = -EILSEQ;
1493 + }
1494 + tasklet_schedule(&host->finish_tasklet);
1495 + return;
1496 + }
1497 + }
1498 +
1499 + if (host->cmd->flags & MMC_RSP_PRESENT) {
1500 + if (host->cmd->flags & MMC_RSP_136) {
1501 + int i;
1502 + for (i = 0; i < 4; i++)
1503 + host->cmd->resp[3 - i] = bcm2835_sdhost_read(host, SDRSP0 + i*4);
1504 + pr_debug("%s: finish_command %08x %08x %08x %08x\n",
1505 + mmc_hostname(host->mmc),
1506 + host->cmd->resp[0], host->cmd->resp[1], host->cmd->resp[2], host->cmd->resp[3]);
1507 + log_event("RSP ", host->cmd->resp[0], host->cmd->resp[1]);
1508 + } else {
1509 + host->cmd->resp[0] = bcm2835_sdhost_read(host, SDRSP0);
1510 + pr_debug("%s: finish_command %08x\n",
1511 + mmc_hostname(host->mmc),
1512 + host->cmd->resp[0]);
1513 + log_event("RSP ", host->cmd->resp[0], 0);
1514 + }
1515 + }
1516 +
1517 + if (host->cmd == host->mrq->sbc) {
1518 + /* Finished CMD23, now send actual command. */
1519 + host->cmd = NULL;
1520 + if (bcm2835_sdhost_send_command(host, host->mrq->cmd)) {
1521 + if (host->data && host->dma_desc)
1522 + /* DMA transfer starts now, PIO starts after irq */
1523 + bcm2835_sdhost_start_dma(host);
1524 +
1525 + if (!host->use_busy)
1526 + bcm2835_sdhost_finish_command(host, NULL);
1527 + }
1528 + } else if (host->cmd == host->mrq->stop) {
1529 + /* Finished CMD12 */
1530 + tasklet_schedule(&host->finish_tasklet);
1531 + } else {
1532 + /* Processed actual command. */
1533 + host->cmd = NULL;
1534 + if (!host->data)
1535 + tasklet_schedule(&host->finish_tasklet);
1536 + else if (host->data_complete)
1537 + bcm2835_sdhost_transfer_complete(host);
1538 + }
1539 + log_event("FCM>", (u32)host->mrq, (u32)host->cmd);
1540 +}
1541 +
1542 +static void bcm2835_sdhost_timeout(struct timer_list *t)
1543 +{
1544 + struct bcm2835_host *host = from_timer(host, t, timer);
1545 + unsigned long flags;
1546 +
1547 + spin_lock_irqsave(&host->lock, flags);
1548 + log_event("TIM<", 0, 0);
1549 +
1550 + if (host->mrq) {
1551 + pr_err("%s: timeout waiting for hardware interrupt.\n",
1552 + mmc_hostname(host->mmc));
1553 + log_dump();
1554 + bcm2835_sdhost_dumpregs(host);
1555 +
1556 + if (host->data) {
1557 + host->data->error = -ETIMEDOUT;
1558 + bcm2835_sdhost_finish_data(host);
1559 + } else {
1560 + if (host->cmd)
1561 + host->cmd->error = -ETIMEDOUT;
1562 + else
1563 + host->mrq->cmd->error = -ETIMEDOUT;
1564 +
1565 + pr_debug("timeout_timer tasklet_schedule\n");
1566 + tasklet_schedule(&host->finish_tasklet);
1567 + }
1568 + }
1569 +
1570 + mmiowb();
1571 + spin_unlock_irqrestore(&host->lock, flags);
1572 +}
1573 +
1574 +static void bcm2835_sdhost_busy_irq(struct bcm2835_host *host, u32 intmask)
1575 +{
1576 + log_event("IRQB", (u32)host->cmd, intmask);
1577 + if (!host->cmd) {
1578 + pr_err("%s: got command busy interrupt 0x%08x even "
1579 + "though no command operation was in progress.\n",
1580 + mmc_hostname(host->mmc), (unsigned)intmask);
1581 + bcm2835_sdhost_dumpregs(host);
1582 + return;
1583 + }
1584 +
1585 + if (!host->use_busy) {
1586 + pr_err("%s: got command busy interrupt 0x%08x even "
1587 + "though not expecting one.\n",
1588 + mmc_hostname(host->mmc), (unsigned)intmask);
1589 + bcm2835_sdhost_dumpregs(host);
1590 + return;
1591 + }
1592 + host->use_busy = 0;
1593 +
1594 + if (intmask & SDHSTS_ERROR_MASK)
1595 + {
1596 + pr_err("sdhost_busy_irq: intmask %x, data %p\n", intmask, host->mrq->data);
1597 + if (intmask & SDHSTS_CRC7_ERROR)
1598 + host->cmd->error = -EILSEQ;
1599 + else if (intmask & (SDHSTS_CRC16_ERROR |
1600 + SDHSTS_FIFO_ERROR)) {
1601 + if (host->mrq->data)
1602 + host->mrq->data->error = -EILSEQ;
1603 + else
1604 + host->cmd->error = -EILSEQ;
1605 + } else if (intmask & SDHSTS_REW_TIME_OUT) {
1606 + if (host->mrq->data)
1607 + host->mrq->data->error = -ETIMEDOUT;
1608 + else
1609 + host->cmd->error = -ETIMEDOUT;
1610 + } else if (intmask & SDHSTS_CMD_TIME_OUT)
1611 + host->cmd->error = -ETIMEDOUT;
1612 +
1613 + if (host->debug) {
1614 + log_dump();
1615 + bcm2835_sdhost_dumpregs(host);
1616 + }
1617 + }
1618 + else
1619 + bcm2835_sdhost_finish_command(host, NULL);
1620 +}
1621 +
1622 +static void bcm2835_sdhost_data_irq(struct bcm2835_host *host, u32 intmask)
1623 +{
1624 + /* There are no dedicated data/space available interrupt
1625 + status bits, so it is necessary to use the single shared
1626 + data/space available FIFO status bits. It is therefore not
1627 + an error to get here when there is no data transfer in
1628 + progress. */
1629 + log_event("IRQD", (u32)host->data, intmask);
1630 + if (!host->data)
1631 + return;
1632 +
1633 + if (intmask & (SDHSTS_CRC16_ERROR |
1634 + SDHSTS_FIFO_ERROR |
1635 + SDHSTS_REW_TIME_OUT)) {
1636 + if (intmask & (SDHSTS_CRC16_ERROR |
1637 + SDHSTS_FIFO_ERROR))
1638 + host->data->error = -EILSEQ;
1639 + else
1640 + host->data->error = -ETIMEDOUT;
1641 +
1642 + if (host->debug) {
1643 + log_dump();
1644 + bcm2835_sdhost_dumpregs(host);
1645 + }
1646 + }
1647 +
1648 + if (host->data->error) {
1649 + bcm2835_sdhost_finish_data(host);
1650 + } else if (host->data->flags & MMC_DATA_WRITE) {
1651 + /* Use the block interrupt for writes after the first block */
1652 + host->hcfg &= ~(SDHCFG_DATA_IRPT_EN);
1653 + host->hcfg |= SDHCFG_BLOCK_IRPT_EN;
1654 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1655 + bcm2835_sdhost_transfer_pio(host);
1656 + } else {
1657 + bcm2835_sdhost_transfer_pio(host);
1658 + host->blocks--;
1659 + if ((host->blocks == 0) || host->data->error)
1660 + bcm2835_sdhost_finish_data(host);
1661 + }
1662 +}
1663 +
1664 +static void bcm2835_sdhost_block_irq(struct bcm2835_host *host, u32 intmask)
1665 +{
1666 + log_event("IRQK", (u32)host->data, intmask);
1667 + if (!host->data) {
1668 + pr_err("%s: got block interrupt 0x%08x even "
1669 + "though no data operation was in progress.\n",
1670 + mmc_hostname(host->mmc), (unsigned)intmask);
1671 + bcm2835_sdhost_dumpregs(host);
1672 + return;
1673 + }
1674 +
1675 + if (intmask & (SDHSTS_CRC16_ERROR |
1676 + SDHSTS_FIFO_ERROR |
1677 + SDHSTS_REW_TIME_OUT)) {
1678 + if (intmask & (SDHSTS_CRC16_ERROR |
1679 + SDHSTS_FIFO_ERROR))
1680 + host->data->error = -EILSEQ;
1681 + else
1682 + host->data->error = -ETIMEDOUT;
1683 +
1684 + if (host->debug) {
1685 + log_dump();
1686 + bcm2835_sdhost_dumpregs(host);
1687 + }
1688 + }
1689 +
1690 + if (!host->dma_desc) {
1691 + BUG_ON(!host->blocks);
1692 + if (host->data->error || (--host->blocks == 0)) {
1693 + bcm2835_sdhost_finish_data(host);
1694 + } else {
1695 + bcm2835_sdhost_transfer_pio(host);
1696 + }
1697 + } else if (host->data->flags & MMC_DATA_WRITE) {
1698 + bcm2835_sdhost_finish_data(host);
1699 + }
1700 +}
1701 +
1702 +static irqreturn_t bcm2835_sdhost_irq(int irq, void *dev_id)
1703 +{
1704 + irqreturn_t result = IRQ_NONE;
1705 + struct bcm2835_host *host = dev_id;
1706 + u32 intmask;
1707 +
1708 + spin_lock(&host->lock);
1709 +
1710 + intmask = bcm2835_sdhost_read(host, SDHSTS);
1711 + log_event("IRQ<", intmask, 0);
1712 +
1713 + bcm2835_sdhost_write(host,
1714 + SDHSTS_BUSY_IRPT |
1715 + SDHSTS_BLOCK_IRPT |
1716 + SDHSTS_SDIO_IRPT |
1717 + SDHSTS_DATA_FLAG,
1718 + SDHSTS);
1719 +
1720 + if (intmask & SDHSTS_BLOCK_IRPT) {
1721 + bcm2835_sdhost_block_irq(host, intmask);
1722 + result = IRQ_HANDLED;
1723 + }
1724 +
1725 + if (intmask & SDHSTS_BUSY_IRPT) {
1726 + bcm2835_sdhost_busy_irq(host, intmask);
1727 + result = IRQ_HANDLED;
1728 + }
1729 +
1730 + /* There is no true data interrupt status bit, so it is
1731 + necessary to qualify the data flag with the interrupt
1732 + enable bit */
1733 + if ((intmask & SDHSTS_DATA_FLAG) &&
1734 + (host->hcfg & SDHCFG_DATA_IRPT_EN)) {
1735 + bcm2835_sdhost_data_irq(host, intmask);
1736 + result = IRQ_HANDLED;
1737 + }
1738 +
1739 + mmiowb();
1740 +
1741 + log_event("IRQ>", bcm2835_sdhost_read(host, SDHSTS), 0);
1742 + spin_unlock(&host->lock);
1743 +
1744 + return result;
1745 +}
1746 +
1747 +void bcm2835_sdhost_set_clock(struct bcm2835_host *host, unsigned int clock)
1748 +{
1749 + int div = 0; /* Initialized for compiler warning */
1750 + unsigned int input_clock = clock;
1751 + unsigned long flags;
1752 +
1753 + if (host->debug)
1754 + pr_info("%s: set_clock(%d)\n", mmc_hostname(host->mmc), clock);
1755 +
1756 + if (host->overclock_50 && (clock == 50*MHZ))
1757 + clock = host->overclock_50 * MHZ + (MHZ - 1);
1758 +
1759 + /* The SDCDIV register has 11 bits, and holds (div - 2).
1760 + But in data mode the max is 50MHz wihout a minimum, and only the
1761 + bottom 3 bits are used. Since the switch over is automatic (unless
1762 + we have marked the card as slow...), chosen values have to make
1763 + sense in both modes.
1764 + Ident mode must be 100-400KHz, so can range check the requested
1765 + clock. CMD15 must be used to return to data mode, so this can be
1766 + monitored.
1767 +
1768 + clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
1769 + 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
1770 +
1771 + 623->400KHz/27.8MHz
1772 + reset value (507)->491159/50MHz
1773 +
1774 + BUT, the 3-bit clock divisor in data mode is too small if the
1775 + core clock is higher than 250MHz, so instead use the SLOW_CARD
1776 + configuration bit to force the use of the ident clock divisor
1777 + at all times.
1778 + */
1779 +
1780 + host->mmc->actual_clock = 0;
1781 +
1782 + if (host->firmware_sets_cdiv) {
1783 + u32 msg[3] = { clock, 0, 0 };
1784 +
1785 + rpi_firmware_property(rpi_firmware_get(NULL),
1786 + RPI_FIRMWARE_SET_SDHOST_CLOCK,
1787 + &msg, sizeof(msg));
1788 +
1789 + clock = max(msg[1], msg[2]);
1790 + spin_lock_irqsave(&host->lock, flags);
1791 + } else {
1792 + spin_lock_irqsave(&host->lock, flags);
1793 + if (clock < 100000) {
1794 + /* Can't stop the clock, but make it as slow as
1795 + * possible to show willing
1796 + */
1797 + host->cdiv = SDCDIV_MAX_CDIV;
1798 + bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
1799 + mmiowb();
1800 + spin_unlock_irqrestore(&host->lock, flags);
1801 + return;
1802 + }
1803 +
1804 + div = host->max_clk / clock;
1805 + if (div < 2)
1806 + div = 2;
1807 + if ((host->max_clk / div) > clock)
1808 + div++;
1809 + div -= 2;
1810 +
1811 + if (div > SDCDIV_MAX_CDIV)
1812 + div = SDCDIV_MAX_CDIV;
1813 +
1814 + clock = host->max_clk / (div + 2);
1815 +
1816 + host->cdiv = div;
1817 + bcm2835_sdhost_write(host, host->cdiv, SDCDIV);
1818 +
1819 + if (host->debug)
1820 + pr_info("%s: clock=%d -> max_clk=%d, cdiv=%x "
1821 + "(actual clock %d)\n",
1822 + mmc_hostname(host->mmc), input_clock,
1823 + host->max_clk, host->cdiv,
1824 + clock);
1825 + }
1826 +
1827 + /* Calibrate some delays */
1828 +
1829 + host->ns_per_fifo_word = (1000000000/clock) *
1830 + ((host->mmc->caps & MMC_CAP_4_BIT_DATA) ? 8 : 32);
1831 +
1832 + if (input_clock == 50 * MHZ) {
1833 + if (clock > input_clock) {
1834 + /* Save the closest value, to make it easier
1835 + to reduce in the event of error */
1836 + host->overclock_50 = (clock/MHZ);
1837 +
1838 + if (clock != host->overclock) {
1839 + pr_info("%s: overclocking to %dHz\n",
1840 + mmc_hostname(host->mmc), clock);
1841 + host->overclock = clock;
1842 + }
1843 + } else if (host->overclock) {
1844 + host->overclock = 0;
1845 + if (clock == 50 * MHZ)
1846 + pr_warn("%s: cancelling overclock\n",
1847 + mmc_hostname(host->mmc));
1848 + }
1849 + } else if (input_clock == 0) {
1850 + /* Reset the preferred overclock when the clock is stopped.
1851 + * This always happens during initialisation. */
1852 + host->overclock_50 = host->user_overclock_50;
1853 + host->overclock = 0;
1854 + }
1855 +
1856 + /* Set the timeout to 500ms */
1857 + bcm2835_sdhost_write(host, clock/2, SDTOUT);
1858 +
1859 + host->mmc->actual_clock = clock;
1860 + host->clock = input_clock;
1861 + host->reset_clock = 0;
1862 +
1863 + mmiowb();
1864 + spin_unlock_irqrestore(&host->lock, flags);
1865 +}
1866 +
1867 +static void bcm2835_sdhost_request(struct mmc_host *mmc, struct mmc_request *mrq)
1868 +{
1869 + struct bcm2835_host *host;
1870 + unsigned long flags;
1871 + u32 edm, fsm;
1872 +
1873 + host = mmc_priv(mmc);
1874 +
1875 + if (host->debug) {
1876 + struct mmc_command *cmd = mrq->cmd;
1877 + BUG_ON(!cmd);
1878 + if (cmd->data)
1879 + pr_info("%s: cmd %d 0x%x (flags 0x%x) - %s %d*%d\n",
1880 + mmc_hostname(mmc),
1881 + cmd->opcode, cmd->arg, cmd->flags,
1882 + (cmd->data->flags & MMC_DATA_READ) ?
1883 + "read" : "write", cmd->data->blocks,
1884 + cmd->data->blksz);
1885 + else
1886 + pr_info("%s: cmd %d 0x%x (flags 0x%x)\n",
1887 + mmc_hostname(mmc),
1888 + cmd->opcode, cmd->arg, cmd->flags);
1889 + }
1890 +
1891 + /* Reset the error statuses in case this is a retry */
1892 + if (mrq->sbc)
1893 + mrq->sbc->error = 0;
1894 + if (mrq->cmd)
1895 + mrq->cmd->error = 0;
1896 + if (mrq->data)
1897 + mrq->data->error = 0;
1898 + if (mrq->stop)
1899 + mrq->stop->error = 0;
1900 +
1901 + if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
1902 + pr_err("%s: unsupported block size (%d bytes)\n",
1903 + mmc_hostname(mmc), mrq->data->blksz);
1904 + mrq->cmd->error = -EINVAL;
1905 + mmc_request_done(mmc, mrq);
1906 + return;
1907 + }
1908 +
1909 + if (host->use_dma && mrq->data &&
1910 + (mrq->data->blocks > host->pio_limit))
1911 + bcm2835_sdhost_prepare_dma(host, mrq->data);
1912 +
1913 + if (host->reset_clock)
1914 + bcm2835_sdhost_set_clock(host, host->clock);
1915 +
1916 + spin_lock_irqsave(&host->lock, flags);
1917 +
1918 + WARN_ON(host->mrq != NULL);
1919 + host->mrq = mrq;
1920 +
1921 + edm = bcm2835_sdhost_read(host, SDEDM);
1922 + fsm = edm & SDEDM_FSM_MASK;
1923 +
1924 + log_event("REQ<", (u32)mrq, edm);
1925 + if ((fsm != SDEDM_FSM_IDENTMODE) &&
1926 + (fsm != SDEDM_FSM_DATAMODE)) {
1927 + log_event("REQ!", (u32)mrq, edm);
1928 + if (host->debug) {
1929 + pr_warn("%s: previous command (%d) not complete (EDM %x)\n",
1930 + mmc_hostname(host->mmc),
1931 + bcm2835_sdhost_read(host, SDCMD) & SDCMD_CMD_MASK,
1932 + edm);
1933 + log_dump();
1934 + bcm2835_sdhost_dumpregs(host);
1935 + }
1936 + mrq->cmd->error = -EILSEQ;
1937 + tasklet_schedule(&host->finish_tasklet);
1938 + mmiowb();
1939 + spin_unlock_irqrestore(&host->lock, flags);
1940 + return;
1941 + }
1942 +
1943 + host->use_sbc = !!mrq->sbc &&
1944 + (host->mrq->data->flags & USE_CMD23_FLAGS);
1945 + if (host->use_sbc) {
1946 + if (bcm2835_sdhost_send_command(host, mrq->sbc)) {
1947 + if (!host->use_busy)
1948 + bcm2835_sdhost_finish_command(host, &flags);
1949 + }
1950 + } else if (bcm2835_sdhost_send_command(host, mrq->cmd)) {
1951 + if (host->data && host->dma_desc)
1952 + /* DMA transfer starts now, PIO starts after irq */
1953 + bcm2835_sdhost_start_dma(host);
1954 +
1955 + if (!host->use_busy)
1956 + bcm2835_sdhost_finish_command(host, &flags);
1957 + }
1958 +
1959 + log_event("CMD ", (u32)mrq->cmd->opcode,
1960 + mrq->data ? (u32)mrq->data->blksz : 0);
1961 + mmiowb();
1962 +
1963 + log_event("REQ>", (u32)mrq, 0);
1964 + spin_unlock_irqrestore(&host->lock, flags);
1965 +}
1966 +
1967 +static void bcm2835_sdhost_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1968 +{
1969 +
1970 + struct bcm2835_host *host = mmc_priv(mmc);
1971 + unsigned long flags;
1972 +
1973 + if (host->debug)
1974 + pr_info("%s: ios clock %d, pwr %d, bus_width %d, "
1975 + "timing %d, vdd %d, drv_type %d\n",
1976 + mmc_hostname(mmc),
1977 + ios->clock, ios->power_mode, ios->bus_width,
1978 + ios->timing, ios->signal_voltage, ios->drv_type);
1979 +
1980 + spin_lock_irqsave(&host->lock, flags);
1981 +
1982 + log_event("IOS<", ios->clock, 0);
1983 +
1984 + /* set bus width */
1985 + host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
1986 + if (ios->bus_width == MMC_BUS_WIDTH_4)
1987 + host->hcfg |= SDHCFG_WIDE_EXT_BUS;
1988 +
1989 + host->hcfg |= SDHCFG_WIDE_INT_BUS;
1990 +
1991 + /* Disable clever clock switching, to cope with fast core clocks */
1992 + host->hcfg |= SDHCFG_SLOW_CARD;
1993 +
1994 + bcm2835_sdhost_write(host, host->hcfg, SDHCFG);
1995 +
1996 + mmiowb();
1997 +
1998 + spin_unlock_irqrestore(&host->lock, flags);
1999 +
2000 + if (!ios->clock || ios->clock != host->clock)
2001 + bcm2835_sdhost_set_clock(host, ios->clock);
2002 +}
2003 +
2004 +static struct mmc_host_ops bcm2835_sdhost_ops = {
2005 + .request = bcm2835_sdhost_request,
2006 + .set_ios = bcm2835_sdhost_set_ios,
2007 + .hw_reset = bcm2835_sdhost_reset,
2008 +};
2009 +
2010 +static void bcm2835_sdhost_cmd_wait_work(struct work_struct *work)
2011 +{
2012 + struct bcm2835_host *host;
2013 + unsigned long flags;
2014 +
2015 + host = container_of(work, struct bcm2835_host, cmd_wait_wq);
2016 +
2017 + spin_lock_irqsave(&host->lock, flags);
2018 +
2019 + log_event("CWK<", (u32)host->cmd, (u32)host->mrq);
2020 +
2021 + /*
2022 + * If this tasklet gets rescheduled while running, it will
2023 + * be run again afterwards but without any active request.
2024 + */
2025 + if (!host->mrq) {
2026 + spin_unlock_irqrestore(&host->lock, flags);
2027 + return;
2028 + }
2029 +
2030 + bcm2835_sdhost_finish_command(host, &flags);
2031 +
2032 + mmiowb();
2033 +
2034 + log_event("CWK>", (u32)host->cmd, 0);
2035 +
2036 + spin_unlock_irqrestore(&host->lock, flags);
2037 +}
2038 +
2039 +static void bcm2835_sdhost_tasklet_finish(unsigned long param)
2040 +{
2041 + struct bcm2835_host *host;
2042 + unsigned long flags;
2043 + struct mmc_request *mrq;
2044 + struct dma_chan *terminate_chan = NULL;
2045 +
2046 + host = (struct bcm2835_host *)param;
2047 +
2048 + spin_lock_irqsave(&host->lock, flags);
2049 +
2050 + log_event("TSK<", (u32)host->mrq, 0);
2051 + /*
2052 + * If this tasklet gets rescheduled while running, it will
2053 + * be run again afterwards but without any active request.
2054 + */
2055 + if (!host->mrq) {
2056 + spin_unlock_irqrestore(&host->lock, flags);
2057 + return;
2058 + }
2059 +
2060 + del_timer(&host->timer);
2061 +
2062 + mrq = host->mrq;
2063 +
2064 + /* Drop the overclock after any data corruption, or after any
2065 + * error while overclocked. Ignore errors for status commands,
2066 + * as they are likely when a card is ejected. */
2067 + if (host->overclock) {
2068 + if ((mrq->cmd && mrq->cmd->error &&
2069 + (mrq->cmd->opcode != MMC_SEND_STATUS)) ||
2070 + (mrq->data && mrq->data->error) ||
2071 + (mrq->stop && mrq->stop->error) ||
2072 + (mrq->sbc && mrq->sbc->error)) {
2073 + host->overclock_50--;
2074 + pr_warn("%s: reducing overclock due to errors\n",
2075 + mmc_hostname(host->mmc));
2076 + host->reset_clock = 1;
2077 + mrq->cmd->error = -ETIMEDOUT;
2078 + mrq->cmd->retries = 1;
2079 + }
2080 + }
2081 +
2082 + host->mrq = NULL;
2083 + host->cmd = NULL;
2084 + host->data = NULL;
2085 +
2086 + mmiowb();
2087 +
2088 + host->dma_desc = NULL;
2089 + terminate_chan = host->dma_chan;
2090 + host->dma_chan = NULL;
2091 +
2092 + spin_unlock_irqrestore(&host->lock, flags);
2093 +
2094 + if (terminate_chan)
2095 + {
2096 + int err = dmaengine_terminate_all(terminate_chan);
2097 + if (err)
2098 + pr_err("%s: failed to terminate DMA (%d)\n",
2099 + mmc_hostname(host->mmc), err);
2100 + }
2101 +
2102 + /* The SDHOST block doesn't report any errors for a disconnected
2103 + interface. All cards and SDIO devices should report some supported
2104 + voltage range, so a zero response to SEND_OP_COND, IO_SEND_OP_COND
2105 + or APP_SEND_OP_COND can be treated as an error. */
2106 + if (((mrq->cmd->opcode == MMC_SEND_OP_COND) ||
2107 + (mrq->cmd->opcode == SD_IO_SEND_OP_COND) ||
2108 + (mrq->cmd->opcode == SD_APP_OP_COND)) &&
2109 + (mrq->cmd->error == 0) &&
2110 + (mrq->cmd->resp[0] == 0)) {
2111 + mrq->cmd->error = -ETIMEDOUT;
2112 + if (host->debug)
2113 + pr_info("%s: faking timeout due to zero OCR\n",
2114 + mmc_hostname(host->mmc));
2115 + }
2116 +
2117 + mmc_request_done(host->mmc, mrq);
2118 + log_event("TSK>", (u32)mrq, 0);
2119 +}
2120 +
2121 +int bcm2835_sdhost_add_host(struct bcm2835_host *host)
2122 +{
2123 + struct mmc_host *mmc;
2124 + struct dma_slave_config cfg;
2125 + char pio_limit_string[20];
2126 + int ret;
2127 +
2128 + mmc = host->mmc;
2129 +
2130 + if (!mmc->f_max || mmc->f_max > host->max_clk)
2131 + mmc->f_max = host->max_clk;
2132 + mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV;
2133 +
2134 + mmc->max_busy_timeout = (~(unsigned int)0)/(mmc->f_max/1000);
2135 +
2136 + pr_debug("f_max %d, f_min %d, max_busy_timeout %d\n",
2137 + mmc->f_max, mmc->f_min, mmc->max_busy_timeout);
2138 +
2139 + /* host controller capabilities */
2140 + mmc->caps |=
2141 + MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
2142 + MMC_CAP_NEEDS_POLL | MMC_CAP_HW_RESET | MMC_CAP_ERASE |
2143 + ((ALLOW_CMD23_READ|ALLOW_CMD23_WRITE) * MMC_CAP_CMD23);
2144 +
2145 + spin_lock_init(&host->lock);
2146 +
2147 + if (host->allow_dma) {
2148 + if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
2149 + pr_err("%s: unable to initialise DMA channel. "
2150 + "Falling back to PIO\n",
2151 + mmc_hostname(mmc));
2152 + host->use_dma = false;
2153 + } else {
2154 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2155 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2156 + cfg.slave_id = 13; /* DREQ channel */
2157 +
2158 + /* Validate the slave configurations */
2159 +
2160 + cfg.direction = DMA_MEM_TO_DEV;
2161 + cfg.src_addr = 0;
2162 + cfg.dst_addr = host->bus_addr + SDDATA;
2163 +
2164 + ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
2165 +
2166 + if (ret == 0) {
2167 + host->dma_cfg_tx = cfg;
2168 +
2169 + cfg.direction = DMA_DEV_TO_MEM;
2170 + cfg.src_addr = host->bus_addr + SDDATA;
2171 + cfg.dst_addr = 0;
2172 +
2173 + ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
2174 + }
2175 +
2176 + if (ret == 0) {
2177 + host->dma_cfg_rx = cfg;
2178 +
2179 + host->use_dma = true;
2180 + } else {
2181 + pr_err("%s: unable to configure DMA channel. "
2182 + "Falling back to PIO\n",
2183 + mmc_hostname(mmc));
2184 + dma_release_channel(host->dma_chan_rxtx);
2185 + host->dma_chan_rxtx = NULL;
2186 + host->use_dma = false;
2187 + }
2188 + }
2189 + } else {
2190 + host->use_dma = false;
2191 + }
2192 +
2193 + mmc->max_segs = 128;
2194 + mmc->max_req_size = 524288;
2195 + mmc->max_seg_size = mmc->max_req_size;
2196 + mmc->max_blk_size = 512;
2197 + mmc->max_blk_count = 65535;
2198 +
2199 + /* report supported voltage ranges */
2200 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2201 +
2202 + tasklet_init(&host->finish_tasklet,
2203 + bcm2835_sdhost_tasklet_finish, (unsigned long)host);
2204 +
2205 + INIT_WORK(&host->cmd_wait_wq, bcm2835_sdhost_cmd_wait_work);
2206 +
2207 + timer_setup(&host->timer, bcm2835_sdhost_timeout, 0);
2208 +
2209 + bcm2835_sdhost_init(host, 0);
2210 +
2211 + ret = request_irq(host->irq, bcm2835_sdhost_irq, 0 /*IRQF_SHARED*/,
2212 + mmc_hostname(mmc), host);
2213 + if (ret) {
2214 + pr_err("%s: failed to request IRQ %d: %d\n",
2215 + mmc_hostname(mmc), host->irq, ret);
2216 + goto untasklet;
2217 + }
2218 +
2219 + mmiowb();
2220 + mmc_add_host(mmc);
2221 +
2222 + pio_limit_string[0] = '\0';
2223 + if (host->use_dma && (host->pio_limit > 0))
2224 + sprintf(pio_limit_string, " (>%d)", host->pio_limit);
2225 + pr_info("%s: %s loaded - DMA %s%s\n",
2226 + mmc_hostname(mmc), DRIVER_NAME,
2227 + host->use_dma ? "enabled" : "disabled",
2228 + pio_limit_string);
2229 +
2230 + return 0;
2231 +
2232 +untasklet:
2233 + tasklet_kill(&host->finish_tasklet);
2234 +
2235 + return ret;
2236 +}
2237 +
2238 +static int bcm2835_sdhost_probe(struct platform_device *pdev)
2239 +{
2240 + struct device *dev = &pdev->dev;
2241 + struct device_node *node = dev->of_node;
2242 + struct clk *clk;
2243 + struct resource *iomem;
2244 + struct bcm2835_host *host;
2245 + struct mmc_host *mmc;
2246 + const __be32 *addr;
2247 + u32 msg[3];
2248 + int ret;
2249 +
2250 + pr_debug("bcm2835_sdhost_probe\n");
2251 + mmc = mmc_alloc_host(sizeof(*host), dev);
2252 + if (!mmc)
2253 + return -ENOMEM;
2254 +
2255 + mmc->ops = &bcm2835_sdhost_ops;
2256 + host = mmc_priv(mmc);
2257 + host->mmc = mmc;
2258 + host->pio_timeout = msecs_to_jiffies(500);
2259 + host->pio_limit = 1;
2260 + host->max_delay = 1; /* Warn if over 1ms */
2261 + host->allow_dma = 1;
2262 + spin_lock_init(&host->lock);
2263 +
2264 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2265 + host->ioaddr = devm_ioremap_resource(dev, iomem);
2266 + if (IS_ERR(host->ioaddr)) {
2267 + ret = PTR_ERR(host->ioaddr);
2268 + goto err;
2269 + }
2270 +
2271 + addr = of_get_address(node, 0, NULL, NULL);
2272 + if (!addr) {
2273 + dev_err(dev, "could not get DMA-register address\n");
2274 + return -ENODEV;
2275 + }
2276 + host->bus_addr = be32_to_cpup(addr);
2277 + pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
2278 + (unsigned long)host->ioaddr,
2279 + (unsigned long)iomem->start,
2280 + (unsigned long)host->bus_addr);
2281 +
2282 + if (node) {
2283 + /* Read any custom properties */
2284 + of_property_read_u32(node,
2285 + "brcm,delay-after-stop",
2286 + &host->delay_after_stop);
2287 + of_property_read_u32(node,
2288 + "brcm,overclock-50",
2289 + &host->user_overclock_50);
2290 + of_property_read_u32(node,
2291 + "brcm,pio-limit",
2292 + &host->pio_limit);
2293 + host->allow_dma =
2294 + !of_property_read_bool(node, "brcm,force-pio");
2295 + host->debug = of_property_read_bool(node, "brcm,debug");
2296 + }
2297 +
2298 + host->dma_chan = NULL;
2299 + host->dma_desc = NULL;
2300 +
2301 + /* Formally recognise the other way of disabling DMA */
2302 + if (host->pio_limit == 0x7fffffff)
2303 + host->allow_dma = false;
2304 +
2305 + if (host->allow_dma) {
2306 + if (node) {
2307 + host->dma_chan_rxtx =
2308 + dma_request_slave_channel(dev, "rx-tx");
2309 + if (!host->dma_chan_rxtx)
2310 + host->dma_chan_rxtx =
2311 + dma_request_slave_channel(dev, "tx");
2312 + if (!host->dma_chan_rxtx)
2313 + host->dma_chan_rxtx =
2314 + dma_request_slave_channel(dev, "rx");
2315 + } else {
2316 + dma_cap_mask_t mask;
2317 +
2318 + dma_cap_zero(mask);
2319 + /* we don't care about the channel, any would work */
2320 + dma_cap_set(DMA_SLAVE, mask);
2321 + host->dma_chan_rxtx =
2322 + dma_request_channel(mask, NULL, NULL);
2323 + }
2324 + }
2325 +
2326 + clk = devm_clk_get(dev, NULL);
2327 + if (IS_ERR(clk)) {
2328 + ret = PTR_ERR(clk);
2329 + if (ret == -EPROBE_DEFER)
2330 + dev_info(dev, "could not get clk, deferring probe\n");
2331 + else
2332 + dev_err(dev, "could not get clk\n");
2333 + goto err;
2334 + }
2335 +
2336 + host->max_clk = clk_get_rate(clk);
2337 +
2338 + host->irq = platform_get_irq(pdev, 0);
2339 + if (host->irq <= 0) {
2340 + dev_err(dev, "get IRQ failed\n");
2341 + ret = -EINVAL;
2342 + goto err;
2343 + }
2344 +
2345 + pr_debug(" - max_clk %lx, irq %d\n",
2346 + (unsigned long)host->max_clk,
2347 + (int)host->irq);
2348 +
2349 + log_init(dev, iomem->start - host->bus_addr);
2350 +
2351 + if (node)
2352 + mmc_of_parse(mmc);
2353 + else
2354 + mmc->caps |= MMC_CAP_4_BIT_DATA;
2355 +
2356 + msg[0] = 0;
2357 + msg[1] = ~0;
2358 + msg[2] = ~0;
2359 +
2360 + rpi_firmware_property(rpi_firmware_get(NULL),
2361 + RPI_FIRMWARE_SET_SDHOST_CLOCK,
2362 + &msg, sizeof(msg));
2363 +
2364 + host->firmware_sets_cdiv = (msg[1] != ~0);
2365 +
2366 + ret = bcm2835_sdhost_add_host(host);
2367 + if (ret)
2368 + goto err;
2369 +
2370 + platform_set_drvdata(pdev, host);
2371 +
2372 + pr_debug("bcm2835_sdhost_probe -> OK\n");
2373 +
2374 + return 0;
2375 +
2376 +err:
2377 + pr_debug("bcm2835_sdhost_probe -> err %d\n", ret);
2378 + mmc_free_host(mmc);
2379 +
2380 + return ret;
2381 +}
2382 +
2383 +static int bcm2835_sdhost_remove(struct platform_device *pdev)
2384 +{
2385 + struct bcm2835_host *host = platform_get_drvdata(pdev);
2386 +
2387 + pr_debug("bcm2835_sdhost_remove\n");
2388 +
2389 + mmc_remove_host(host->mmc);
2390 +
2391 + bcm2835_sdhost_set_power(host, false);
2392 +
2393 + free_irq(host->irq, host);
2394 +
2395 + del_timer_sync(&host->timer);
2396 +
2397 + tasklet_kill(&host->finish_tasklet);
2398 +
2399 + mmc_free_host(host->mmc);
2400 + platform_set_drvdata(pdev, NULL);
2401 +
2402 + pr_debug("bcm2835_sdhost_remove - OK\n");
2403 + return 0;
2404 +}
2405 +
2406 +static const struct of_device_id bcm2835_sdhost_match[] = {
2407 + { .compatible = "brcm,bcm2835-sdhost" },
2408 + { }
2409 +};
2410 +MODULE_DEVICE_TABLE(of, bcm2835_sdhost_match);
2411 +
2412 +static struct platform_driver bcm2835_sdhost_driver = {
2413 + .probe = bcm2835_sdhost_probe,
2414 + .remove = bcm2835_sdhost_remove,
2415 + .driver = {
2416 + .name = DRIVER_NAME,
2417 + .owner = THIS_MODULE,
2418 + .of_match_table = bcm2835_sdhost_match,
2419 + },
2420 +};
2421 +module_platform_driver(bcm2835_sdhost_driver);
2422 +
2423 +MODULE_ALIAS("platform:sdhost-bcm2835");
2424 +MODULE_DESCRIPTION("BCM2835 SDHost driver");
2425 +MODULE_LICENSE("GPL v2");
2426 +MODULE_AUTHOR("Phil Elwell");
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