git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From adf7289aab83651c41e7734b34844470a25ecc5f Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 25 Mar 2022 17:09:41 +0100
   4 Subject: [PATCH] drm/vc4: Make sure we don't end up with a core clock
   5  too high
   6
   7 Following the clock rate range improvements to the clock framework,
   8 trying to set a disjoint range on a clock will now result in an error.
   9
  10 Thus, we can't set a minimum rate higher than the maximum reported by
  11 the firmware, or clk_set_min_rate() will fail.
  12
  13 Thus we need to clamp the rate we are about to ask for to the maximum
  14 rate possible on that clock.
  15
  16 Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  17 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  18 ---
  19  drivers/gpu/drm/vc4/vc4_kms.c | 13 ++++++++-----
  20  1 file changed, 8 insertions(+), 5 deletions(-)
  21
  22 --- a/drivers/gpu/drm/vc4/vc4_kms.c
  23 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
  24 @@ -399,8 +399,8 @@ static void vc4_atomic_commit_tail(struc
  25         if (vc4->is_vc5 && !vc4->firmware_kms) {
  26                 unsigned long state_rate = max(old_hvs_state->core_clock_rate,
  27                                                new_hvs_state->core_clock_rate);
  28 -               unsigned long core_rate = max_t(unsigned long,
  29 -                                               500000000, state_rate);
  30 +               unsigned long core_rate = clamp_t(unsigned long, state_rate,
  31 +                                                 500000000, hvs->max_core_rate);
  32
  33                 drm_dbg(dev, "Raising the core clock at %lu Hz\n", core_rate);
  34
  35 @@ -436,14 +436,17 @@ static void vc4_atomic_commit_tail(struc
  36         drm_atomic_helper_cleanup_planes(dev, state);
  37
  38         if (vc4->is_vc5 && !vc4->firmware_kms) {
  39 -               drm_dbg(dev, "Running the core clock at %lu Hz\n",
  40 -                       new_hvs_state->core_clock_rate);
  41 +               unsigned long core_rate = min_t(unsigned long,
  42 +                                               hvs->max_core_rate,
  43 +                                               new_hvs_state->core_clock_rate);
  44 +
  45 +               drm_dbg(dev, "Running the core clock at %lu Hz\n", core_rate);
  46
  47                 /*
  48                  * Request a clock rate based on the current HVS
  49                  * requirements.
  50                  */
  51 -               WARN_ON(clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate));
  52 +               WARN_ON(clk_set_min_rate(hvs->core_clk, core_rate));
  53
  54                 drm_dbg(dev, "Core clock actual rate: %lu Hz\n",
  55                         clk_get_rate(hvs->core_clk));