1 From 518d779810c0e4185f2d8a71fc112232df5be62e Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Mon, 16 Dec 2019 15:09:49 +0200
4 Subject: [PATCH] net: mscc: ocelot: export ANA, DEV and QSYS registers to
7 Since the Felix DSA driver is implementing its own PHYLINK instance due
8 to SoC differences, it needs access to the few registers that are
9 common, mainly for flow control.
11 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
14 drivers/net/ethernet/mscc/ocelot_tsn.c
16 which has been added in downstream patch b5c05e3404a5 ("net: mscc:
17 ocelot: tsn configuration support") and also needs to be adapted to the
18 new location of the header files.
20 drivers/net/ethernet/mscc/ocelot.h | 6 +-
21 drivers/net/ethernet/mscc/ocelot_ana.h | 642 --------------------------------
22 drivers/net/ethernet/mscc/ocelot_dev.h | 275 --------------
23 drivers/net/ethernet/mscc/ocelot_qsys.h | 270 --------------
24 drivers/net/ethernet/mscc/ocelot_tsn.c | 4 +-
25 include/soc/mscc/ocelot_ana.h | 642 ++++++++++++++++++++++++++++++++
26 include/soc/mscc/ocelot_dev.h | 275 ++++++++++++++
27 include/soc/mscc/ocelot_qsys.h | 270 ++++++++++++++
28 8 files changed, 1192 insertions(+), 1192 deletions(-)
29 delete mode 100644 drivers/net/ethernet/mscc/ocelot_ana.h
30 delete mode 100644 drivers/net/ethernet/mscc/ocelot_dev.h
31 delete mode 100644 drivers/net/ethernet/mscc/ocelot_qsys.h
32 create mode 100644 include/soc/mscc/ocelot_ana.h
33 create mode 100644 include/soc/mscc/ocelot_dev.h
34 create mode 100644 include/soc/mscc/ocelot_qsys.h
36 --- a/drivers/net/ethernet/mscc/ocelot.h
37 +++ b/drivers/net/ethernet/mscc/ocelot.h
39 #include <linux/ptp_clock_kernel.h>
40 #include <linux/regmap.h>
42 +#include <soc/mscc/ocelot_qsys.h>
43 #include <soc/mscc/ocelot_sys.h>
44 +#include <soc/mscc/ocelot_dev.h>
45 +#include <soc/mscc/ocelot_ana.h>
46 #include <soc/mscc/ocelot.h>
47 -#include "ocelot_ana.h"
48 -#include "ocelot_dev.h"
49 -#include "ocelot_qsys.h"
50 #include "ocelot_rew.h"
51 #include "ocelot_qs.h"
52 #include "ocelot_tc.h"
53 --- a/drivers/net/ethernet/mscc/ocelot_ana.h
56 -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
58 - * Microsemi Ocelot Switch driver
60 - * Copyright (c) 2017 Microsemi Corporation
63 -#ifndef _MSCC_OCELOT_ANA_H_
64 -#define _MSCC_OCELOT_ANA_H_
66 -#define ANA_ANAGEFIL_B_DOM_EN BIT(22)
67 -#define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
68 -#define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
69 -#define ANA_ANAGEFIL_PID_EN BIT(19)
70 -#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
71 -#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
72 -#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
73 -#define ANA_ANAGEFIL_VID_EN BIT(13)
74 -#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
75 -#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
77 -#define ANA_STORMLIMIT_CFG_RSZ 0x4
79 -#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
80 -#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
81 -#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
82 -#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
83 -#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
84 -#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
86 -#define ANA_AUTOAGE_AGE_FAST BIT(21)
87 -#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
88 -#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
89 -#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
90 -#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
92 -#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
93 -#define ANA_MACTOPTIONS_SHADOW BIT(0)
95 -#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
96 -#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
97 -#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
98 -#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
99 -#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
100 -#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
101 -#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
102 -#define ANA_AGENCTRL_MIRROR_CPU BIT(7)
103 -#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
104 -#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
105 -#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
106 -#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
107 -#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
108 -#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
109 -#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
111 -#define ANA_FLOODING_RSZ 0x4
113 -#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
114 -#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
115 -#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
116 -#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
117 -#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
118 -#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
119 -#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
120 -#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
122 -#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
123 -#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
124 -#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
125 -#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
126 -#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
127 -#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
128 -#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
129 -#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
130 -#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
131 -#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
132 -#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
134 -#define ANA_SFLOW_CFG_RSZ 0x4
136 -#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
137 -#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
138 -#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
139 -#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
140 -#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
142 -#define ANA_PORT_MODE_RSZ 0x4
144 -#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
145 -#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
146 -#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
147 -#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
148 -#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
150 -#define ANA_CUT_THRU_CFG_RSZ 0x4
152 -#define ANA_PGID_PGID_RSZ 0x4
154 -#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
155 -#define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
156 -#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
157 -#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
158 -#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
160 -#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
161 -#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
162 -#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
163 -#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
164 -#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
166 -#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
167 -#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
168 -#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
169 -#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
170 -#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
171 -#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
172 -#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
174 -#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
175 -#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
176 -#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
177 -#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
178 -#define ANA_TABLES_MACACCESS_VALID BIT(11)
179 -#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
180 -#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
181 -#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
182 -#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
183 -#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
184 -#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
185 -#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
186 -#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
187 -#define MACACCESS_CMD_IDLE 0
188 -#define MACACCESS_CMD_LEARN 1
189 -#define MACACCESS_CMD_FORGET 2
190 -#define MACACCESS_CMD_AGE 3
191 -#define MACACCESS_CMD_GET_NEXT 4
192 -#define MACACCESS_CMD_INIT 5
193 -#define MACACCESS_CMD_READ 6
194 -#define MACACCESS_CMD_WRITE 7
196 -#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
197 -#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
198 -#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
199 -#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
200 -#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
201 -#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
202 -#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
203 -#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
205 -#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
206 -#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
207 -#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
208 -#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
209 -#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
210 -#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
211 -#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
212 -#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
214 -#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
215 -#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
216 -#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
217 -#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
218 -#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
220 -#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
221 -#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
222 -#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
223 -#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
224 -#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
225 -#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
226 -#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
227 -#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
228 -#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
229 -#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
231 -#define ANA_TABLES_ENTRYLIM_RSZ 0x4
233 -#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
234 -#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
235 -#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
236 -#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
237 -#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
239 -#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
240 -#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
241 -#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
242 -#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
243 -#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
244 -#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
245 -#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
247 -#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
248 -#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
249 -#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
250 -#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
251 -#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
252 -#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
253 -#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
254 -#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
255 -#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
256 -#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
257 -#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
258 -#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
259 -#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
260 -#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
261 -#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
263 -#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
264 -#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
265 -#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
266 -#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
267 -#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
269 -#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
270 -#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
271 -#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
272 -#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
274 -#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
275 -#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
276 -#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
277 -#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
278 -#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
279 -#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
280 -#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
281 -#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
282 -#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
283 -#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
285 -#define SFIDACCESS_CMD_IDLE 0
286 -#define SFIDACCESS_CMD_READ 1
287 -#define SFIDACCESS_CMD_WRITE 2
288 -#define SFIDACCESS_CMD_INIT 3
290 -#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
291 -#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
292 -#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
293 -#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
294 -#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
295 -#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
296 -#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
297 -#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
298 -#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
299 -#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
301 -#define ANA_MSTI_STATE_RSZ 0x4
303 -#define ANA_OAM_UPM_LM_CNT_RSZ 0x4
305 -#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
306 -#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
307 -#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
309 -#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
310 -#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
311 -#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
312 -#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
313 -#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
314 -#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
315 -#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
316 -#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
317 -#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
318 -#define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24)
319 -#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24))
320 -#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21))
321 -#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21)
322 -#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21)
323 -#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
325 -#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
327 -#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
328 -#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
329 -#define ANA_SG_GCL_GS_CONFIG_IPV_VALID BIT(3)
330 -#define ANA_SG_GCL_GS_CONFIG_IPV(x) ((x) & GENMASK(2, 0))
331 -#define ANA_SG_GCL_GS_CONFIG_IPV_M GENMASK(2, 0)
332 -#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
334 -#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
336 -#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
337 -#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
338 -#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
339 -#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
340 -#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
341 -#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
342 -#define ANA_SG_STATUS_REG_3_IPV_VALID BIT(23)
343 -#define ANA_SG_STATUS_REG_3_IPV(x) (((x) << 20) & GENMASK(22, 20))
344 -#define ANA_SG_STATUS_REG_3_IPV_M GENMASK(22, 20)
345 -#define ANA_SG_STATUS_REG_3_IPV_X(x) (((x) & GENMASK(22, 20)) >> 20)
346 -#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
348 -#define ANA_PORT_VLAN_CFG_GSZ 0x100
350 -#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
351 -#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
352 -#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
353 -#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
354 -#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
355 -#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
356 -#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
357 -#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
358 -#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
359 -#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
360 -#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
361 -#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
362 -#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
364 -#define ANA_PORT_DROP_CFG_GSZ 0x100
366 -#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
367 -#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
368 -#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
369 -#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
370 -#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
371 -#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
372 -#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
374 -#define ANA_PORT_QOS_CFG_GSZ 0x100
376 -#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
377 -#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
378 -#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
379 -#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
380 -#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
381 -#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
382 -#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
383 -#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
384 -#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
386 -#define ANA_PORT_VCAP_CFG_GSZ 0x100
388 -#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
389 -#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
390 -#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
391 -#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
392 -#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
393 -#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
394 -#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
395 -#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
396 -#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
398 -#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
399 -#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
401 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
402 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
403 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
404 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
405 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
406 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
407 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
408 -#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
410 -#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
412 -#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
413 -#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
414 -#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
415 -#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
416 -#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
417 -#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
418 -#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
419 -#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
420 -#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
421 -#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
422 -#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
423 -#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
424 -#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
425 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
426 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
427 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
428 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
429 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
430 -#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
431 -#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
432 -#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
433 -#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
434 -#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
435 -#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
437 -#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
438 -#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
440 -#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
441 -#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
442 -#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
444 -#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
446 -#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
447 -#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
448 -#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
449 -#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
450 -#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
451 -#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
452 -#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
453 -#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
455 -#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
457 -#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
458 -#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
459 -#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
460 -#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
461 -#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
463 -#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
465 -#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
466 -#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
467 -#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
468 -#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
469 -#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
471 -#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
473 -#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
474 -#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
475 -#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
476 -#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
477 -#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
479 -#define ANA_PORT_PORT_CFG_GSZ 0x100
481 -#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
482 -#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
483 -#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
484 -#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
485 -#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
486 -#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
487 -#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
488 -#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
489 -#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
490 -#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
491 -#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
492 -#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
493 -#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
494 -#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
495 -#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
497 -#define ANA_PORT_POL_CFG_GSZ 0x100
499 -#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
500 -#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
501 -#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
502 -#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
503 -#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
504 -#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
505 -#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
506 -#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
508 -#define ANA_PORT_PTP_CFG_GSZ 0x100
510 -#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
512 -#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
514 -#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
516 -#define ANA_PORT_SFID_CFG_GSZ 0x100
517 -#define ANA_PORT_SFID_CFG_RSZ 0x4
519 -#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
520 -#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
521 -#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
523 -#define ANA_PFC_PFC_CFG_GSZ 0x40
525 -#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
526 -#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
527 -#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
528 -#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
529 -#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
531 -#define ANA_PFC_PFC_TIMER_GSZ 0x40
532 -#define ANA_PFC_PFC_TIMER_RSZ 0x4
534 -#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
536 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
537 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
538 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
539 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
540 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
541 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
542 -#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
544 -#define ANA_IPT_IPT_GSZ 0x8
546 -#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
547 -#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
548 -#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
549 -#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
550 -#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
551 -#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
552 -#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
553 -#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
555 -#define ANA_PPT_PPT_RSZ 0x4
557 -#define ANA_FID_MAP_FID_MAP_RSZ 0x4
559 -#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
560 -#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
561 -#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
562 -#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
563 -#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
565 -#define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
566 -#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
567 -#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
568 -#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
569 -#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
570 -#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
571 -#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
572 -#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
574 -#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
575 -#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
576 -#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
577 -#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
578 -#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
579 -#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
580 -#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
581 -#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
582 -#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
583 -#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
584 -#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
585 -#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
586 -#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
587 -#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
588 -#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
589 -#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
590 -#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
591 -#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
592 -#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
593 -#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
594 -#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
595 -#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
596 -#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
597 -#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
598 -#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
599 -#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
600 -#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
601 -#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
602 -#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
604 -#define ANA_CPUQ_8021_CFG_RSZ 0x4
606 -#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
607 -#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
608 -#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
609 -#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
610 -#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
611 -#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
612 -#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
613 -#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
615 -#define ANA_DSCP_CFG_RSZ 0x4
617 -#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
618 -#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
619 -#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
620 -#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
621 -#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
622 -#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
623 -#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
624 -#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
625 -#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
627 -#define ANA_DSCP_REWR_CFG_RSZ 0x4
629 -#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
631 -#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
633 -#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
634 -#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
635 -#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
636 -#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
637 -#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
639 -#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
640 -#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
641 -#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
643 -#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
644 -#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
645 -#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
646 -#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
648 -#define ANA_FID_CFG_VID_MC_ENA BIT(0)
650 -#define ANA_POL_PIR_CFG_GSZ 0x20
652 -#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
653 -#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
654 -#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
655 -#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
656 -#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
658 -#define ANA_POL_CIR_CFG_GSZ 0x20
660 -#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
661 -#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
662 -#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
663 -#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
664 -#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
666 -#define ANA_POL_MODE_CFG_GSZ 0x20
668 -#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
669 -#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
670 -#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
671 -#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
672 -#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
673 -#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
674 -#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
675 -#define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
676 -#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
678 -#define ANA_POL_PIR_STATE_GSZ 0x20
680 -#define ANA_POL_CIR_STATE_GSZ 0x20
682 -#define ANA_POL_STATE_GSZ 0x20
684 -#define ANA_POL_FLOWC_RSZ 0x4
686 -#define ANA_POL_FLOWC_POL_FLOWC BIT(0)
688 -#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
689 -#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
690 -#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
691 -#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
692 -#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
694 -#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
695 -#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
698 --- a/drivers/net/ethernet/mscc/ocelot_dev.h
701 -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
703 - * Microsemi Ocelot Switch driver
705 - * Copyright (c) 2017 Microsemi Corporation
708 -#ifndef _MSCC_OCELOT_DEV_H_
709 -#define _MSCC_OCELOT_DEV_H_
711 -#define DEV_CLOCK_CFG 0x0
713 -#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
714 -#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
715 -#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
716 -#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
717 -#define DEV_CLOCK_CFG_PORT_RST BIT(3)
718 -#define DEV_CLOCK_CFG_PHY_RST BIT(2)
719 -#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
720 -#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
722 -#define DEV_PORT_MISC 0x4
724 -#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
725 -#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
726 -#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
727 -#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
728 -#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
730 -#define DEV_EVENTS 0x8
732 -#define DEV_EEE_CFG 0xc
734 -#define DEV_EEE_CFG_EEE_ENA BIT(22)
735 -#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
736 -#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
737 -#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
738 -#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
739 -#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
740 -#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
741 -#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
742 -#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
743 -#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
744 -#define DEV_EEE_CFG_PORT_LPI BIT(0)
746 -#define DEV_RX_PATH_DELAY 0x10
748 -#define DEV_TX_PATH_DELAY 0x14
750 -#define DEV_PTP_PREDICT_CFG 0x18
752 -#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
753 -#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
754 -#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
755 -#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
756 -#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
758 -#define DEV_MAC_ENA_CFG 0x1c
760 -#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
761 -#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
763 -#define DEV_MAC_MODE_CFG 0x20
765 -#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
766 -#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
767 -#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
769 -#define DEV_MAC_MAXLEN_CFG 0x24
771 -#define DEV_MAC_TAGS_CFG 0x28
773 -#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
774 -#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
775 -#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
776 -#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
777 -#define DEV_MAC_TAGS_CFG_PB_ENA BIT(1)
778 -#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
780 -#define DEV_MAC_ADV_CHK_CFG 0x2c
782 -#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
784 -#define DEV_MAC_IFG_CFG 0x30
786 -#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
787 -#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
788 -#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
789 -#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
790 -#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
791 -#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
792 -#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
793 -#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
794 -#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
795 -#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
797 -#define DEV_MAC_HDX_CFG 0x34
799 -#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
800 -#define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
801 -#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
802 -#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
803 -#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
804 -#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
805 -#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
806 -#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
807 -#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
808 -#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
810 -#define DEV_MAC_DBG_CFG 0x38
812 -#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
813 -#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
815 -#define DEV_MAC_FC_MAC_LOW_CFG 0x3c
817 -#define DEV_MAC_FC_MAC_HIGH_CFG 0x40
819 -#define DEV_MAC_STICKY 0x44
821 -#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
822 -#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
823 -#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
824 -#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
825 -#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
826 -#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
827 -#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
828 -#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
829 -#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
830 -#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
832 -#define PCS1G_CFG 0x48
834 -#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
835 -#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
836 -#define PCS1G_CFG_PCS_ENA BIT(0)
838 -#define PCS1G_MODE_CFG 0x4c
840 -#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
841 -#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
843 -#define PCS1G_SD_CFG 0x50
845 -#define PCS1G_SD_CFG_SD_SEL BIT(8)
846 -#define PCS1G_SD_CFG_SD_POL BIT(4)
847 -#define PCS1G_SD_CFG_SD_ENA BIT(0)
849 -#define PCS1G_ANEG_CFG 0x54
851 -#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
852 -#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
853 -#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
854 -#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
855 -#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
856 -#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
858 -#define PCS1G_ANEG_NP_CFG 0x58
860 -#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
861 -#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
862 -#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
863 -#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
865 -#define PCS1G_LB_CFG 0x5c
867 -#define PCS1G_LB_CFG_RA_ENA BIT(4)
868 -#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
869 -#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
871 -#define PCS1G_DBG_CFG 0x60
873 -#define PCS1G_DBG_CFG_UDLT BIT(0)
875 -#define PCS1G_CDET_CFG 0x64
877 -#define PCS1G_CDET_CFG_CDET_ENA BIT(0)
879 -#define PCS1G_ANEG_STATUS 0x68
881 -#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
882 -#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
883 -#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
884 -#define PCS1G_ANEG_STATUS_PR BIT(4)
885 -#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
886 -#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
888 -#define PCS1G_ANEG_NP_STATUS 0x6c
890 -#define PCS1G_LINK_STATUS 0x70
892 -#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
893 -#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
894 -#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
895 -#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
896 -#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
897 -#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
899 -#define PCS1G_LINK_DOWN_CNT 0x74
901 -#define PCS1G_STICKY 0x78
903 -#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
904 -#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
906 -#define PCS1G_DEBUG_STATUS 0x7c
908 -#define PCS1G_LPI_CFG 0x80
910 -#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
911 -#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
912 -#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
913 -#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
914 -#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
915 -#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
916 -#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
918 -#define PCS1G_LPI_WAKE_ERROR_CNT 0x84
920 -#define PCS1G_LPI_STATUS 0x88
922 -#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
923 -#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
924 -#define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
925 -#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
926 -#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
927 -#define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
928 -#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
930 -#define PCS1G_TSTPAT_MODE_CFG 0x8c
932 -#define PCS1G_TSTPAT_STATUS 0x90
934 -#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
935 -#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
936 -#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
937 -#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
938 -#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
940 -#define DEV_PCS_FX100_CFG 0x94
942 -#define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
943 -#define DEV_PCS_FX100_CFG_SD_POL BIT(25)
944 -#define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
945 -#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
946 -#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
947 -#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
948 -#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
949 -#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
950 -#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
951 -#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
952 -#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
953 -#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
954 -#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
955 -#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
956 -#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
957 -#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
958 -#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
959 -#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
960 -#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
962 -#define DEV_PCS_FX100_STATUS 0x98
964 -#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
965 -#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
966 -#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
967 -#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
968 -#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
969 -#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
970 -#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
971 -#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
972 -#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
973 -#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
976 --- a/drivers/net/ethernet/mscc/ocelot_qsys.h
979 -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
981 - * Microsemi Ocelot Switch driver
983 - * Copyright (c) 2017 Microsemi Corporation
986 -#ifndef _MSCC_OCELOT_QSYS_H_
987 -#define _MSCC_OCELOT_QSYS_H_
989 -#define QSYS_PORT_MODE_RSZ 0x4
991 -#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
992 -#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
994 -#define QSYS_SWITCH_PORT_MODE_RSZ 0x4
996 -#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
997 -#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
998 -#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
999 -#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
1000 -#define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10)
1001 -#define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9)
1002 -#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
1003 -#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
1004 -#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
1005 -#define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0)
1007 -#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
1008 -#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
1009 -#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
1010 -#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
1011 -#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
1012 -#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
1014 -#define QSYS_EEE_CFG_RSZ 0x4
1016 -#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
1017 -#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
1018 -#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
1019 -#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
1020 -#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
1022 -#define QSYS_SW_STATUS_RSZ 0x4
1024 -#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
1025 -#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
1026 -#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
1027 -#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
1028 -#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
1030 -#define QSYS_QMAP_GSZ 0x4
1032 -#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
1033 -#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
1034 -#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
1035 -#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
1036 -#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
1037 -#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
1038 -#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
1039 -#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
1041 -#define QSYS_ISDX_SGRP_GSZ 0x4
1043 -#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
1045 -#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
1046 -#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
1047 -#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
1048 -#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
1049 -#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
1050 -#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
1051 -#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
1053 -#define QSYS_RED_PROFILE_RSZ 0x4
1055 -#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
1056 -#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
1057 -#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
1058 -#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
1059 -#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
1061 -#define QSYS_RES_CFG_GSZ 0x8
1063 -#define QSYS_RES_STAT_GSZ 0x8
1065 -#define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12))
1066 -#define QSYS_RES_STAT_INUSE_M GENMASK(23, 12)
1067 -#define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12)
1068 -#define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0))
1069 -#define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0)
1071 -#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
1072 -#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
1073 -#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
1074 -#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
1075 -#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
1077 -#define QSYS_QMAXSDU_CFG_0_RSZ 0x4
1079 -#define QSYS_QMAXSDU_CFG_1_RSZ 0x4
1081 -#define QSYS_QMAXSDU_CFG_2_RSZ 0x4
1083 -#define QSYS_QMAXSDU_CFG_3_RSZ 0x4
1085 -#define QSYS_QMAXSDU_CFG_4_RSZ 0x4
1087 -#define QSYS_QMAXSDU_CFG_5_RSZ 0x4
1089 -#define QSYS_QMAXSDU_CFG_6_RSZ 0x4
1091 -#define QSYS_QMAXSDU_CFG_7_RSZ 0x4
1093 -#define QSYS_PREEMPTION_CFG_RSZ 0x4
1095 -#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
1096 -#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
1097 -#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
1098 -#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
1099 -#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
1100 -#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
1101 -#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
1102 -#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
1103 -#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
1104 -#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
1105 -#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
1107 -#define QSYS_CIR_CFG_GSZ 0x80
1109 -#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
1110 -#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
1111 -#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
1112 -#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
1113 -#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
1115 -#define QSYS_EIR_CFG_GSZ 0x80
1117 -#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
1118 -#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
1119 -#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
1120 -#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
1121 -#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
1122 -#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
1123 -#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
1125 -#define QSYS_SE_CFG_GSZ 0x80
1127 -#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
1128 -#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
1129 -#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
1130 -#define QSYS_SE_CFG_SE_RR_ENA BIT(5)
1131 -#define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
1132 -#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
1133 -#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
1134 -#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
1135 -#define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
1136 -#define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
1138 -#define QSYS_SE_DWRR_CFG_GSZ 0x80
1139 -#define QSYS_SE_DWRR_CFG_RSZ 0x4
1141 -#define QSYS_SE_CONNECT_GSZ 0x80
1143 -#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
1144 -#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
1145 -#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
1146 -#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
1147 -#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
1148 -#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
1149 -#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
1150 -#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
1151 -#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
1152 -#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
1153 -#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
1154 -#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
1155 -#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
1157 -#define QSYS_SE_DLB_SENSE_GSZ 0x80
1159 -#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
1160 -#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
1161 -#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
1162 -#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
1163 -#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
1164 -#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
1165 -#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
1166 -#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
1167 -#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
1168 -#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
1169 -#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
1170 -#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
1172 -#define QSYS_CIR_STATE_GSZ 0x80
1174 -#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
1175 -#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
1176 -#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
1177 -#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
1178 -#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
1180 -#define QSYS_EIR_STATE_GSZ 0x80
1182 -#define QSYS_SE_STATE_GSZ 0x80
1184 -#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
1185 -#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
1186 -#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
1187 -#define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
1189 -#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
1190 -#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
1191 -#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
1192 -#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
1193 -#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
1194 -#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
1195 -#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
1197 -#define QSYS_TAG_CONFIG_RSZ 0x4
1199 -#define QSYS_TAG_CONFIG_ENABLE BIT(0)
1200 -#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
1201 -#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
1202 -#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
1203 -#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
1204 -#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
1205 -#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
1206 -#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
1207 -#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
1208 -#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
1210 -#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
1211 -#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
1212 -#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
1213 -#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
1215 -#define QSYS_PORT_MAX_SDU_RSZ 0x4
1217 -#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
1218 -#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
1219 -#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
1220 -#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
1221 -#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
1223 -#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
1224 -#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
1225 -#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
1226 -#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
1227 -#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
1229 -#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
1230 -#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
1231 -#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
1232 -#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
1233 -#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
1235 -#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
1236 -#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
1237 -#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
1238 -#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
1239 -#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
1240 -#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
1242 -#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
1243 -#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
1244 -#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
1245 -#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
1246 -#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
1249 --- a/drivers/net/ethernet/mscc/ocelot_tsn.c
1250 +++ b/drivers/net/ethernet/mscc/ocelot_tsn.c
1252 #include <linux/iopoll.h>
1254 #include <soc/mscc/ocelot_sys.h>
1255 -#include "ocelot_ana.h"
1256 -#include "ocelot_qsys.h"
1257 +#include <soc/mscc/ocelot_ana.h>
1258 +#include <soc/mscc/ocelot_qsys.h>
1259 #include "ocelot_rew.h"
1260 #include "ocelot_dev_gmii.h"
1261 #include "ocelot_tsn.h"
1263 +++ b/include/soc/mscc/ocelot_ana.h
1265 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
1267 + * Microsemi Ocelot Switch driver
1269 + * Copyright (c) 2017 Microsemi Corporation
1272 +#ifndef _MSCC_OCELOT_ANA_H_
1273 +#define _MSCC_OCELOT_ANA_H_
1275 +#define ANA_ANAGEFIL_B_DOM_EN BIT(22)
1276 +#define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
1277 +#define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
1278 +#define ANA_ANAGEFIL_PID_EN BIT(19)
1279 +#define ANA_ANAGEFIL_PID_VAL(x) (((x) << 14) & GENMASK(18, 14))
1280 +#define ANA_ANAGEFIL_PID_VAL_M GENMASK(18, 14)
1281 +#define ANA_ANAGEFIL_PID_VAL_X(x) (((x) & GENMASK(18, 14)) >> 14)
1282 +#define ANA_ANAGEFIL_VID_EN BIT(13)
1283 +#define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
1284 +#define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
1286 +#define ANA_STORMLIMIT_CFG_RSZ 0x4
1288 +#define ANA_STORMLIMIT_CFG_STORM_RATE(x) (((x) << 3) & GENMASK(6, 3))
1289 +#define ANA_STORMLIMIT_CFG_STORM_RATE_M GENMASK(6, 3)
1290 +#define ANA_STORMLIMIT_CFG_STORM_RATE_X(x) (((x) & GENMASK(6, 3)) >> 3)
1291 +#define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
1292 +#define ANA_STORMLIMIT_CFG_STORM_MODE(x) ((x) & GENMASK(1, 0))
1293 +#define ANA_STORMLIMIT_CFG_STORM_MODE_M GENMASK(1, 0)
1295 +#define ANA_AUTOAGE_AGE_FAST BIT(21)
1296 +#define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
1297 +#define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
1298 +#define ANA_AUTOAGE_AGE_PERIOD_X(x) (((x) & GENMASK(20, 1)) >> 1)
1299 +#define ANA_AUTOAGE_AUTOAGE_LOCKED BIT(0)
1301 +#define ANA_MACTOPTIONS_REDUCED_TABLE BIT(1)
1302 +#define ANA_MACTOPTIONS_SHADOW BIT(0)
1304 +#define ANA_AGENCTRL_FID_MASK(x) (((x) << 12) & GENMASK(23, 12))
1305 +#define ANA_AGENCTRL_FID_MASK_M GENMASK(23, 12)
1306 +#define ANA_AGENCTRL_FID_MASK_X(x) (((x) & GENMASK(23, 12)) >> 12)
1307 +#define ANA_AGENCTRL_IGNORE_DMAC_FLAGS BIT(11)
1308 +#define ANA_AGENCTRL_IGNORE_SMAC_FLAGS BIT(10)
1309 +#define ANA_AGENCTRL_FLOOD_SPECIAL BIT(9)
1310 +#define ANA_AGENCTRL_FLOOD_IGNORE_VLAN BIT(8)
1311 +#define ANA_AGENCTRL_MIRROR_CPU BIT(7)
1312 +#define ANA_AGENCTRL_LEARN_CPU_COPY BIT(6)
1313 +#define ANA_AGENCTRL_LEARN_FWD_KILL BIT(5)
1314 +#define ANA_AGENCTRL_LEARN_IGNORE_VLAN BIT(4)
1315 +#define ANA_AGENCTRL_CPU_CPU_KILL_ENA BIT(3)
1316 +#define ANA_AGENCTRL_GREEN_COUNT_MODE BIT(2)
1317 +#define ANA_AGENCTRL_YELLOW_COUNT_MODE BIT(1)
1318 +#define ANA_AGENCTRL_RED_COUNT_MODE BIT(0)
1320 +#define ANA_FLOODING_RSZ 0x4
1322 +#define ANA_FLOODING_FLD_UNICAST(x) (((x) << 12) & GENMASK(17, 12))
1323 +#define ANA_FLOODING_FLD_UNICAST_M GENMASK(17, 12)
1324 +#define ANA_FLOODING_FLD_UNICAST_X(x) (((x) & GENMASK(17, 12)) >> 12)
1325 +#define ANA_FLOODING_FLD_BROADCAST(x) (((x) << 6) & GENMASK(11, 6))
1326 +#define ANA_FLOODING_FLD_BROADCAST_M GENMASK(11, 6)
1327 +#define ANA_FLOODING_FLD_BROADCAST_X(x) (((x) & GENMASK(11, 6)) >> 6)
1328 +#define ANA_FLOODING_FLD_MULTICAST(x) ((x) & GENMASK(5, 0))
1329 +#define ANA_FLOODING_FLD_MULTICAST_M GENMASK(5, 0)
1331 +#define ANA_FLOODING_IPMC_FLD_MC4_CTRL(x) (((x) << 18) & GENMASK(23, 18))
1332 +#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_M GENMASK(23, 18)
1333 +#define ANA_FLOODING_IPMC_FLD_MC4_CTRL_X(x) (((x) & GENMASK(23, 18)) >> 18)
1334 +#define ANA_FLOODING_IPMC_FLD_MC4_DATA(x) (((x) << 12) & GENMASK(17, 12))
1335 +#define ANA_FLOODING_IPMC_FLD_MC4_DATA_M GENMASK(17, 12)
1336 +#define ANA_FLOODING_IPMC_FLD_MC4_DATA_X(x) (((x) & GENMASK(17, 12)) >> 12)
1337 +#define ANA_FLOODING_IPMC_FLD_MC6_CTRL(x) (((x) << 6) & GENMASK(11, 6))
1338 +#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_M GENMASK(11, 6)
1339 +#define ANA_FLOODING_IPMC_FLD_MC6_CTRL_X(x) (((x) & GENMASK(11, 6)) >> 6)
1340 +#define ANA_FLOODING_IPMC_FLD_MC6_DATA(x) ((x) & GENMASK(5, 0))
1341 +#define ANA_FLOODING_IPMC_FLD_MC6_DATA_M GENMASK(5, 0)
1343 +#define ANA_SFLOW_CFG_RSZ 0x4
1345 +#define ANA_SFLOW_CFG_SF_RATE(x) (((x) << 2) & GENMASK(13, 2))
1346 +#define ANA_SFLOW_CFG_SF_RATE_M GENMASK(13, 2)
1347 +#define ANA_SFLOW_CFG_SF_RATE_X(x) (((x) & GENMASK(13, 2)) >> 2)
1348 +#define ANA_SFLOW_CFG_SF_SAMPLE_RX BIT(1)
1349 +#define ANA_SFLOW_CFG_SF_SAMPLE_TX BIT(0)
1351 +#define ANA_PORT_MODE_RSZ 0x4
1353 +#define ANA_PORT_MODE_REDTAG_PARSE_CFG BIT(3)
1354 +#define ANA_PORT_MODE_VLAN_PARSE_CFG(x) (((x) << 1) & GENMASK(2, 1))
1355 +#define ANA_PORT_MODE_VLAN_PARSE_CFG_M GENMASK(2, 1)
1356 +#define ANA_PORT_MODE_VLAN_PARSE_CFG_X(x) (((x) & GENMASK(2, 1)) >> 1)
1357 +#define ANA_PORT_MODE_L3_PARSE_CFG BIT(0)
1359 +#define ANA_CUT_THRU_CFG_RSZ 0x4
1361 +#define ANA_PGID_PGID_RSZ 0x4
1363 +#define ANA_PGID_PGID_PGID(x) ((x) & GENMASK(11, 0))
1364 +#define ANA_PGID_PGID_PGID_M GENMASK(11, 0)
1365 +#define ANA_PGID_PGID_CPUQ_DST_PGID(x) (((x) << 27) & GENMASK(29, 27))
1366 +#define ANA_PGID_PGID_CPUQ_DST_PGID_M GENMASK(29, 27)
1367 +#define ANA_PGID_PGID_CPUQ_DST_PGID_X(x) (((x) & GENMASK(29, 27)) >> 27)
1369 +#define ANA_TABLES_MACHDATA_VID(x) (((x) << 16) & GENMASK(28, 16))
1370 +#define ANA_TABLES_MACHDATA_VID_M GENMASK(28, 16)
1371 +#define ANA_TABLES_MACHDATA_VID_X(x) (((x) & GENMASK(28, 16)) >> 16)
1372 +#define ANA_TABLES_MACHDATA_MACHDATA(x) ((x) & GENMASK(15, 0))
1373 +#define ANA_TABLES_MACHDATA_MACHDATA_M GENMASK(15, 0)
1375 +#define ANA_TABLES_STREAMDATA_SSID_VALID BIT(16)
1376 +#define ANA_TABLES_STREAMDATA_SSID(x) (((x) << 9) & GENMASK(15, 9))
1377 +#define ANA_TABLES_STREAMDATA_SSID_M GENMASK(15, 9)
1378 +#define ANA_TABLES_STREAMDATA_SSID_X(x) (((x) & GENMASK(15, 9)) >> 9)
1379 +#define ANA_TABLES_STREAMDATA_SFID_VALID BIT(8)
1380 +#define ANA_TABLES_STREAMDATA_SFID(x) ((x) & GENMASK(7, 0))
1381 +#define ANA_TABLES_STREAMDATA_SFID_M GENMASK(7, 0)
1383 +#define ANA_TABLES_MACACCESS_MAC_CPU_COPY BIT(15)
1384 +#define ANA_TABLES_MACACCESS_SRC_KILL BIT(14)
1385 +#define ANA_TABLES_MACACCESS_IGNORE_VLAN BIT(13)
1386 +#define ANA_TABLES_MACACCESS_AGED_FLAG BIT(12)
1387 +#define ANA_TABLES_MACACCESS_VALID BIT(11)
1388 +#define ANA_TABLES_MACACCESS_ENTRYTYPE(x) (((x) << 9) & GENMASK(10, 9))
1389 +#define ANA_TABLES_MACACCESS_ENTRYTYPE_M GENMASK(10, 9)
1390 +#define ANA_TABLES_MACACCESS_ENTRYTYPE_X(x) (((x) & GENMASK(10, 9)) >> 9)
1391 +#define ANA_TABLES_MACACCESS_DEST_IDX(x) (((x) << 3) & GENMASK(8, 3))
1392 +#define ANA_TABLES_MACACCESS_DEST_IDX_M GENMASK(8, 3)
1393 +#define ANA_TABLES_MACACCESS_DEST_IDX_X(x) (((x) & GENMASK(8, 3)) >> 3)
1394 +#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) ((x) & GENMASK(2, 0))
1395 +#define ANA_TABLES_MACACCESS_MAC_TABLE_CMD_M GENMASK(2, 0)
1396 +#define MACACCESS_CMD_IDLE 0
1397 +#define MACACCESS_CMD_LEARN 1
1398 +#define MACACCESS_CMD_FORGET 2
1399 +#define MACACCESS_CMD_AGE 3
1400 +#define MACACCESS_CMD_GET_NEXT 4
1401 +#define MACACCESS_CMD_INIT 5
1402 +#define MACACCESS_CMD_READ 6
1403 +#define MACACCESS_CMD_WRITE 7
1405 +#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK(x) (((x) << 2) & GENMASK(13, 2))
1406 +#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_M GENMASK(13, 2)
1407 +#define ANA_TABLES_VLANACCESS_VLAN_PORT_MASK_X(x) (((x) & GENMASK(13, 2)) >> 2)
1408 +#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD(x) ((x) & GENMASK(1, 0))
1409 +#define ANA_TABLES_VLANACCESS_VLAN_TBL_CMD_M GENMASK(1, 0)
1410 +#define ANA_TABLES_VLANACCESS_CMD_IDLE 0x0
1411 +#define ANA_TABLES_VLANACCESS_CMD_WRITE 0x2
1412 +#define ANA_TABLES_VLANACCESS_CMD_INIT 0x3
1414 +#define ANA_TABLES_VLANTIDX_VLAN_SEC_FWD_ENA BIT(17)
1415 +#define ANA_TABLES_VLANTIDX_VLAN_FLOOD_DIS BIT(16)
1416 +#define ANA_TABLES_VLANTIDX_VLAN_PRIV_VLAN BIT(15)
1417 +#define ANA_TABLES_VLANTIDX_VLAN_LEARN_DISABLED BIT(14)
1418 +#define ANA_TABLES_VLANTIDX_VLAN_MIRROR BIT(13)
1419 +#define ANA_TABLES_VLANTIDX_VLAN_SRC_CHK BIT(12)
1420 +#define ANA_TABLES_VLANTIDX_V_INDEX(x) ((x) & GENMASK(11, 0))
1421 +#define ANA_TABLES_VLANTIDX_V_INDEX_M GENMASK(11, 0)
1423 +#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK(x) (((x) << 2) & GENMASK(8, 2))
1424 +#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_M GENMASK(8, 2)
1425 +#define ANA_TABLES_ISDXACCESS_ISDX_PORT_MASK_X(x) (((x) & GENMASK(8, 2)) >> 2)
1426 +#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD(x) ((x) & GENMASK(1, 0))
1427 +#define ANA_TABLES_ISDXACCESS_ISDX_TBL_CMD_M GENMASK(1, 0)
1429 +#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI(x) (((x) << 21) & GENMASK(28, 21))
1430 +#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_M GENMASK(28, 21)
1431 +#define ANA_TABLES_ISDXTIDX_ISDX_SDLBI_X(x) (((x) & GENMASK(28, 21)) >> 21)
1432 +#define ANA_TABLES_ISDXTIDX_ISDX_MSTI(x) (((x) << 15) & GENMASK(20, 15))
1433 +#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_M GENMASK(20, 15)
1434 +#define ANA_TABLES_ISDXTIDX_ISDX_MSTI_X(x) (((x) & GENMASK(20, 15)) >> 15)
1435 +#define ANA_TABLES_ISDXTIDX_ISDX_ES0_KEY_ENA BIT(14)
1436 +#define ANA_TABLES_ISDXTIDX_ISDX_FORCE_ENA BIT(10)
1437 +#define ANA_TABLES_ISDXTIDX_ISDX_INDEX(x) ((x) & GENMASK(7, 0))
1438 +#define ANA_TABLES_ISDXTIDX_ISDX_INDEX_M GENMASK(7, 0)
1440 +#define ANA_TABLES_ENTRYLIM_RSZ 0x4
1442 +#define ANA_TABLES_ENTRYLIM_ENTRYLIM(x) (((x) << 14) & GENMASK(17, 14))
1443 +#define ANA_TABLES_ENTRYLIM_ENTRYLIM_M GENMASK(17, 14)
1444 +#define ANA_TABLES_ENTRYLIM_ENTRYLIM_X(x) (((x) & GENMASK(17, 14)) >> 14)
1445 +#define ANA_TABLES_ENTRYLIM_ENTRYSTAT(x) ((x) & GENMASK(13, 0))
1446 +#define ANA_TABLES_ENTRYLIM_ENTRYSTAT_M GENMASK(13, 0)
1448 +#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM(x) (((x) << 4) & GENMASK(31, 4))
1449 +#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_M GENMASK(31, 4)
1450 +#define ANA_TABLES_STREAMACCESS_GEN_REC_SEQ_NUM_X(x) (((x) & GENMASK(31, 4)) >> 4)
1451 +#define ANA_TABLES_STREAMACCESS_SEQ_GEN_REC_ENA BIT(3)
1452 +#define ANA_TABLES_STREAMACCESS_GEN_REC_TYPE BIT(2)
1453 +#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD(x) ((x) & GENMASK(1, 0))
1454 +#define ANA_TABLES_STREAMACCESS_STREAM_TBL_CMD_M GENMASK(1, 0)
1456 +#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS(x) (((x) << 30) & GENMASK(31, 30))
1457 +#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_M GENMASK(31, 30)
1458 +#define ANA_TABLES_STREAMTIDX_SEQ_GEN_ERR_STATUS_X(x) (((x) & GENMASK(31, 30)) >> 30)
1459 +#define ANA_TABLES_STREAMTIDX_S_INDEX(x) (((x) << 16) & GENMASK(22, 16))
1460 +#define ANA_TABLES_STREAMTIDX_S_INDEX_M GENMASK(22, 16)
1461 +#define ANA_TABLES_STREAMTIDX_S_INDEX_X(x) (((x) & GENMASK(22, 16)) >> 16)
1462 +#define ANA_TABLES_STREAMTIDX_FORCE_SF_BEHAVIOUR BIT(14)
1463 +#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN(x) (((x) << 8) & GENMASK(13, 8))
1464 +#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_M GENMASK(13, 8)
1465 +#define ANA_TABLES_STREAMTIDX_SEQ_HISTORY_LEN_X(x) (((x) & GENMASK(13, 8)) >> 8)
1466 +#define ANA_TABLES_STREAMTIDX_RESET_ON_ROGUE BIT(7)
1467 +#define ANA_TABLES_STREAMTIDX_REDTAG_POP BIT(6)
1468 +#define ANA_TABLES_STREAMTIDX_STREAM_SPLIT BIT(5)
1469 +#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2(x) ((x) & GENMASK(4, 0))
1470 +#define ANA_TABLES_STREAMTIDX_SEQ_SPACE_LOG2_M GENMASK(4, 0)
1472 +#define ANA_TABLES_SEQ_MASK_SPLIT_MASK(x) (((x) << 16) & GENMASK(22, 16))
1473 +#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_M GENMASK(22, 16)
1474 +#define ANA_TABLES_SEQ_MASK_SPLIT_MASK_X(x) (((x) & GENMASK(22, 16)) >> 16)
1475 +#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK(x) ((x) & GENMASK(6, 0))
1476 +#define ANA_TABLES_SEQ_MASK_INPUT_PORT_MASK_M GENMASK(6, 0)
1478 +#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK(x) (((x) << 1) & GENMASK(7, 1))
1479 +#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_M GENMASK(7, 1)
1480 +#define ANA_TABLES_SFID_MASK_IGR_PORT_MASK_X(x) (((x) & GENMASK(7, 1)) >> 1)
1481 +#define ANA_TABLES_SFID_MASK_IGR_SRCPORT_MATCH_ENA BIT(0)
1483 +#define ANA_TABLES_SFIDACCESS_IGR_PRIO_MATCH_ENA BIT(22)
1484 +#define ANA_TABLES_SFIDACCESS_IGR_PRIO(x) (((x) << 19) & GENMASK(21, 19))
1485 +#define ANA_TABLES_SFIDACCESS_IGR_PRIO_M GENMASK(21, 19)
1486 +#define ANA_TABLES_SFIDACCESS_IGR_PRIO_X(x) (((x) & GENMASK(21, 19)) >> 19)
1487 +#define ANA_TABLES_SFIDACCESS_FORCE_BLOCK BIT(18)
1488 +#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN(x) (((x) << 2) & GENMASK(17, 2))
1489 +#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_M GENMASK(17, 2)
1490 +#define ANA_TABLES_SFIDACCESS_MAX_SDU_LEN_X(x) (((x) & GENMASK(17, 2)) >> 2)
1491 +#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD(x) ((x) & GENMASK(1, 0))
1492 +#define ANA_TABLES_SFIDACCESS_SFID_TBL_CMD_M GENMASK(1, 0)
1494 +#define SFIDACCESS_CMD_IDLE 0
1495 +#define SFIDACCESS_CMD_READ 1
1496 +#define SFIDACCESS_CMD_WRITE 2
1497 +#define SFIDACCESS_CMD_INIT 3
1499 +#define ANA_TABLES_SFIDTIDX_SGID_VALID BIT(26)
1500 +#define ANA_TABLES_SFIDTIDX_SGID(x) (((x) << 18) & GENMASK(25, 18))
1501 +#define ANA_TABLES_SFIDTIDX_SGID_M GENMASK(25, 18)
1502 +#define ANA_TABLES_SFIDTIDX_SGID_X(x) (((x) & GENMASK(25, 18)) >> 18)
1503 +#define ANA_TABLES_SFIDTIDX_POL_ENA BIT(17)
1504 +#define ANA_TABLES_SFIDTIDX_POL_IDX(x) (((x) << 8) & GENMASK(16, 8))
1505 +#define ANA_TABLES_SFIDTIDX_POL_IDX_M GENMASK(16, 8)
1506 +#define ANA_TABLES_SFIDTIDX_POL_IDX_X(x) (((x) & GENMASK(16, 8)) >> 8)
1507 +#define ANA_TABLES_SFIDTIDX_SFID_INDEX(x) ((x) & GENMASK(7, 0))
1508 +#define ANA_TABLES_SFIDTIDX_SFID_INDEX_M GENMASK(7, 0)
1510 +#define ANA_MSTI_STATE_RSZ 0x4
1512 +#define ANA_OAM_UPM_LM_CNT_RSZ 0x4
1514 +#define ANA_SG_ACCESS_CTRL_SGID(x) ((x) & GENMASK(7, 0))
1515 +#define ANA_SG_ACCESS_CTRL_SGID_M GENMASK(7, 0)
1516 +#define ANA_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28)
1518 +#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
1519 +#define ANA_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
1520 +#define ANA_SG_CONFIG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(18, 16))
1521 +#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M GENMASK(18, 16)
1522 +#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(18, 16)) >> 16)
1523 +#define ANA_SG_CONFIG_REG_3_GATE_ENABLE BIT(20)
1524 +#define ANA_SG_CONFIG_REG_3_INIT_IPS(x) (((x) << 21) & GENMASK(24, 21))
1525 +#define ANA_SG_CONFIG_REG_3_INIT_IPS_M GENMASK(24, 21)
1526 +#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x) (((x) & GENMASK(24, 21)) >> 21)
1527 +#define ANA_SG_CONFIG_REG_3_IPV_VALID BIT(24)
1528 +#define ANA_SG_CONFIG_REG_3_IPV_INVALID(x) (((x) << 24) & GENMASK(24, 24))
1529 +#define ANA_SG_CONFIG_REG_3_INIT_IPV(x) (((x) << 21) & GENMASK(23, 21))
1530 +#define ANA_SG_CONFIG_REG_3_INIT_IPV_M GENMASK(23, 21)
1531 +#define ANA_SG_CONFIG_REG_3_INIT_IPV_X(x) (((x) & GENMASK(23, 21)) >> 21)
1532 +#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE BIT(25)
1534 +#define ANA_SG_GCL_GS_CONFIG_RSZ 0x4
1536 +#define ANA_SG_GCL_GS_CONFIG_IPS(x) ((x) & GENMASK(3, 0))
1537 +#define ANA_SG_GCL_GS_CONFIG_IPS_M GENMASK(3, 0)
1538 +#define ANA_SG_GCL_GS_CONFIG_IPV_VALID BIT(3)
1539 +#define ANA_SG_GCL_GS_CONFIG_IPV(x) ((x) & GENMASK(2, 0))
1540 +#define ANA_SG_GCL_GS_CONFIG_IPV_M GENMASK(2, 0)
1541 +#define ANA_SG_GCL_GS_CONFIG_GATE_STATE BIT(4)
1543 +#define ANA_SG_GCL_TI_CONFIG_RSZ 0x4
1545 +#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
1546 +#define ANA_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
1547 +#define ANA_SG_STATUS_REG_3_GATE_STATE BIT(16)
1548 +#define ANA_SG_STATUS_REG_3_IPS(x) (((x) << 20) & GENMASK(23, 20))
1549 +#define ANA_SG_STATUS_REG_3_IPS_M GENMASK(23, 20)
1550 +#define ANA_SG_STATUS_REG_3_IPS_X(x) (((x) & GENMASK(23, 20)) >> 20)
1551 +#define ANA_SG_STATUS_REG_3_IPV_VALID BIT(23)
1552 +#define ANA_SG_STATUS_REG_3_IPV(x) (((x) << 20) & GENMASK(22, 20))
1553 +#define ANA_SG_STATUS_REG_3_IPV_M GENMASK(22, 20)
1554 +#define ANA_SG_STATUS_REG_3_IPV_X(x) (((x) & GENMASK(22, 20)) >> 20)
1555 +#define ANA_SG_STATUS_REG_3_CONFIG_PENDING BIT(24)
1557 +#define ANA_PORT_VLAN_CFG_GSZ 0x100
1559 +#define ANA_PORT_VLAN_CFG_VLAN_VID_AS_ISDX BIT(21)
1560 +#define ANA_PORT_VLAN_CFG_VLAN_AWARE_ENA BIT(20)
1561 +#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT(x) (((x) << 18) & GENMASK(19, 18))
1562 +#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_M GENMASK(19, 18)
1563 +#define ANA_PORT_VLAN_CFG_VLAN_POP_CNT_X(x) (((x) & GENMASK(19, 18)) >> 18)
1564 +#define ANA_PORT_VLAN_CFG_VLAN_INNER_TAG_ENA BIT(17)
1565 +#define ANA_PORT_VLAN_CFG_VLAN_TAG_TYPE BIT(16)
1566 +#define ANA_PORT_VLAN_CFG_VLAN_DEI BIT(15)
1567 +#define ANA_PORT_VLAN_CFG_VLAN_PCP(x) (((x) << 12) & GENMASK(14, 12))
1568 +#define ANA_PORT_VLAN_CFG_VLAN_PCP_M GENMASK(14, 12)
1569 +#define ANA_PORT_VLAN_CFG_VLAN_PCP_X(x) (((x) & GENMASK(14, 12)) >> 12)
1570 +#define ANA_PORT_VLAN_CFG_VLAN_VID(x) ((x) & GENMASK(11, 0))
1571 +#define ANA_PORT_VLAN_CFG_VLAN_VID_M GENMASK(11, 0)
1573 +#define ANA_PORT_DROP_CFG_GSZ 0x100
1575 +#define ANA_PORT_DROP_CFG_DROP_UNTAGGED_ENA BIT(6)
1576 +#define ANA_PORT_DROP_CFG_DROP_S_TAGGED_ENA BIT(5)
1577 +#define ANA_PORT_DROP_CFG_DROP_C_TAGGED_ENA BIT(4)
1578 +#define ANA_PORT_DROP_CFG_DROP_PRIO_S_TAGGED_ENA BIT(3)
1579 +#define ANA_PORT_DROP_CFG_DROP_PRIO_C_TAGGED_ENA BIT(2)
1580 +#define ANA_PORT_DROP_CFG_DROP_NULL_MAC_ENA BIT(1)
1581 +#define ANA_PORT_DROP_CFG_DROP_MC_SMAC_ENA BIT(0)
1583 +#define ANA_PORT_QOS_CFG_GSZ 0x100
1585 +#define ANA_PORT_QOS_CFG_DP_DEFAULT_VAL BIT(8)
1586 +#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL(x) (((x) << 5) & GENMASK(7, 5))
1587 +#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_M GENMASK(7, 5)
1588 +#define ANA_PORT_QOS_CFG_QOS_DEFAULT_VAL_X(x) (((x) & GENMASK(7, 5)) >> 5)
1589 +#define ANA_PORT_QOS_CFG_QOS_DSCP_ENA BIT(4)
1590 +#define ANA_PORT_QOS_CFG_QOS_PCP_ENA BIT(3)
1591 +#define ANA_PORT_QOS_CFG_DSCP_TRANSLATE_ENA BIT(2)
1592 +#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG(x) ((x) & GENMASK(1, 0))
1593 +#define ANA_PORT_QOS_CFG_DSCP_REWR_CFG_M GENMASK(1, 0)
1595 +#define ANA_PORT_VCAP_CFG_GSZ 0x100
1597 +#define ANA_PORT_VCAP_CFG_S1_ENA BIT(14)
1598 +#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA(x) (((x) << 11) & GENMASK(13, 11))
1599 +#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_M GENMASK(13, 11)
1600 +#define ANA_PORT_VCAP_CFG_S1_DMAC_DIP_ENA_X(x) (((x) & GENMASK(13, 11)) >> 11)
1601 +#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA(x) (((x) << 8) & GENMASK(10, 8))
1602 +#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_M GENMASK(10, 8)
1603 +#define ANA_PORT_VCAP_CFG_S1_VLAN_INNER_TAG_ENA_X(x) (((x) & GENMASK(10, 8)) >> 8)
1604 +#define ANA_PORT_VCAP_CFG_PAG_VAL(x) ((x) & GENMASK(7, 0))
1605 +#define ANA_PORT_VCAP_CFG_PAG_VAL_M GENMASK(7, 0)
1607 +#define ANA_PORT_VCAP_S1_KEY_CFG_GSZ 0x100
1608 +#define ANA_PORT_VCAP_S1_KEY_CFG_RSZ 0x4
1610 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG(x) (((x) << 4) & GENMASK(6, 4))
1611 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_M GENMASK(6, 4)
1612 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP6_CFG_X(x) (((x) & GENMASK(6, 4)) >> 4)
1613 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG(x) (((x) << 2) & GENMASK(3, 2))
1614 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_M GENMASK(3, 2)
1615 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_IP4_CFG_X(x) (((x) & GENMASK(3, 2)) >> 2)
1616 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG(x) ((x) & GENMASK(1, 0))
1617 +#define ANA_PORT_VCAP_S1_KEY_CFG_S1_KEY_OTHER_CFG_M GENMASK(1, 0)
1619 +#define ANA_PORT_VCAP_S2_CFG_GSZ 0x100
1621 +#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA(x) (((x) << 17) & GENMASK(18, 17))
1622 +#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_M GENMASK(18, 17)
1623 +#define ANA_PORT_VCAP_S2_CFG_S2_UDP_PAYLOAD_ENA_X(x) (((x) & GENMASK(18, 17)) >> 17)
1624 +#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA(x) (((x) << 15) & GENMASK(16, 15))
1625 +#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_M GENMASK(16, 15)
1626 +#define ANA_PORT_VCAP_S2_CFG_S2_ETYPE_PAYLOAD_ENA_X(x) (((x) & GENMASK(16, 15)) >> 15)
1627 +#define ANA_PORT_VCAP_S2_CFG_S2_ENA BIT(14)
1628 +#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS(x) (((x) << 12) & GENMASK(13, 12))
1629 +#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_M GENMASK(13, 12)
1630 +#define ANA_PORT_VCAP_S2_CFG_S2_SNAP_DIS_X(x) (((x) & GENMASK(13, 12)) >> 12)
1631 +#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS(x) (((x) << 10) & GENMASK(11, 10))
1632 +#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_M GENMASK(11, 10)
1633 +#define ANA_PORT_VCAP_S2_CFG_S2_ARP_DIS_X(x) (((x) & GENMASK(11, 10)) >> 10)
1634 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS(x) (((x) << 8) & GENMASK(9, 8))
1635 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_M GENMASK(9, 8)
1636 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_TCPUDP_DIS_X(x) (((x) & GENMASK(9, 8)) >> 8)
1637 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS(x) (((x) << 6) & GENMASK(7, 6))
1638 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_M GENMASK(7, 6)
1639 +#define ANA_PORT_VCAP_S2_CFG_S2_IP_OTHER_DIS_X(x) (((x) & GENMASK(7, 6)) >> 6)
1640 +#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG(x) (((x) << 2) & GENMASK(5, 2))
1641 +#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_M GENMASK(5, 2)
1642 +#define ANA_PORT_VCAP_S2_CFG_S2_IP6_CFG_X(x) (((x) & GENMASK(5, 2)) >> 2)
1643 +#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS(x) ((x) & GENMASK(1, 0))
1644 +#define ANA_PORT_VCAP_S2_CFG_S2_OAM_DIS_M GENMASK(1, 0)
1646 +#define ANA_PORT_PCP_DEI_MAP_GSZ 0x100
1647 +#define ANA_PORT_PCP_DEI_MAP_RSZ 0x4
1649 +#define ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL BIT(3)
1650 +#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(x) ((x) & GENMASK(2, 0))
1651 +#define ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M GENMASK(2, 0)
1653 +#define ANA_PORT_CPU_FWD_CFG_GSZ 0x100
1655 +#define ANA_PORT_CPU_FWD_CFG_CPU_VRAP_REDIR_ENA BIT(7)
1656 +#define ANA_PORT_CPU_FWD_CFG_CPU_MLD_REDIR_ENA BIT(6)
1657 +#define ANA_PORT_CPU_FWD_CFG_CPU_IGMP_REDIR_ENA BIT(5)
1658 +#define ANA_PORT_CPU_FWD_CFG_CPU_IPMC_CTRL_COPY_ENA BIT(4)
1659 +#define ANA_PORT_CPU_FWD_CFG_CPU_SRC_COPY_ENA BIT(3)
1660 +#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_DROP_ENA BIT(2)
1661 +#define ANA_PORT_CPU_FWD_CFG_CPU_ALLBRIDGE_REDIR_ENA BIT(1)
1662 +#define ANA_PORT_CPU_FWD_CFG_CPU_OAM_ENA BIT(0)
1664 +#define ANA_PORT_CPU_FWD_BPDU_CFG_GSZ 0x100
1666 +#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
1667 +#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_M GENMASK(31, 16)
1668 +#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
1669 +#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA(x) ((x) & GENMASK(15, 0))
1670 +#define ANA_PORT_CPU_FWD_BPDU_CFG_BPDU_REDIR_ENA_M GENMASK(15, 0)
1672 +#define ANA_PORT_CPU_FWD_GARP_CFG_GSZ 0x100
1674 +#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
1675 +#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_M GENMASK(31, 16)
1676 +#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
1677 +#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA(x) ((x) & GENMASK(15, 0))
1678 +#define ANA_PORT_CPU_FWD_GARP_CFG_GARP_REDIR_ENA_M GENMASK(15, 0)
1680 +#define ANA_PORT_CPU_FWD_CCM_CFG_GSZ 0x100
1682 +#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA(x) (((x) << 16) & GENMASK(31, 16))
1683 +#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_M GENMASK(31, 16)
1684 +#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_DROP_ENA_X(x) (((x) & GENMASK(31, 16)) >> 16)
1685 +#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA(x) ((x) & GENMASK(15, 0))
1686 +#define ANA_PORT_CPU_FWD_CCM_CFG_CCM_REDIR_ENA_M GENMASK(15, 0)
1688 +#define ANA_PORT_PORT_CFG_GSZ 0x100
1690 +#define ANA_PORT_PORT_CFG_SRC_MIRROR_ENA BIT(15)
1691 +#define ANA_PORT_PORT_CFG_LIMIT_DROP BIT(14)
1692 +#define ANA_PORT_PORT_CFG_LIMIT_CPU BIT(13)
1693 +#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_DROP BIT(12)
1694 +#define ANA_PORT_PORT_CFG_LOCKED_PORTMOVE_CPU BIT(11)
1695 +#define ANA_PORT_PORT_CFG_LEARNDROP BIT(10)
1696 +#define ANA_PORT_PORT_CFG_LEARNCPU BIT(9)
1697 +#define ANA_PORT_PORT_CFG_LEARNAUTO BIT(8)
1698 +#define ANA_PORT_PORT_CFG_LEARN_ENA BIT(7)
1699 +#define ANA_PORT_PORT_CFG_RECV_ENA BIT(6)
1700 +#define ANA_PORT_PORT_CFG_PORTID_VAL(x) (((x) << 2) & GENMASK(5, 2))
1701 +#define ANA_PORT_PORT_CFG_PORTID_VAL_M GENMASK(5, 2)
1702 +#define ANA_PORT_PORT_CFG_PORTID_VAL_X(x) (((x) & GENMASK(5, 2)) >> 2)
1703 +#define ANA_PORT_PORT_CFG_USE_B_DOM_TBL BIT(1)
1704 +#define ANA_PORT_PORT_CFG_LSR_MODE BIT(0)
1706 +#define ANA_PORT_POL_CFG_GSZ 0x100
1708 +#define ANA_PORT_POL_CFG_POL_CPU_REDIR_8021 BIT(19)
1709 +#define ANA_PORT_POL_CFG_POL_CPU_REDIR_IP BIT(18)
1710 +#define ANA_PORT_POL_CFG_PORT_POL_ENA BIT(17)
1711 +#define ANA_PORT_POL_CFG_QUEUE_POL_ENA(x) (((x) << 9) & GENMASK(16, 9))
1712 +#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_M GENMASK(16, 9)
1713 +#define ANA_PORT_POL_CFG_QUEUE_POL_ENA_X(x) (((x) & GENMASK(16, 9)) >> 9)
1714 +#define ANA_PORT_POL_CFG_POL_ORDER(x) ((x) & GENMASK(8, 0))
1715 +#define ANA_PORT_POL_CFG_POL_ORDER_M GENMASK(8, 0)
1717 +#define ANA_PORT_PTP_CFG_GSZ 0x100
1719 +#define ANA_PORT_PTP_CFG_PTP_BACKPLANE_MODE BIT(0)
1721 +#define ANA_PORT_PTP_DLY1_CFG_GSZ 0x100
1723 +#define ANA_PORT_PTP_DLY2_CFG_GSZ 0x100
1725 +#define ANA_PORT_SFID_CFG_GSZ 0x100
1726 +#define ANA_PORT_SFID_CFG_RSZ 0x4
1728 +#define ANA_PORT_SFID_CFG_SFID_VALID BIT(8)
1729 +#define ANA_PORT_SFID_CFG_SFID(x) ((x) & GENMASK(7, 0))
1730 +#define ANA_PORT_SFID_CFG_SFID_M GENMASK(7, 0)
1732 +#define ANA_PFC_PFC_CFG_GSZ 0x40
1734 +#define ANA_PFC_PFC_CFG_RX_PFC_ENA(x) (((x) << 2) & GENMASK(9, 2))
1735 +#define ANA_PFC_PFC_CFG_RX_PFC_ENA_M GENMASK(9, 2)
1736 +#define ANA_PFC_PFC_CFG_RX_PFC_ENA_X(x) (((x) & GENMASK(9, 2)) >> 2)
1737 +#define ANA_PFC_PFC_CFG_FC_LINK_SPEED(x) ((x) & GENMASK(1, 0))
1738 +#define ANA_PFC_PFC_CFG_FC_LINK_SPEED_M GENMASK(1, 0)
1740 +#define ANA_PFC_PFC_TIMER_GSZ 0x40
1741 +#define ANA_PFC_PFC_TIMER_RSZ 0x4
1743 +#define ANA_IPT_OAM_MEP_CFG_GSZ 0x8
1745 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P(x) (((x) << 6) & GENMASK(10, 6))
1746 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_M GENMASK(10, 6)
1747 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_P_X(x) (((x) & GENMASK(10, 6)) >> 6)
1748 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX(x) (((x) << 1) & GENMASK(5, 1))
1749 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_M GENMASK(5, 1)
1750 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_X(x) (((x) & GENMASK(5, 1)) >> 1)
1751 +#define ANA_IPT_OAM_MEP_CFG_MEP_IDX_ENA BIT(0)
1753 +#define ANA_IPT_IPT_GSZ 0x8
1755 +#define ANA_IPT_IPT_IPT_CFG(x) (((x) << 15) & GENMASK(16, 15))
1756 +#define ANA_IPT_IPT_IPT_CFG_M GENMASK(16, 15)
1757 +#define ANA_IPT_IPT_IPT_CFG_X(x) (((x) & GENMASK(16, 15)) >> 15)
1758 +#define ANA_IPT_IPT_ISDX_P(x) (((x) << 7) & GENMASK(14, 7))
1759 +#define ANA_IPT_IPT_ISDX_P_M GENMASK(14, 7)
1760 +#define ANA_IPT_IPT_ISDX_P_X(x) (((x) & GENMASK(14, 7)) >> 7)
1761 +#define ANA_IPT_IPT_PPT_IDX(x) ((x) & GENMASK(6, 0))
1762 +#define ANA_IPT_IPT_PPT_IDX_M GENMASK(6, 0)
1764 +#define ANA_PPT_PPT_RSZ 0x4
1766 +#define ANA_FID_MAP_FID_MAP_RSZ 0x4
1768 +#define ANA_FID_MAP_FID_MAP_FID_C_VAL(x) (((x) << 6) & GENMASK(11, 6))
1769 +#define ANA_FID_MAP_FID_MAP_FID_C_VAL_M GENMASK(11, 6)
1770 +#define ANA_FID_MAP_FID_MAP_FID_C_VAL_X(x) (((x) & GENMASK(11, 6)) >> 6)
1771 +#define ANA_FID_MAP_FID_MAP_FID_B_VAL(x) ((x) & GENMASK(5, 0))
1772 +#define ANA_FID_MAP_FID_MAP_FID_B_VAL_M GENMASK(5, 0)
1774 +#define ANA_AGGR_CFG_AC_RND_ENA BIT(7)
1775 +#define ANA_AGGR_CFG_AC_DMAC_ENA BIT(6)
1776 +#define ANA_AGGR_CFG_AC_SMAC_ENA BIT(5)
1777 +#define ANA_AGGR_CFG_AC_IP6_FLOW_LBL_ENA BIT(4)
1778 +#define ANA_AGGR_CFG_AC_IP6_TCPUDP_ENA BIT(3)
1779 +#define ANA_AGGR_CFG_AC_IP4_SIPDIP_ENA BIT(2)
1780 +#define ANA_AGGR_CFG_AC_IP4_TCPUDP_ENA BIT(1)
1781 +#define ANA_AGGR_CFG_AC_ISDX_ENA BIT(0)
1783 +#define ANA_CPUQ_CFG_CPUQ_MLD(x) (((x) << 27) & GENMASK(29, 27))
1784 +#define ANA_CPUQ_CFG_CPUQ_MLD_M GENMASK(29, 27)
1785 +#define ANA_CPUQ_CFG_CPUQ_MLD_X(x) (((x) & GENMASK(29, 27)) >> 27)
1786 +#define ANA_CPUQ_CFG_CPUQ_IGMP(x) (((x) << 24) & GENMASK(26, 24))
1787 +#define ANA_CPUQ_CFG_CPUQ_IGMP_M GENMASK(26, 24)
1788 +#define ANA_CPUQ_CFG_CPUQ_IGMP_X(x) (((x) & GENMASK(26, 24)) >> 24)
1789 +#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL(x) (((x) << 21) & GENMASK(23, 21))
1790 +#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_M GENMASK(23, 21)
1791 +#define ANA_CPUQ_CFG_CPUQ_IPMC_CTRL_X(x) (((x) & GENMASK(23, 21)) >> 21)
1792 +#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE(x) (((x) << 18) & GENMASK(20, 18))
1793 +#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_M GENMASK(20, 18)
1794 +#define ANA_CPUQ_CFG_CPUQ_ALLBRIDGE_X(x) (((x) & GENMASK(20, 18)) >> 18)
1795 +#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE(x) (((x) << 15) & GENMASK(17, 15))
1796 +#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_M GENMASK(17, 15)
1797 +#define ANA_CPUQ_CFG_CPUQ_LOCKED_PORTMOVE_X(x) (((x) & GENMASK(17, 15)) >> 15)
1798 +#define ANA_CPUQ_CFG_CPUQ_SRC_COPY(x) (((x) << 12) & GENMASK(14, 12))
1799 +#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_M GENMASK(14, 12)
1800 +#define ANA_CPUQ_CFG_CPUQ_SRC_COPY_X(x) (((x) & GENMASK(14, 12)) >> 12)
1801 +#define ANA_CPUQ_CFG_CPUQ_MAC_COPY(x) (((x) << 9) & GENMASK(11, 9))
1802 +#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_M GENMASK(11, 9)
1803 +#define ANA_CPUQ_CFG_CPUQ_MAC_COPY_X(x) (((x) & GENMASK(11, 9)) >> 9)
1804 +#define ANA_CPUQ_CFG_CPUQ_LRN(x) (((x) << 6) & GENMASK(8, 6))
1805 +#define ANA_CPUQ_CFG_CPUQ_LRN_M GENMASK(8, 6)
1806 +#define ANA_CPUQ_CFG_CPUQ_LRN_X(x) (((x) & GENMASK(8, 6)) >> 6)
1807 +#define ANA_CPUQ_CFG_CPUQ_MIRROR(x) (((x) << 3) & GENMASK(5, 3))
1808 +#define ANA_CPUQ_CFG_CPUQ_MIRROR_M GENMASK(5, 3)
1809 +#define ANA_CPUQ_CFG_CPUQ_MIRROR_X(x) (((x) & GENMASK(5, 3)) >> 3)
1810 +#define ANA_CPUQ_CFG_CPUQ_SFLOW(x) ((x) & GENMASK(2, 0))
1811 +#define ANA_CPUQ_CFG_CPUQ_SFLOW_M GENMASK(2, 0)
1813 +#define ANA_CPUQ_8021_CFG_RSZ 0x4
1815 +#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL(x) (((x) << 6) & GENMASK(8, 6))
1816 +#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_M GENMASK(8, 6)
1817 +#define ANA_CPUQ_8021_CFG_CPUQ_BPDU_VAL_X(x) (((x) & GENMASK(8, 6)) >> 6)
1818 +#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL(x) (((x) << 3) & GENMASK(5, 3))
1819 +#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_M GENMASK(5, 3)
1820 +#define ANA_CPUQ_8021_CFG_CPUQ_GARP_VAL_X(x) (((x) & GENMASK(5, 3)) >> 3)
1821 +#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL(x) ((x) & GENMASK(2, 0))
1822 +#define ANA_CPUQ_8021_CFG_CPUQ_CCM_VAL_M GENMASK(2, 0)
1824 +#define ANA_DSCP_CFG_RSZ 0x4
1826 +#define ANA_DSCP_CFG_DP_DSCP_VAL BIT(11)
1827 +#define ANA_DSCP_CFG_QOS_DSCP_VAL(x) (((x) << 8) & GENMASK(10, 8))
1828 +#define ANA_DSCP_CFG_QOS_DSCP_VAL_M GENMASK(10, 8)
1829 +#define ANA_DSCP_CFG_QOS_DSCP_VAL_X(x) (((x) & GENMASK(10, 8)) >> 8)
1830 +#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL(x) (((x) << 2) & GENMASK(7, 2))
1831 +#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_M GENMASK(7, 2)
1832 +#define ANA_DSCP_CFG_DSCP_TRANSLATE_VAL_X(x) (((x) & GENMASK(7, 2)) >> 2)
1833 +#define ANA_DSCP_CFG_DSCP_TRUST_ENA BIT(1)
1834 +#define ANA_DSCP_CFG_DSCP_REWR_ENA BIT(0)
1836 +#define ANA_DSCP_REWR_CFG_RSZ 0x4
1838 +#define ANA_VCAP_RNG_TYPE_CFG_RSZ 0x4
1840 +#define ANA_VCAP_RNG_VAL_CFG_RSZ 0x4
1842 +#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL(x) (((x) << 16) & GENMASK(31, 16))
1843 +#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_M GENMASK(31, 16)
1844 +#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MIN_VAL_X(x) (((x) & GENMASK(31, 16)) >> 16)
1845 +#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL(x) ((x) & GENMASK(15, 0))
1846 +#define ANA_VCAP_RNG_VAL_CFG_VCAP_RNG_MAX_VAL_M GENMASK(15, 0)
1848 +#define ANA_VRAP_CFG_VRAP_VLAN_AWARE_ENA BIT(12)
1849 +#define ANA_VRAP_CFG_VRAP_VID(x) ((x) & GENMASK(11, 0))
1850 +#define ANA_VRAP_CFG_VRAP_VID_M GENMASK(11, 0)
1852 +#define ANA_DISCARD_CFG_DROP_TAGGING_ISDX0 BIT(3)
1853 +#define ANA_DISCARD_CFG_DROP_CTRLPROT_ISDX0 BIT(2)
1854 +#define ANA_DISCARD_CFG_DROP_TAGGING_S2_ENA BIT(1)
1855 +#define ANA_DISCARD_CFG_DROP_CTRLPROT_S2_ENA BIT(0)
1857 +#define ANA_FID_CFG_VID_MC_ENA BIT(0)
1859 +#define ANA_POL_PIR_CFG_GSZ 0x20
1861 +#define ANA_POL_PIR_CFG_PIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
1862 +#define ANA_POL_PIR_CFG_PIR_RATE_M GENMASK(20, 6)
1863 +#define ANA_POL_PIR_CFG_PIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
1864 +#define ANA_POL_PIR_CFG_PIR_BURST(x) ((x) & GENMASK(5, 0))
1865 +#define ANA_POL_PIR_CFG_PIR_BURST_M GENMASK(5, 0)
1867 +#define ANA_POL_CIR_CFG_GSZ 0x20
1869 +#define ANA_POL_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
1870 +#define ANA_POL_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
1871 +#define ANA_POL_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
1872 +#define ANA_POL_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
1873 +#define ANA_POL_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
1875 +#define ANA_POL_MODE_CFG_GSZ 0x20
1877 +#define ANA_POL_MODE_CFG_IPG_SIZE(x) (((x) << 5) & GENMASK(9, 5))
1878 +#define ANA_POL_MODE_CFG_IPG_SIZE_M GENMASK(9, 5)
1879 +#define ANA_POL_MODE_CFG_IPG_SIZE_X(x) (((x) & GENMASK(9, 5)) >> 5)
1880 +#define ANA_POL_MODE_CFG_FRM_MODE(x) (((x) << 3) & GENMASK(4, 3))
1881 +#define ANA_POL_MODE_CFG_FRM_MODE_M GENMASK(4, 3)
1882 +#define ANA_POL_MODE_CFG_FRM_MODE_X(x) (((x) & GENMASK(4, 3)) >> 3)
1883 +#define ANA_POL_MODE_CFG_DLB_COUPLED BIT(2)
1884 +#define ANA_POL_MODE_CFG_CIR_ENA BIT(1)
1885 +#define ANA_POL_MODE_CFG_OVERSHOOT_ENA BIT(0)
1887 +#define ANA_POL_PIR_STATE_GSZ 0x20
1889 +#define ANA_POL_CIR_STATE_GSZ 0x20
1891 +#define ANA_POL_STATE_GSZ 0x20
1893 +#define ANA_POL_FLOWC_RSZ 0x4
1895 +#define ANA_POL_FLOWC_POL_FLOWC BIT(0)
1897 +#define ANA_POL_HYST_POL_FC_HYST(x) (((x) << 4) & GENMASK(9, 4))
1898 +#define ANA_POL_HYST_POL_FC_HYST_M GENMASK(9, 4)
1899 +#define ANA_POL_HYST_POL_FC_HYST_X(x) (((x) & GENMASK(9, 4)) >> 4)
1900 +#define ANA_POL_HYST_POL_STOP_HYST(x) ((x) & GENMASK(3, 0))
1901 +#define ANA_POL_HYST_POL_STOP_HYST_M GENMASK(3, 0)
1903 +#define ANA_POL_MISC_CFG_POL_CLOSE_ALL BIT(1)
1904 +#define ANA_POL_MISC_CFG_POL_LEAK_DIS BIT(0)
1908 +++ b/include/soc/mscc/ocelot_dev.h
1910 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
1912 + * Microsemi Ocelot Switch driver
1914 + * Copyright (c) 2017 Microsemi Corporation
1917 +#ifndef _MSCC_OCELOT_DEV_H_
1918 +#define _MSCC_OCELOT_DEV_H_
1920 +#define DEV_CLOCK_CFG 0x0
1922 +#define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
1923 +#define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
1924 +#define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
1925 +#define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
1926 +#define DEV_CLOCK_CFG_PORT_RST BIT(3)
1927 +#define DEV_CLOCK_CFG_PHY_RST BIT(2)
1928 +#define DEV_CLOCK_CFG_LINK_SPEED(x) ((x) & GENMASK(1, 0))
1929 +#define DEV_CLOCK_CFG_LINK_SPEED_M GENMASK(1, 0)
1931 +#define DEV_PORT_MISC 0x4
1933 +#define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
1934 +#define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
1935 +#define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
1936 +#define DEV_PORT_MISC_DEV_LOOP_ENA BIT(1)
1937 +#define DEV_PORT_MISC_HDX_FAST_DIS BIT(0)
1939 +#define DEV_EVENTS 0x8
1941 +#define DEV_EEE_CFG 0xc
1943 +#define DEV_EEE_CFG_EEE_ENA BIT(22)
1944 +#define DEV_EEE_CFG_EEE_TIMER_AGE(x) (((x) << 15) & GENMASK(21, 15))
1945 +#define DEV_EEE_CFG_EEE_TIMER_AGE_M GENMASK(21, 15)
1946 +#define DEV_EEE_CFG_EEE_TIMER_AGE_X(x) (((x) & GENMASK(21, 15)) >> 15)
1947 +#define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x) (((x) << 8) & GENMASK(14, 8))
1948 +#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M GENMASK(14, 8)
1949 +#define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x) (((x) & GENMASK(14, 8)) >> 8)
1950 +#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x) (((x) << 1) & GENMASK(7, 1))
1951 +#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M GENMASK(7, 1)
1952 +#define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x) (((x) & GENMASK(7, 1)) >> 1)
1953 +#define DEV_EEE_CFG_PORT_LPI BIT(0)
1955 +#define DEV_RX_PATH_DELAY 0x10
1957 +#define DEV_TX_PATH_DELAY 0x14
1959 +#define DEV_PTP_PREDICT_CFG 0x18
1961 +#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x) (((x) << 4) & GENMASK(11, 4))
1962 +#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M GENMASK(11, 4)
1963 +#define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x) (((x) & GENMASK(11, 4)) >> 4)
1964 +#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x) ((x) & GENMASK(3, 0))
1965 +#define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M GENMASK(3, 0)
1967 +#define DEV_MAC_ENA_CFG 0x1c
1969 +#define DEV_MAC_ENA_CFG_RX_ENA BIT(4)
1970 +#define DEV_MAC_ENA_CFG_TX_ENA BIT(0)
1972 +#define DEV_MAC_MODE_CFG 0x20
1974 +#define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8)
1975 +#define DEV_MAC_MODE_CFG_GIGA_MODE_ENA BIT(4)
1976 +#define DEV_MAC_MODE_CFG_FDX_ENA BIT(0)
1978 +#define DEV_MAC_MAXLEN_CFG 0x24
1980 +#define DEV_MAC_TAGS_CFG 0x28
1982 +#define DEV_MAC_TAGS_CFG_TAG_ID(x) (((x) << 16) & GENMASK(31, 16))
1983 +#define DEV_MAC_TAGS_CFG_TAG_ID_M GENMASK(31, 16)
1984 +#define DEV_MAC_TAGS_CFG_TAG_ID_X(x) (((x) & GENMASK(31, 16)) >> 16)
1985 +#define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(2)
1986 +#define DEV_MAC_TAGS_CFG_PB_ENA BIT(1)
1987 +#define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0)
1989 +#define DEV_MAC_ADV_CHK_CFG 0x2c
1991 +#define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0)
1993 +#define DEV_MAC_IFG_CFG 0x30
1995 +#define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
1996 +#define DEV_MAC_IFG_CFG_REDUCED_TX_IFG BIT(16)
1997 +#define DEV_MAC_IFG_CFG_TX_IFG(x) (((x) << 8) & GENMASK(12, 8))
1998 +#define DEV_MAC_IFG_CFG_TX_IFG_M GENMASK(12, 8)
1999 +#define DEV_MAC_IFG_CFG_TX_IFG_X(x) (((x) & GENMASK(12, 8)) >> 8)
2000 +#define DEV_MAC_IFG_CFG_RX_IFG2(x) (((x) << 4) & GENMASK(7, 4))
2001 +#define DEV_MAC_IFG_CFG_RX_IFG2_M GENMASK(7, 4)
2002 +#define DEV_MAC_IFG_CFG_RX_IFG2_X(x) (((x) & GENMASK(7, 4)) >> 4)
2003 +#define DEV_MAC_IFG_CFG_RX_IFG1(x) ((x) & GENMASK(3, 0))
2004 +#define DEV_MAC_IFG_CFG_RX_IFG1_M GENMASK(3, 0)
2006 +#define DEV_MAC_HDX_CFG 0x34
2008 +#define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26)
2009 +#define DEV_MAC_HDX_CFG_OB_ENA BIT(25)
2010 +#define DEV_MAC_HDX_CFG_WEXC_DIS BIT(24)
2011 +#define DEV_MAC_HDX_CFG_SEED(x) (((x) << 16) & GENMASK(23, 16))
2012 +#define DEV_MAC_HDX_CFG_SEED_M GENMASK(23, 16)
2013 +#define DEV_MAC_HDX_CFG_SEED_X(x) (((x) & GENMASK(23, 16)) >> 16)
2014 +#define DEV_MAC_HDX_CFG_SEED_LOAD BIT(12)
2015 +#define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
2016 +#define DEV_MAC_HDX_CFG_LATE_COL_POS(x) ((x) & GENMASK(6, 0))
2017 +#define DEV_MAC_HDX_CFG_LATE_COL_POS_M GENMASK(6, 0)
2019 +#define DEV_MAC_DBG_CFG 0x38
2021 +#define DEV_MAC_DBG_CFG_TBI_MODE BIT(4)
2022 +#define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA BIT(0)
2024 +#define DEV_MAC_FC_MAC_LOW_CFG 0x3c
2026 +#define DEV_MAC_FC_MAC_HIGH_CFG 0x40
2028 +#define DEV_MAC_STICKY 0x44
2030 +#define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY BIT(9)
2031 +#define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY BIT(8)
2032 +#define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY BIT(7)
2033 +#define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY BIT(6)
2034 +#define DEV_MAC_STICKY_RX_JUNK_STICKY BIT(5)
2035 +#define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY BIT(4)
2036 +#define DEV_MAC_STICKY_TX_JAM_STICKY BIT(3)
2037 +#define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY BIT(2)
2038 +#define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY BIT(1)
2039 +#define DEV_MAC_STICKY_TX_ABORT_STICKY BIT(0)
2041 +#define PCS1G_CFG 0x48
2043 +#define PCS1G_CFG_LINK_STATUS_TYPE BIT(4)
2044 +#define PCS1G_CFG_AN_LINK_CTRL_ENA BIT(1)
2045 +#define PCS1G_CFG_PCS_ENA BIT(0)
2047 +#define PCS1G_MODE_CFG 0x4c
2049 +#define PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4)
2050 +#define PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)
2052 +#define PCS1G_SD_CFG 0x50
2054 +#define PCS1G_SD_CFG_SD_SEL BIT(8)
2055 +#define PCS1G_SD_CFG_SD_POL BIT(4)
2056 +#define PCS1G_SD_CFG_SD_ENA BIT(0)
2058 +#define PCS1G_ANEG_CFG 0x54
2060 +#define PCS1G_ANEG_CFG_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
2061 +#define PCS1G_ANEG_CFG_ADV_ABILITY_M GENMASK(31, 16)
2062 +#define PCS1G_ANEG_CFG_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
2063 +#define PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)
2064 +#define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
2065 +#define PCS1G_ANEG_CFG_ANEG_ENA BIT(0)
2067 +#define PCS1G_ANEG_NP_CFG 0x58
2069 +#define PCS1G_ANEG_NP_CFG_NP_TX(x) (((x) << 16) & GENMASK(31, 16))
2070 +#define PCS1G_ANEG_NP_CFG_NP_TX_M GENMASK(31, 16)
2071 +#define PCS1G_ANEG_NP_CFG_NP_TX_X(x) (((x) & GENMASK(31, 16)) >> 16)
2072 +#define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT BIT(0)
2074 +#define PCS1G_LB_CFG 0x5c
2076 +#define PCS1G_LB_CFG_RA_ENA BIT(4)
2077 +#define PCS1G_LB_CFG_GMII_PHY_LB_ENA BIT(1)
2078 +#define PCS1G_LB_CFG_TBI_HOST_LB_ENA BIT(0)
2080 +#define PCS1G_DBG_CFG 0x60
2082 +#define PCS1G_DBG_CFG_UDLT BIT(0)
2084 +#define PCS1G_CDET_CFG 0x64
2086 +#define PCS1G_CDET_CFG_CDET_ENA BIT(0)
2088 +#define PCS1G_ANEG_STATUS 0x68
2090 +#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x) (((x) << 16) & GENMASK(31, 16))
2091 +#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M GENMASK(31, 16)
2092 +#define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x) (((x) & GENMASK(31, 16)) >> 16)
2093 +#define PCS1G_ANEG_STATUS_PR BIT(4)
2094 +#define PCS1G_ANEG_STATUS_PAGE_RX_STICKY BIT(3)
2095 +#define PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)
2097 +#define PCS1G_ANEG_NP_STATUS 0x6c
2099 +#define PCS1G_LINK_STATUS 0x70
2101 +#define PCS1G_LINK_STATUS_DELAY_VAR(x) (((x) << 12) & GENMASK(15, 12))
2102 +#define PCS1G_LINK_STATUS_DELAY_VAR_M GENMASK(15, 12)
2103 +#define PCS1G_LINK_STATUS_DELAY_VAR_X(x) (((x) & GENMASK(15, 12)) >> 12)
2104 +#define PCS1G_LINK_STATUS_SIGNAL_DETECT BIT(8)
2105 +#define PCS1G_LINK_STATUS_LINK_STATUS BIT(4)
2106 +#define PCS1G_LINK_STATUS_SYNC_STATUS BIT(0)
2108 +#define PCS1G_LINK_DOWN_CNT 0x74
2110 +#define PCS1G_STICKY 0x78
2112 +#define PCS1G_STICKY_LINK_DOWN_STICKY BIT(4)
2113 +#define PCS1G_STICKY_OUT_OF_SYNC_STICKY BIT(0)
2115 +#define PCS1G_DEBUG_STATUS 0x7c
2117 +#define PCS1G_LPI_CFG 0x80
2119 +#define PCS1G_LPI_CFG_QSGMII_MS_SEL BIT(20)
2120 +#define PCS1G_LPI_CFG_RX_LPI_OUT_DIS BIT(17)
2121 +#define PCS1G_LPI_CFG_LPI_TESTMODE BIT(16)
2122 +#define PCS1G_LPI_CFG_LPI_RX_WTIM(x) (((x) << 4) & GENMASK(5, 4))
2123 +#define PCS1G_LPI_CFG_LPI_RX_WTIM_M GENMASK(5, 4)
2124 +#define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x) (((x) & GENMASK(5, 4)) >> 4)
2125 +#define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE BIT(0)
2127 +#define PCS1G_LPI_WAKE_ERROR_CNT 0x84
2129 +#define PCS1G_LPI_STATUS 0x88
2131 +#define PCS1G_LPI_STATUS_RX_LPI_FAIL BIT(16)
2132 +#define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY BIT(12)
2133 +#define PCS1G_LPI_STATUS_RX_QUIET BIT(9)
2134 +#define PCS1G_LPI_STATUS_RX_LPI_MODE BIT(8)
2135 +#define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY BIT(4)
2136 +#define PCS1G_LPI_STATUS_TX_QUIET BIT(1)
2137 +#define PCS1G_LPI_STATUS_TX_LPI_MODE BIT(0)
2139 +#define PCS1G_TSTPAT_MODE_CFG 0x8c
2141 +#define PCS1G_TSTPAT_STATUS 0x90
2143 +#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x) (((x) << 8) & GENMASK(15, 8))
2144 +#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M GENMASK(15, 8)
2145 +#define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x) (((x) & GENMASK(15, 8)) >> 8)
2146 +#define PCS1G_TSTPAT_STATUS_JTP_ERR BIT(4)
2147 +#define PCS1G_TSTPAT_STATUS_JTP_LOCK BIT(0)
2149 +#define DEV_PCS_FX100_CFG 0x94
2151 +#define DEV_PCS_FX100_CFG_SD_SEL BIT(26)
2152 +#define DEV_PCS_FX100_CFG_SD_POL BIT(25)
2153 +#define DEV_PCS_FX100_CFG_SD_ENA BIT(24)
2154 +#define DEV_PCS_FX100_CFG_LOOPBACK_ENA BIT(20)
2155 +#define DEV_PCS_FX100_CFG_SWAP_MII_ENA BIT(16)
2156 +#define DEV_PCS_FX100_CFG_RXBITSEL(x) (((x) << 12) & GENMASK(15, 12))
2157 +#define DEV_PCS_FX100_CFG_RXBITSEL_M GENMASK(15, 12)
2158 +#define DEV_PCS_FX100_CFG_RXBITSEL_X(x) (((x) & GENMASK(15, 12)) >> 12)
2159 +#define DEV_PCS_FX100_CFG_SIGDET_CFG(x) (((x) << 9) & GENMASK(10, 9))
2160 +#define DEV_PCS_FX100_CFG_SIGDET_CFG_M GENMASK(10, 9)
2161 +#define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x) (((x) & GENMASK(10, 9)) >> 9)
2162 +#define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA BIT(8)
2163 +#define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x) (((x) << 4) & GENMASK(7, 4))
2164 +#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M GENMASK(7, 4)
2165 +#define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x) (((x) & GENMASK(7, 4)) >> 4)
2166 +#define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA BIT(3)
2167 +#define DEV_PCS_FX100_CFG_FEFCHK_ENA BIT(2)
2168 +#define DEV_PCS_FX100_CFG_FEFGEN_ENA BIT(1)
2169 +#define DEV_PCS_FX100_CFG_PCS_ENA BIT(0)
2171 +#define DEV_PCS_FX100_STATUS 0x98
2173 +#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x) (((x) << 8) & GENMASK(11, 8))
2174 +#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M GENMASK(11, 8)
2175 +#define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x) (((x) & GENMASK(11, 8)) >> 8)
2176 +#define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
2177 +#define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
2178 +#define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
2179 +#define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
2180 +#define DEV_PCS_FX100_STATUS_FEF_STATUS BIT(2)
2181 +#define DEV_PCS_FX100_STATUS_SIGNAL_DETECT BIT(1)
2182 +#define DEV_PCS_FX100_STATUS_SYNC_STATUS BIT(0)
2186 +++ b/include/soc/mscc/ocelot_qsys.h
2188 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2190 + * Microsemi Ocelot Switch driver
2192 + * Copyright (c) 2017 Microsemi Corporation
2195 +#ifndef _MSCC_OCELOT_QSYS_H_
2196 +#define _MSCC_OCELOT_QSYS_H_
2198 +#define QSYS_PORT_MODE_RSZ 0x4
2200 +#define QSYS_PORT_MODE_DEQUEUE_DIS BIT(1)
2201 +#define QSYS_PORT_MODE_DEQUEUE_LATE BIT(0)
2203 +#define QSYS_SWITCH_PORT_MODE_RSZ 0x4
2205 +#define QSYS_SWITCH_PORT_MODE_PORT_ENA BIT(14)
2206 +#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(x) (((x) << 11) & GENMASK(13, 11))
2207 +#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_M GENMASK(13, 11)
2208 +#define QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG_X(x) (((x) & GENMASK(13, 11)) >> 11)
2209 +#define QSYS_SWITCH_PORT_MODE_YEL_RSRVD BIT(10)
2210 +#define QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE BIT(9)
2211 +#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA(x) (((x) << 1) & GENMASK(8, 1))
2212 +#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_M GENMASK(8, 1)
2213 +#define QSYS_SWITCH_PORT_MODE_TX_PFC_ENA_X(x) (((x) & GENMASK(8, 1)) >> 1)
2214 +#define QSYS_SWITCH_PORT_MODE_TX_PFC_MODE BIT(0)
2216 +#define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE BIT(5)
2217 +#define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE BIT(4)
2218 +#define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE BIT(3)
2219 +#define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE BIT(2)
2220 +#define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE BIT(1)
2221 +#define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS BIT(0)
2223 +#define QSYS_EEE_CFG_RSZ 0x4
2225 +#define QSYS_EEE_THRES_EEE_HIGH_BYTES(x) (((x) << 8) & GENMASK(15, 8))
2226 +#define QSYS_EEE_THRES_EEE_HIGH_BYTES_M GENMASK(15, 8)
2227 +#define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x) (((x) & GENMASK(15, 8)) >> 8)
2228 +#define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x) ((x) & GENMASK(7, 0))
2229 +#define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M GENMASK(7, 0)
2231 +#define QSYS_SW_STATUS_RSZ 0x4
2233 +#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x) (((x) << 8) & GENMASK(12, 8))
2234 +#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M GENMASK(12, 8)
2235 +#define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x) (((x) & GENMASK(12, 8)) >> 8)
2236 +#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x) ((x) & GENMASK(7, 0))
2237 +#define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M GENMASK(7, 0)
2239 +#define QSYS_QMAP_GSZ 0x4
2241 +#define QSYS_QMAP_SE_BASE(x) (((x) << 5) & GENMASK(12, 5))
2242 +#define QSYS_QMAP_SE_BASE_M GENMASK(12, 5)
2243 +#define QSYS_QMAP_SE_BASE_X(x) (((x) & GENMASK(12, 5)) >> 5)
2244 +#define QSYS_QMAP_SE_IDX_SEL(x) (((x) << 2) & GENMASK(4, 2))
2245 +#define QSYS_QMAP_SE_IDX_SEL_M GENMASK(4, 2)
2246 +#define QSYS_QMAP_SE_IDX_SEL_X(x) (((x) & GENMASK(4, 2)) >> 2)
2247 +#define QSYS_QMAP_SE_INP_SEL(x) ((x) & GENMASK(1, 0))
2248 +#define QSYS_QMAP_SE_INP_SEL_M GENMASK(1, 0)
2250 +#define QSYS_ISDX_SGRP_GSZ 0x4
2252 +#define QSYS_TIMED_FRAME_ENTRY_GSZ 0x4
2254 +#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x) (((x) << 9) & GENMASK(18, 9))
2255 +#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M GENMASK(18, 9)
2256 +#define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x) (((x) & GENMASK(18, 9)) >> 9)
2257 +#define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT BIT(8)
2258 +#define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC BIT(7)
2259 +#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x) ((x) & GENMASK(6, 0))
2260 +#define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M GENMASK(6, 0)
2262 +#define QSYS_RED_PROFILE_RSZ 0x4
2264 +#define QSYS_RED_PROFILE_WM_RED_LOW(x) (((x) << 8) & GENMASK(15, 8))
2265 +#define QSYS_RED_PROFILE_WM_RED_LOW_M GENMASK(15, 8)
2266 +#define QSYS_RED_PROFILE_WM_RED_LOW_X(x) (((x) & GENMASK(15, 8)) >> 8)
2267 +#define QSYS_RED_PROFILE_WM_RED_HIGH(x) ((x) & GENMASK(7, 0))
2268 +#define QSYS_RED_PROFILE_WM_RED_HIGH_M GENMASK(7, 0)
2270 +#define QSYS_RES_CFG_GSZ 0x8
2272 +#define QSYS_RES_STAT_GSZ 0x8
2274 +#define QSYS_RES_STAT_INUSE(x) (((x) << 12) & GENMASK(23, 12))
2275 +#define QSYS_RES_STAT_INUSE_M GENMASK(23, 12)
2276 +#define QSYS_RES_STAT_INUSE_X(x) (((x) & GENMASK(23, 12)) >> 12)
2277 +#define QSYS_RES_STAT_MAXUSE(x) ((x) & GENMASK(11, 0))
2278 +#define QSYS_RES_STAT_MAXUSE_M GENMASK(11, 0)
2280 +#define QSYS_EVENTS_CORE_EV_FDC(x) (((x) << 2) & GENMASK(4, 2))
2281 +#define QSYS_EVENTS_CORE_EV_FDC_M GENMASK(4, 2)
2282 +#define QSYS_EVENTS_CORE_EV_FDC_X(x) (((x) & GENMASK(4, 2)) >> 2)
2283 +#define QSYS_EVENTS_CORE_EV_FRD(x) ((x) & GENMASK(1, 0))
2284 +#define QSYS_EVENTS_CORE_EV_FRD_M GENMASK(1, 0)
2286 +#define QSYS_QMAXSDU_CFG_0_RSZ 0x4
2288 +#define QSYS_QMAXSDU_CFG_1_RSZ 0x4
2290 +#define QSYS_QMAXSDU_CFG_2_RSZ 0x4
2292 +#define QSYS_QMAXSDU_CFG_3_RSZ 0x4
2294 +#define QSYS_QMAXSDU_CFG_4_RSZ 0x4
2296 +#define QSYS_QMAXSDU_CFG_5_RSZ 0x4
2298 +#define QSYS_QMAXSDU_CFG_6_RSZ 0x4
2300 +#define QSYS_QMAXSDU_CFG_7_RSZ 0x4
2302 +#define QSYS_PREEMPTION_CFG_RSZ 0x4
2304 +#define QSYS_PREEMPTION_CFG_P_QUEUES(x) ((x) & GENMASK(7, 0))
2305 +#define QSYS_PREEMPTION_CFG_P_QUEUES_M GENMASK(7, 0)
2306 +#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x) (((x) << 8) & GENMASK(9, 8))
2307 +#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M GENMASK(9, 8)
2308 +#define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x) (((x) & GENMASK(9, 8)) >> 8)
2309 +#define QSYS_PREEMPTION_CFG_STRICT_IPG(x) (((x) << 12) & GENMASK(13, 12))
2310 +#define QSYS_PREEMPTION_CFG_STRICT_IPG_M GENMASK(13, 12)
2311 +#define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x) (((x) & GENMASK(13, 12)) >> 12)
2312 +#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x) (((x) << 16) & GENMASK(31, 16))
2313 +#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M GENMASK(31, 16)
2314 +#define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x) (((x) & GENMASK(31, 16)) >> 16)
2316 +#define QSYS_CIR_CFG_GSZ 0x80
2318 +#define QSYS_CIR_CFG_CIR_RATE(x) (((x) << 6) & GENMASK(20, 6))
2319 +#define QSYS_CIR_CFG_CIR_RATE_M GENMASK(20, 6)
2320 +#define QSYS_CIR_CFG_CIR_RATE_X(x) (((x) & GENMASK(20, 6)) >> 6)
2321 +#define QSYS_CIR_CFG_CIR_BURST(x) ((x) & GENMASK(5, 0))
2322 +#define QSYS_CIR_CFG_CIR_BURST_M GENMASK(5, 0)
2324 +#define QSYS_EIR_CFG_GSZ 0x80
2326 +#define QSYS_EIR_CFG_EIR_RATE(x) (((x) << 7) & GENMASK(21, 7))
2327 +#define QSYS_EIR_CFG_EIR_RATE_M GENMASK(21, 7)
2328 +#define QSYS_EIR_CFG_EIR_RATE_X(x) (((x) & GENMASK(21, 7)) >> 7)
2329 +#define QSYS_EIR_CFG_EIR_BURST(x) (((x) << 1) & GENMASK(6, 1))
2330 +#define QSYS_EIR_CFG_EIR_BURST_M GENMASK(6, 1)
2331 +#define QSYS_EIR_CFG_EIR_BURST_X(x) (((x) & GENMASK(6, 1)) >> 1)
2332 +#define QSYS_EIR_CFG_EIR_MARK_ENA BIT(0)
2334 +#define QSYS_SE_CFG_GSZ 0x80
2336 +#define QSYS_SE_CFG_SE_DWRR_CNT(x) (((x) << 6) & GENMASK(9, 6))
2337 +#define QSYS_SE_CFG_SE_DWRR_CNT_M GENMASK(9, 6)
2338 +#define QSYS_SE_CFG_SE_DWRR_CNT_X(x) (((x) & GENMASK(9, 6)) >> 6)
2339 +#define QSYS_SE_CFG_SE_RR_ENA BIT(5)
2340 +#define QSYS_SE_CFG_SE_AVB_ENA BIT(4)
2341 +#define QSYS_SE_CFG_SE_FRM_MODE(x) (((x) << 2) & GENMASK(3, 2))
2342 +#define QSYS_SE_CFG_SE_FRM_MODE_M GENMASK(3, 2)
2343 +#define QSYS_SE_CFG_SE_FRM_MODE_X(x) (((x) & GENMASK(3, 2)) >> 2)
2344 +#define QSYS_SE_CFG_SE_EXC_ENA BIT(1)
2345 +#define QSYS_SE_CFG_SE_EXC_FWD BIT(0)
2347 +#define QSYS_SE_DWRR_CFG_GSZ 0x80
2348 +#define QSYS_SE_DWRR_CFG_RSZ 0x4
2350 +#define QSYS_SE_CONNECT_GSZ 0x80
2352 +#define QSYS_SE_CONNECT_SE_OUTP_IDX(x) (((x) << 17) & GENMASK(24, 17))
2353 +#define QSYS_SE_CONNECT_SE_OUTP_IDX_M GENMASK(24, 17)
2354 +#define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x) (((x) & GENMASK(24, 17)) >> 17)
2355 +#define QSYS_SE_CONNECT_SE_INP_IDX(x) (((x) << 9) & GENMASK(16, 9))
2356 +#define QSYS_SE_CONNECT_SE_INP_IDX_M GENMASK(16, 9)
2357 +#define QSYS_SE_CONNECT_SE_INP_IDX_X(x) (((x) & GENMASK(16, 9)) >> 9)
2358 +#define QSYS_SE_CONNECT_SE_OUTP_CON(x) (((x) << 5) & GENMASK(8, 5))
2359 +#define QSYS_SE_CONNECT_SE_OUTP_CON_M GENMASK(8, 5)
2360 +#define QSYS_SE_CONNECT_SE_OUTP_CON_X(x) (((x) & GENMASK(8, 5)) >> 5)
2361 +#define QSYS_SE_CONNECT_SE_INP_CNT(x) (((x) << 1) & GENMASK(4, 1))
2362 +#define QSYS_SE_CONNECT_SE_INP_CNT_M GENMASK(4, 1)
2363 +#define QSYS_SE_CONNECT_SE_INP_CNT_X(x) (((x) & GENMASK(4, 1)) >> 1)
2364 +#define QSYS_SE_CONNECT_SE_TERMINAL BIT(0)
2366 +#define QSYS_SE_DLB_SENSE_GSZ 0x80
2368 +#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x) (((x) << 11) & GENMASK(13, 11))
2369 +#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M GENMASK(13, 11)
2370 +#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x) (((x) & GENMASK(13, 11)) >> 11)
2371 +#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x) (((x) << 7) & GENMASK(10, 7))
2372 +#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M GENMASK(10, 7)
2373 +#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x) (((x) & GENMASK(10, 7)) >> 7)
2374 +#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x) (((x) << 3) & GENMASK(6, 3))
2375 +#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M GENMASK(6, 3)
2376 +#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x) (((x) & GENMASK(6, 3)) >> 3)
2377 +#define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA BIT(2)
2378 +#define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA BIT(1)
2379 +#define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA BIT(0)
2381 +#define QSYS_CIR_STATE_GSZ 0x80
2383 +#define QSYS_CIR_STATE_CIR_LVL(x) (((x) << 4) & GENMASK(25, 4))
2384 +#define QSYS_CIR_STATE_CIR_LVL_M GENMASK(25, 4)
2385 +#define QSYS_CIR_STATE_CIR_LVL_X(x) (((x) & GENMASK(25, 4)) >> 4)
2386 +#define QSYS_CIR_STATE_SHP_TIME(x) ((x) & GENMASK(3, 0))
2387 +#define QSYS_CIR_STATE_SHP_TIME_M GENMASK(3, 0)
2389 +#define QSYS_EIR_STATE_GSZ 0x80
2391 +#define QSYS_SE_STATE_GSZ 0x80
2393 +#define QSYS_SE_STATE_SE_OUTP_LVL(x) (((x) << 1) & GENMASK(2, 1))
2394 +#define QSYS_SE_STATE_SE_OUTP_LVL_M GENMASK(2, 1)
2395 +#define QSYS_SE_STATE_SE_OUTP_LVL_X(x) (((x) & GENMASK(2, 1)) >> 1)
2396 +#define QSYS_SE_STATE_SE_WAS_YEL BIT(0)
2398 +#define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD BIT(8)
2399 +#define QSYS_HSCH_MISC_CFG_FRM_ADJ(x) (((x) << 3) & GENMASK(7, 3))
2400 +#define QSYS_HSCH_MISC_CFG_FRM_ADJ_M GENMASK(7, 3)
2401 +#define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x) (((x) & GENMASK(7, 3)) >> 3)
2402 +#define QSYS_HSCH_MISC_CFG_LEAK_DIS BIT(2)
2403 +#define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA BIT(1)
2404 +#define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD BIT(0)
2406 +#define QSYS_TAG_CONFIG_RSZ 0x4
2408 +#define QSYS_TAG_CONFIG_ENABLE BIT(0)
2409 +#define QSYS_TAG_CONFIG_LINK_SPEED(x) (((x) << 4) & GENMASK(5, 4))
2410 +#define QSYS_TAG_CONFIG_LINK_SPEED_M GENMASK(5, 4)
2411 +#define QSYS_TAG_CONFIG_LINK_SPEED_X(x) (((x) & GENMASK(5, 4)) >> 4)
2412 +#define QSYS_TAG_CONFIG_INIT_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
2413 +#define QSYS_TAG_CONFIG_INIT_GATE_STATE_M GENMASK(15, 8)
2414 +#define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
2415 +#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x) (((x) << 16) & GENMASK(23, 16))
2416 +#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M GENMASK(23, 16)
2417 +#define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x) (((x) & GENMASK(23, 16)) >> 16)
2419 +#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x) ((x) & GENMASK(7, 0))
2420 +#define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M GENMASK(7, 0)
2421 +#define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q BIT(8)
2422 +#define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE BIT(16)
2424 +#define QSYS_PORT_MAX_SDU_RSZ 0x4
2426 +#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
2427 +#define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
2428 +#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
2429 +#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M GENMASK(31, 16)
2430 +#define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
2432 +#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
2433 +#define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
2434 +#define QSYS_GCL_CFG_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
2435 +#define QSYS_GCL_CFG_REG_1_GATE_STATE_M GENMASK(15, 8)
2436 +#define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
2438 +#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
2439 +#define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M GENMASK(15, 0)
2440 +#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x) (((x) << 16) & GENMASK(31, 16))
2441 +#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M GENMASK(31, 16)
2442 +#define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x) (((x) & GENMASK(31, 16)) >> 16)
2444 +#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x) ((x) & GENMASK(15, 0))
2445 +#define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M GENMASK(15, 0)
2446 +#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x) (((x) << 16) & GENMASK(23, 16))
2447 +#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M GENMASK(23, 16)
2448 +#define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x) (((x) & GENMASK(23, 16)) >> 16)
2449 +#define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING BIT(24)
2451 +#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x) ((x) & GENMASK(5, 0))
2452 +#define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M GENMASK(5, 0)
2453 +#define QSYS_GCL_STATUS_REG_1_GATE_STATE(x) (((x) << 8) & GENMASK(15, 8))
2454 +#define QSYS_GCL_STATUS_REG_1_GATE_STATE_M GENMASK(15, 8)
2455 +#define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x) (((x) & GENMASK(15, 8)) >> 8)
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